| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 566 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
569 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
570 SuperReg = Reg; in FindSuitableFreeRegisters()
592 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
593 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
608 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
622 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
644 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
655 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
658 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 78 Register SuperReg; member
113 : SuperReg(MI->getOperand(0).getReg()), MI(MI), in SGPRSpillBuilder()
132 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in SGPRSpillBuilder()
133 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
184 RS->setRegUsed(SuperReg); in prepare()
1323 ? SB.SuperReg in spillSGPR()
1340 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1368 ? SB.SuperReg in spillSGPR()
1418 ? SB.SuperReg in restoreSGPR()
1427 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
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| H A D | SIInstrInfo.h | 64 MachineOperand &SuperReg,
70 MachineOperand &SuperReg,
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| H A D | SIInstrInfo.cpp | 4531 MachineOperand &SuperReg, in buildExtractSubReg() argument
4540 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
4542 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
4553 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 193 SDValue SuperReg = SDValue(Load, 0); in selectVLSEG() local
197 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
236 SDValue SuperReg = SDValue(Load, 0); in selectVLSEGFF() local
240 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
284 SDValue SuperReg = SDValue(Load, 0); in selectVLXSEG() local
288 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLXSEG()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1381 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1384 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1417 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1419 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1423 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1476 SDValue SuperReg = SDValue(Load, 0); in SelectPredicatedLoad() local
1479 AArch64::zsub0 + i, DL, VT, SuperReg)); in SelectPredicatedLoad()
1628 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1677 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1680 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2201 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
2451 SDValue SuperReg; in SelectVLDSTLane() local
2456 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2458 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2465 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2467 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2469 Ops.push_back(SuperReg); in SelectVLDSTLane()
2485 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
3018 SDValue SuperReg = SDValue(VLdA, 0); in SelectVLDDup() local
3020 const SDValue OpsB[] = { MemAddr, Align, SuperReg, Pred, Reg0, Chain }; in SelectVLDDup()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1690 MCRegister SuperReg = in copyPhysReg() local
1693 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
1696 DestReg = SuperReg; in copyPhysReg()
1699 MCRegister SuperReg = in copyPhysReg() local
1702 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
1705 SrcReg = SuperReg; in copyPhysReg()
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