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Searched refs:TRC (Results 1 – 25 of 38) sorted by relevance

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/netbsd/usr.bin/banner/
H A Dbanner.c104 #define TRC(q) (((q)-' ')&0177) macro
112 case TRC('_'): in dropit()
113 case TRC(';'): in dropit()
114 case TRC(','): in dropit()
115 case TRC('g'): in dropit()
116 case TRC('j'): in dropit()
117 case TRC('p'): in dropit()
118 case TRC('q'): in dropit()
119 case TRC('y'): in dropit()
144 d = dropit(c = TRC(cc)); in scan_out()
/netbsd/external/gpl3/gdb/dist/sim/m32c/
H A Dreg.c599 #define TRC(f,n, id) \ macro
614 TRC (r[0].r_r0, "r0", r0); in trace_register_changes()
615 TRC (r[0].r_r1, "r1", r1); in trace_register_changes()
616 TRC (r[0].r_r2, "r2", r2); in trace_register_changes()
617 TRC (r[0].r_r3, "r3", r3); in trace_register_changes()
618 TRC (r[0].r_a0, "a0", a0); in trace_register_changes()
619 TRC (r[0].r_a1, "a1", a1); in trace_register_changes()
620 TRC (r[0].r_sb, "sb", sb); in trace_register_changes()
632 TRC (r_usp, "usp", usp); in trace_register_changes()
633 TRC (r_isp, "isp", isp); in trace_register_changes()
[all …]
/netbsd/external/gpl3/gdb.old/dist/sim/m32c/
H A Dreg.c599 #define TRC(f,n, id) \ macro
614 TRC (r[0].r_r0, "r0", r0); in trace_register_changes()
615 TRC (r[0].r_r1, "r1", r1); in trace_register_changes()
616 TRC (r[0].r_r2, "r2", r2); in trace_register_changes()
617 TRC (r[0].r_r3, "r3", r3); in trace_register_changes()
618 TRC (r[0].r_a0, "a0", a0); in trace_register_changes()
619 TRC (r[0].r_a1, "a1", a1); in trace_register_changes()
620 TRC (r[0].r_sb, "sb", sb); in trace_register_changes()
632 TRC (r_usp, "usp", usp); in trace_register_changes()
633 TRC (r_isp, "isp", isp); in trace_register_changes()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp74 unsigned Lane, const TargetRegisterClass *TRC);
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) { in usesRegClass() argument
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
141 return TRC->contains(Reg); in usesRegClass()
270 const TargetRegisterClass *TRC = in optimizeSDPattern() local
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
434 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
435 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
H A DARMLoadStoreOptimizer.cpp2435 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2436 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2437 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2786 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local
2787 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
2789 TRC = TII->getRegClass(MCID, 2, TRI, *MF); in createPostIncLoadStore()
2790 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
H A DARMISelLowering.cpp10306 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock()
10411 NewVReg6 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock()
10443 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock()
10737 const TargetRegisterClass *TRC = nullptr; in EmitStructByval() local
10840 Register varEnd = MRI.createVirtualRegister(TRC); in EmitStructByval()
10844 Vtmp = MRI.createVirtualRegister(TRC); in EmitStructByval()
10888 Register varLoop = MRI.createVirtualRegister(TRC); in EmitStructByval()
10889 Register varPhi = MRI.createVirtualRegister(TRC); in EmitStructByval()
10890 Register srcLoop = MRI.createVirtualRegister(TRC); in EmitStructByval()
10891 Register srcPhi = MRI.createVirtualRegister(TRC); in EmitStructByval()
[all …]
/netbsd/external/gpl3/gdb/dist/sim/rx/
H A Dreg.c509 #define TRC(f,n) \ macro
528 TRC (r[i], reg_names[i]); in trace_register_changes()
529 TRC (r_intb, "intb"); in trace_register_changes()
530 TRC (r_usp, "usp"); in trace_register_changes()
531 TRC (r_isp, "isp"); in trace_register_changes()
/netbsd/external/gpl3/gdb.old/dist/sim/rx/
H A Dreg.c509 #define TRC(f,n) \ macro
528 TRC (r[i], reg_names[i]); in trace_register_changes()
529 TRC (r_intb, "intb"); in trace_register_changes()
530 TRC (r_usp, "usp"); in trace_register_changes()
531 TRC (r_isp, "isp"); in trace_register_changes()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp106 const TargetRegisterClass &TRC) const { in getRegisterOrder()
107 for (unsigned i = 0; i < TRC.getNumRegs(); ++i) { in getRegisterOrder()
108 if (regsOverlap(Reg, TRC.getRegister(i))) { in getRegisterOrder()
H A DM68kRegisterInfo.h77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
/netbsd/usr.sbin/lpr/lpd/
H A Dprintjob.c1063 #define TRC(q) (((q)-' ')&0177) macro
1078 d = dropit(c = TRC(cc = *sp++)); in scan_out()
1104 case TRC('_'): in dropit()
1105 case TRC(';'): in dropit()
1106 case TRC(','): in dropit()
1107 case TRC('g'): in dropit()
1108 case TRC('j'): in dropit()
1109 case TRC('p'): in dropit()
1110 case TRC('q'): in dropit()
1111 case TRC('y'): in dropit()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp498 const TargetRegisterClass *TRC = in EmitSubregNode() local
517 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
523 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
537 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
656 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp62 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
65 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp496 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
497 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
H A DRegAllocPBQP.cpp617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
625 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
H A DLiveDebugVariables.cpp1437 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local
1438 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
/netbsd/external/apache2/llvm/dist/clang/include/clang/AST/
H A DASTNodeTraverser.h405 if (const Expr *TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local
406 Visit(TRC); in VisitFunctionDecl()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h1125 const TargetRegisterClass &TRC, in isOfRegClass() argument
1129 return RC == &TRC; in isOfRegClass()
1131 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp563 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
565 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
/netbsd/external/apache2/llvm/dist/clang/lib/Sema/
H A DSemaTemplateVariadic.cpp966 if (Expr *TRC = D.getTrailingRequiresClause()) in containsUnexpandedParameterPacks() local
967 if (TRC->containsUnexpandedParameterPack()) in containsUnexpandedParameterPacks()
/netbsd/external/apache2/llvm/dist/clang/include/clang/Sema/
H A DDeclSpec.h2466 void setTrailingRequiresClause(Expr *TRC) { in setTrailingRequiresClause() argument
2467 TrailingRequiresClause = TRC; in setTrailingRequiresClause()
2469 SetRangeEnd(TRC->getEndLoc()); in setTrailingRequiresClause()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h71 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() argument
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp943 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
946 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
/netbsd/external/apache2/llvm/dist/clang/lib/AST/
H A DDeclTemplate.cpp232 if (const Expr *TRC = FD->getTrailingRequiresClause()) in getAssociatedConstraints() local
233 AC.push_back(TRC); in getAssociatedConstraints()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp2015 const TargetRegisterClass *TRC; in createVR() local
2017 TRC = &Hexagon::PredRegsRegClass; in createVR()
2019 TRC = &Hexagon::IntRegsRegClass; in createVR()
2021 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
2026 Register NewReg = MRI.createVirtualRegister(TRC); in createVR()

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