Searched refs:TTM_PL_FLAG_TT (Results 1 – 11 of 11) sorted by relevance
76 flags = TTM_PL_FLAG_TT; in nouveau_gem_prime_import_sg_table()116 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_TT, false); in nouveau_gem_prime_pin()
268 if ((flags & TTM_PL_FLAG_TT) && in nouveau_bo_alloc()353 if (type & TTM_PL_FLAG_TT) in set_placement_list()354 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; in set_placement_list()445 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); in nouveau_bo_pin()813 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, in nouveau_bo_evict_flags()1326 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING in nouveau_bo_move_flipd()1363 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING in nouveau_bo_move_flips()
189 flags |= TTM_PL_FLAG_TT; in nouveau_gem_new()314 valid_flags |= TTM_PL_FLAG_TT; in nouveau_gem_set_domain()322 pref_flags |= TTM_PL_FLAG_TT; in nouveau_gem_set_domain()328 pref_flags |= TTM_PL_FLAG_TT; in nouveau_gem_set_domain()
213 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; in nv84_fence_create()
336 ret = nouveau_bo_pin(chan->ntfy, TTM_PL_FLAG_TT, false); in nouveau_abi16_ioctl_channel_alloc()
149 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; in nouveau_channel_prep()
48 #define TTM_PL_FLAG_TT (1 << TTM_PL_TT) macro
137 TTM_PL_FLAG_TT; in radeon_ttm_placement_from_domain()144 TTM_PL_FLAG_TT; in radeon_ttm_placement_from_domain()148 TTM_PL_FLAG_TT; in radeon_ttm_placement_from_domain()
293 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; in radeon_move_vram_ram()338 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; in radeon_move_ram_vram()
518 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; in amdgpu_move_vram_ram()574 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; in amdgpu_move_ram_vram()1187 TTM_PL_FLAG_TT; in amdgpu_ttm_alloc_gart()
161 places[c].flags = TTM_PL_FLAG_TT; in amdgpu_bo_placement_from_domain()