| /netbsd/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| H A D | InOrderIssueStage.cpp | 179 SmallVectorImpl<unsigned> &UsedRegs) { in addRegisterReadWrite() argument
186 PRF.addRegisterWrite(WriteRef(SourceIndex, &WS), UsedRegs); in addRegisterReadWrite()
202 const SmallVectorImpl<unsigned> &UsedRegs, in notifyInstructionDispatch() argument
206 HWInstructionDispatchedEvent(IR, UsedRegs, Ops)); in notifyInstructionDispatch()
237 SmallVector<unsigned, 4> UsedRegs(PRF.getNumRegisterFiles()); in tryIssue() local
238 addRegisterReadWrite(PRF, IS, SourceIndex, STI, UsedRegs); in tryIssue()
241 notifyInstructionDispatch(IR, NumMicroOps, UsedRegs, *this); in tryIssue()
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| H A D | DispatchStage.cpp | 39 ArrayRef<unsigned> UsedRegs, in notifyInstructionDispatched() argument
43 HWInstructionDispatchedEvent(IR, UsedRegs, UOps)); in notifyInstructionDispatched()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86CallFrameOptimization.cpp | 115 DenseSet<unsigned int> &UsedRegs);
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
344 for (unsigned int U : UsedRegs) in classifyInstruction()
409 DenseSet<unsigned int> UsedRegs; in collectCallInfo() local
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
458 UsedRegs.insert(Reg); in collectCallInfo()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 584 const LivePhysRegs &UsedRegs, unsigned &PopReg, in findTemporariesForLR() argument
588 if (!UsedRegs.contains(Reg)) { in findTemporariesForLR()
655 LivePhysRegs UsedRegs(TRI); in emitPopSpecialFixUp() local
656 UsedRegs.addLiveOuts(MBB); in emitPopSpecialFixUp()
663 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
672 UsedRegs.stepBackward(*--InstUpToMBBI); in emitPopSpecialFixUp()
696 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
706 UsedRegs.stepBackward(*PrevMBBI); in emitPopSpecialFixUp()
707 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
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| H A D | ARMFastISel.cpp | 226 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2017 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, in FinishCall() argument
2044 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2045 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2063 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2279 SmallVector<Register, 4> UsedRegs; in ARMEmitLibcall() local
2280 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; in ARMEmitLibcall()
2283 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
2423 SmallVector<Register, 4> UsedRegs; in SelectCall() local
2424 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) in SelectCall()
[all …]
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| H A D | ARMLoadStoreOptimizer.cpp | 865 DenseSet<unsigned> UsedRegs; in MergeOpsUpdate() local
874 UsedRegs.insert(Reg); in MergeOpsUpdate()
966 if (UsedRegs.count(MO.getReg())) in MergeOpsUpdate()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 38 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
63 UsedRegs[*AI / 32] |= 1 << (*AI & 31); in MarkAllocated()
68 UsedRegs[*AI / 32] &= ~(1 << (*AI & 31)); in MarkUnallocated()
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| H A D | MachineBasicBlock.cpp | 1081 SmallVector<Register, 4> UsedRegs; in SplitCriticalEdge() local
1093 if (!is_contained(UsedRegs, Reg)) in SplitCriticalEdge()
1094 UsedRegs.push_back(Reg); in SplitCriticalEdge()
1234 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); in SplitCriticalEdge()
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| H A D | MachineInstr.cpp | 2044 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, in setPhysRegsDeadExcept() argument
2057 if (llvm::none_of(UsedRegs, in setPhysRegsDeadExcept()
2065 for (const Register &UsedReg : UsedRegs) in setPhysRegsDeadExcept()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 1026 SmallVector<Register, 8> UsedRegs; in EmitMachineNode() local
1035 UsedRegs.push_back(Reg); in EmitMachineNode()
1044 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
1052 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
1060 UsedRegs.push_back(Reg); in EmitMachineNode()
1066 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef()) in EmitMachineNode()
1067 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | VarLocBasedImpl.cpp | 827 SmallVectorImpl<Register> &UsedRegs) const;
1158 SmallVectorImpl<Register> &UsedRegs) const { in getUsedRegs()
1171 assert((UsedRegs.empty() || FoundReg != UsedRegs.back()) && in getUsedRegs()
1173 UsedRegs.push_back(FoundReg); in getUsedRegs()
1491 SmallVector<Register, 32> UsedRegs; in transferRegisterDef() local
1492 getUsedRegs(OpenRanges.getVarLocs(), UsedRegs); in transferRegisterDef()
1493 for (Register Reg : UsedRegs) { in transferRegisterDef()
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| H A D | InstrRefBasedImpl.cpp | 2219 BitVector UsedRegs(TRI->getNumRegs()); in produceMLocTransferFunction() local
2224 UsedRegs.set(ID); in produceMLocTransferFunction()
2233 BV &= UsedRegs; in produceMLocTransferFunction()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 203 SmallVector<uint32_t, 16> UsedRegs; variable
278 return UsedRegs[Reg / 32] & (1 << (Reg & 31)); in isAllocated()
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| H A D | MachineInstr.h | 508 SmallSet<Register, 4> UsedRegs;
511 UsedRegs.insert(MO.getReg());
512 return UsedRegs;
1602 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
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