Searched refs:V30 (Results 1 – 12 of 12) sorted by relevance
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.td | 61 CCAssignToReg<[V24, V26, V28, V30, V25, V27, V29, V31]>>>
125 CCIfFixed<CCAssignToReg<[V24, V26, V28, V30,
200 CCAssignToReg<[V24, V25, V26, V27, V28, V29, V30, V31]>>>
251 V28, V29, V30, V31]>>>>,
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| /netbsd/external/gpl3/gdb/dist/sim/aarch64/ |
| H A D | cpustate.h | 122 V30, enumerator
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| /netbsd/external/gpl3/gdb.old/dist/sim/aarch64/ |
| H A D | cpustate.h | 122 V30, enumerator
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 110 SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 83 V28, V29, V30, V31, 0 in getCallerSavedRegs()
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| H A D | HexagonRegisterInfo.td | 222 def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>;
242 def WR15: Rd<31, "v30:31", [V30, V31, VFR15]>, DwarfRegNum<[176]>;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 268 V28, V29, V30, V31)>;
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| H A D | PPCRegisterInfo.td | 347 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
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| H A D | PPCFrameLowering.cpp | 162 {PPC::V30, -32}, \ in getCalleeSavedSpillSlots()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 102 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 583 Hexagon::V30, Hexagon::V31}; in DecodeHvxVRRegisterClass()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8193 .Case("{v30}", RISCV::V30) in getRegForInlineAsmConstraint()
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