Searched refs:VECREDUCE_SMAX (Results 1 – 14 of 14) sorted by relevance
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1224 VECREDUCE_SMAX, enumerator
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 482 case ISD::VECREDUCE_SMAX: in LegalizeOp()
886 case ISD::VECREDUCE_SMAX: in Expand()
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| H A D | SelectionDAGDumper.cpp | 475 case ISD::VECREDUCE_SMAX: return "vecreduce_smax"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 213 case ISD::VECREDUCE_SMAX: in PromoteIntegerResult()
1555 case ISD::VECREDUCE_SMAX: in PromoteIntegerOperand()
2005 case ISD::VECREDUCE_SMAX: in PromoteIntOp_VECREDUCE()
2203 case ISD::VECREDUCE_SMAX: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 656 case ISD::VECREDUCE_SMAX: in ScalarizeVectorOperand()
2221 case ISD::VECREDUCE_SMAX: in SplitVectorOperand()
4574 case ISD::VECREDUCE_SMAX: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1172 case ISD::VECREDUCE_SMAX: in LegalizeOp()
3773 case ISD::VECREDUCE_SMAX: in ExpandNode()
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| H A D | SelectionDAG.cpp | 388 case ISD::VECREDUCE_SMAX: in getVecReduceBaseOpcode()
5016 case ISD::VECREDUCE_SMAX: in getNode()
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| H A D | SelectionDAGBuilder.cpp | 9306 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); in visitVectorReduce()
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| H A D | DAGCombiner.cpp | 1733 case ISD::VECREDUCE_SMAX: in visit()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 429 setOperationAction(ISD::VECREDUCE_SMAX, MVT::i64, Custom); in RISCVTargetLowering()
503 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in RISCVTargetLowering()
719 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in RISCVTargetLowering()
2285 case ISD::VECREDUCE_SMAX: in LowerOperation()
3496 case ISD::VECREDUCE_SMAX: in getRVVReductionOp()
5080 case ISD::VECREDUCE_SMAX: in ReplaceNodeResults()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 832 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); in initActions()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1058 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in AArch64TargetLowering()
1159 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in AArch64TargetLowering()
1319 setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom); in AArch64TargetLowering()
1520 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in addTypeForFixedLengthSVE()
4644 case ISD::VECREDUCE_SMAX: in LowerOperation()
10611 case ISD::VECREDUCE_SMAX: in LowerVECREDUCE()
10637 case ISD::VECREDUCE_SMAX: in LowerVECREDUCE()
16698 case ISD::VECREDUCE_SMAX: in ReplaceNodeResults()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 448 def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 298 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal); in addMVEVectorTypes()
12519 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_SMAX || in PerformSELECTCombine()
12520 FalseVal->getOpcode() == ISD::VECREDUCE_SMAX) && in PerformSELECTCombine()
12533 case ISD::VECREDUCE_SMAX: in PerformSELECTCombine()
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