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Searched refs:VM_L2_CNTL2 (Results 1 – 17 of 17) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfxhub_v1_0.c162 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
H A Damdgpu_mmhub_v1_0.c182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
H A Damdgpu_gmc_v7_0.c656 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
657 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
H A Damdgpu_gmc_v8_0.c878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
H A Dsid.h382 #define VM_L2_CNTL2 0x501 macro
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_rv770.c918 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
964 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable()
995 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
H A Drv770d.h649 #define VM_L2_CNTL2 0x1404 macro
H A Dnid.h119 #define VM_L2_CNTL2 0x1404 macro
H A Dradeon_ni.c1307 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
1386 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
H A Dsid.h380 #define VM_L2_CNTL2 0x1404 macro
H A Dcikd.h498 #define VM_L2_CNTL2 0x1404 macro
H A Dradeon_evergreen.c2420 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2473 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2503 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
H A Devergreend.h1157 #define VM_L2_CNTL2 0x1404 macro
H A Dr600d.h594 #define VM_L2_CNTL2 0x1404 macro
H A Dradeon_r600.c1179 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable()
1271 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
H A Dradeon_si.c4318 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
4404 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
H A Dradeon_cik.c5472 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5589 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()