Searched refs:VM_L2_CNTL2 (Results 1 – 17 of 17) sorted by relevance
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_gfxhub_v1_0.c | 162 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs() 163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
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H A D | amdgpu_mmhub_v1_0.c | 182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs() 183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
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H A D | amdgpu_gmc_v7_0.c | 656 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable() 657 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
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H A D | amdgpu_gmc_v8_0.c | 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable() 879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
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H A D | sid.h | 382 #define VM_L2_CNTL2 0x501 macro
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_rv770.c | 918 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable() 964 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable() 995 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
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H A D | rv770d.h | 649 #define VM_L2_CNTL2 0x1404 macro
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H A D | nid.h | 119 #define VM_L2_CNTL2 0x1404 macro
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H A D | radeon_ni.c | 1307 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable() 1386 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
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H A D | sid.h | 380 #define VM_L2_CNTL2 0x1404 macro
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H A D | cikd.h | 498 #define VM_L2_CNTL2 0x1404 macro
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H A D | radeon_evergreen.c | 2420 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable() 2473 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable() 2503 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
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H A D | evergreend.h | 1157 #define VM_L2_CNTL2 0x1404 macro
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H A D | r600d.h | 594 #define VM_L2_CNTL2 0x1404 macro
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H A D | radeon_r600.c | 1179 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable() 1271 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
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H A D | radeon_si.c | 4318 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable() 4404 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
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H A D | radeon_cik.c | 5472 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable() 5589 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
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