| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
277 .addReg(VR1, RegState::Kill); in expandCopyACC()
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| H A D | MipsSEISelLowering.cpp | 3073 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3074 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3082 .addReg(VR1) in emitBPOSGE32()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 224 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
225 return operator[](VR1) < operator[](VR2); in operator ()()
299 bool operator() (unsigned VR1, unsigned VR2) const;
317 bool operator() (unsigned VR1, unsigned VR2) const;
328 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
338 if (VR1 == VR2) in operator ()()
341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
352 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
356 if (VR1 == VR2) in operator ()()
358 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()()
[all …]
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| /netbsd/external/gpl3/gdb/dist/opcodes/ |
| H A D | v850-opc.c | 1266 #define VR1 (VECTOR5 + 1) macro
1269 #define VR2 (VR1 + 1)
1758 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
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| /netbsd/external/gpl3/binutils.old/dist/opcodes/ |
| H A D | v850-opc.c | 1272 #define VR1 (VECTOR5 + 1) macro
1275 #define VR2 (VR1 + 1)
1764 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
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| /netbsd/external/gpl3/binutils/dist/opcodes/ |
| H A D | v850-opc.c | 1266 #define VR1 (VECTOR5 + 1) macro
1269 #define VR2 (VR1 + 1)
1758 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
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| /netbsd/external/gpl3/gdb.old/dist/opcodes/ |
| H A D | v850-opc.c | 1266 #define VR1 (VECTOR5 + 1) macro
1269 #define VR2 (VR1 + 1)
1758 { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
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| /netbsd/external/gpl3/gcc/dist/gcc/ |
| H A D | ChangeLog-2005 | 3891 than VR1 or vice-versa.
5677 sets VR0->EQUIV and VR1->EQUIV when meeting a range and an
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