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Searched refs:VT1 (Results 1 – 22 of 22) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h89 static int ValCompare(const PassNameParser::OptionInfo *VT1, in ValCompare() argument
91 return VT1->Name.compare(VT2->Name); in ValCompare()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteOutArguments.cpp193 auto *VT1 = dyn_cast<FixedVectorType>(Ty1); in isVec3ToVec4Shuffle() local
194 if (!VT0 || !VT1) in isVec3ToVec4Shuffle()
198 VT1->getNumElements() != 4) in isVec3ToVec4Shuffle()
202 DL->getTypeSizeInBits(VT1->getElementType()); in isVec3ToVec4Shuffle()
H A DAMDGPUISelLowering.h167 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.h137 bool isTruncateFree(EVT VT1, EVT VT2) const override;
141 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DBPFISelLowering.cpp199 bool BPFTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
200 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
202 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
215 bool BPFTargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
216 if (!getHasAlu32() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
218 unsigned NumBits1 = VT1.getSizeInBits(); in isZExtFree()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h603 SDVTList getVTList(EVT VT1, EVT VT2);
604 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
605 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
1405 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1406 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1408 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1410 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1440 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1442 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1444 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
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H A DTargetLowering.h1454 EVT VT1; in getRegisterType() local
1457 (void)getVectorTypeBreakdown(Context, VT, VT1, in getRegisterType()
1482 EVT VT1; in getNumRegisters() local
1485 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); in getNumRegisters()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h117 bool isTruncateFree(EVT VT1, EVT VT2) const override;
128 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1396 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
1397 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1400 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
1408 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
1410 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp8069 ID.AddInteger(VT1.getRawBits()); in getVTList()
8076 Array[0] = VT1; in getVTList()
8087 ID.AddInteger(VT1.getRawBits()); in getVTList()
8095 Array[0] = VT1; in getVTList()
8107 ID.AddInteger(VT1.getRawBits()); in getVTList()
8116 Array[0] = VT1; in getVTList()
8329 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
8335 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
8349 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
8537 SDVTList VTs = getVTList(VT1, VT2); in getMachineNode()
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H A DLegalizeVectorTypes.cpp4307 EVT VT1 = getSetCCResultType(getSETCCOperandType(SETCC1)); in WidenVSELECTMask() local
4309 unsigned ScalarBits1 = VT1.getScalarSizeInBits(); in WidenVSELECTMask()
4316 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTMask()
4317 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask()
4330 SETCC1 = convertMask(SETCC1, VT1, MaskVT); in WidenVSELECTMask()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h1203 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1216 bool isZExtFree(EVT VT1, EVT VT2) const override;
1236 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DX86ISelLowering.cpp31820 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
31836 EVT VT1 = Val.getValueType(); in isZExtFree() local
31837 if (isZExtFree(VT1, VT2)) in isZExtFree()
31843 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
31847 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()
31928 return !(VT1 == MVT::i32 && VT2 == MVT::i16); in isNarrowingProfitable()
35581 MVT VT1 = V1.getSimpleValueType(); in combineX86ShuffleChain() local
35583 assert(VT1.getSizeInBits() == RootSizeInBits && in combineX86ShuffleChain()
35623 if (VT1 == VT2 && VT1.getSizeInBits() == RootSizeInBits) { in combineX86ShuffleChain()
35625 unsigned NumElts = VT1.getVectorNumElements(); in combineX86ShuffleChain()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h572 bool isTruncateFree(EVT VT1, EVT VT2) const override;
577 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DAArch64ISelLowering.cpp10981 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
10983 uint64_t NumBits1 = VT1.getFixedSizeInBits(); in isTruncateFree()
11025 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
11026 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
11028 unsigned NumBits1 = VT1.getSizeInBits(); in isZExtFree()
11034 EVT VT1 = Val.getValueType(); in isZExtFree() local
11035 if (isZExtFree(VT1, VT2)) { in isZExtFree()
11043 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() && in isZExtFree()
11045 VT1.getSizeInBits() <= 32); in isZExtFree()
11974 EVT VT1 = VectorT1.getVectorElementType(); in performABSCombine() local
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp183 EVT VT1 = Val.getValueType(); in isZExtFree() local
184 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
188 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h133 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DHexagonISelLowering.cpp2080 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
2081 if (!VT1.isSimple() || !VT2.isSimple()) in isTruncateFree()
2083 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp76 for (MVT VT1 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h967 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DPPCISelLowering.cpp16094 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
16095 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
16097 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17259 EVT VT1 = Val.getValueType(); in isZExtFree() local
17260 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
17264 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()