/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_rs780_dpm.c | 266 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 270 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 293 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, in rs780_voltage_scaling_init() 315 WREG32_P(FVTHROT_CNTRL_REG, 0, in rs780_clk_scaling_enable() 344 WREG32_P(FVTHROT_FBDIV_REG2, in rs780_set_engine_clock_sc() 348 WREG32_P(FVTHROT_CNTRL_REG, in rs780_set_engine_clock_sc() 396 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_force_voltage() 400 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_force_voltage() 468 WREG32_P(FVTHROT_FBDIV_REG0, in rs780_set_engine_clock_scaling() 556 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_enable_voltage_scaling() [all …]
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H A D | radeon_r600_dpm.c | 382 WREG32_P(CG_TPC, TPU(u), ~TPU_MASK); in r600_set_tpu() 387 WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK); in r600_set_tpc() 397 WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK); in r600_set_sst() 407 WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK); in r600_set_fctu() 412 WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK); in r600_set_fct() 427 WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK); in r600_set_vddc3d_oorsu() 432 WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK); in r600_set_vddc3d_oorphc() 513 WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK); in r600_vid_rt_set_ssu() 584 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_voltage_index() 593 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_mem_clock_index() [all …]
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H A D | radeon_uvd_v1_0.c | 232 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init() 282 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start() 285 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start() 286 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start() 326 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start() 328 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start() 360 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v1_0_start() 402 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_stop() 403 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_stop() 414 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_stop() [all …]
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H A D | radeon_vce_v1_0.c | 227 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume() 229 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume() 232 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume() 235 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume() 257 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume() 300 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start() 316 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start() 318 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start() 326 WREG32_P(VCE_SOFT_RESET, 0, ~( in vce_v1_0_start() 345 WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET); in vce_v1_0_start() [all …]
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H A D | radeon_sumo_dpm.c | 133 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); in sumo_program_git() 180 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize() 186 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize() 485 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 488 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 491 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 494 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 570 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); in sumo_program_power_level() 911 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); in sumo_enable_sclk_ds() 917 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); in sumo_program_bootup_at() [all …]
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H A D | radeon_r600_hdmi.c | 191 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr() 197 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr() 200 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr() 204 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr() 207 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr() 211 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr() 214 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr() 315 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround() 375 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_audio_packet() 388 WREG32_P(HDMI0_60958_0 + offset, in r600_set_audio_packet() [all …]
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H A D | radeon_vce_v2_0.c | 167 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume() 168 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume() 169 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume() 173 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume() 195 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume() 197 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()
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H A D | radeon_dce3_1_afmt.c | 185 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr() 188 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr() 192 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr() 195 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr() 199 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr() 202 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()
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H A D | radeon_rv6xx_dpm.c | 322 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s() 360 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 362 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 378 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_enable_post_divider() 387 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_post_divider() 401 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_reference_divider() 407 WREG32_P(VID_RT, BRT(rt), ~BRT_MASK); in rv6xx_vid_response_set_brt() 998 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP); in rv6xx_enable_display_gap() 1181 WREG32_P(GENERAL_PWRMGT, 0, in rv6xx_enable_backbias() 1244 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE); in rv6xx_set_safe_backbias() [all …]
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H A D | radeon_rv770_dpm.c | 140 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable() 142 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable() 186 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv770_start_dpm() 188 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv770_start_dpm() 202 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv770_stop_dpm() 798 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv770_enable_spread_spectrum() 802 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv770_enable_spread_spectrum() 862 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in rv770_program_tp() 1343 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); in rv770_enable_voltage_control() 1372 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in rv770_enable_dynamic_pcie_gen2() [all …]
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H A D | radeon_cypress_dpm.c | 100 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2() 109 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 111 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 151 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable() 153 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in cypress_gfx_clock_gating_enable() 236 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); in cypress_enable_spread_spectrum() 238 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in cypress_enable_spread_spectrum() 240 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); in cypress_enable_spread_spectrum() 241 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN); in cypress_enable_spread_spectrum() 254 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in cypress_enable_sclk_control() [all …]
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H A D | radeon_rv770_smc.c | 399 WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); in rv770_start_smc() 404 WREG32_P(SMC_IO, 0, ~SMC_RST_N); in rv770_reset_smc() 409 WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); in rv770_stop_smc_clock() 414 WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); in rv770_start_smc_clock() 438 WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); in rv770_send_msg_to_smc()
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H A D | radeon_rv770.c | 66 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks() 72 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in rv770_set_uvd_clocks() 94 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks() 101 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks() 104 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); in rv770_set_uvd_clocks() 105 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks() 112 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks() 119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks() 124 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks() 125 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks() [all …]
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H A D | radeon_ci_smc.c | 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_set_smc_sram_address() 235 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode() 245 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
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H A D | radeon_legacy_crtc.c | 336 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms() 338 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | in radeon_crtc_dpms() 340 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms() 352 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms() 354 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | in radeon_crtc_dpms() 356 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms() 953 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll() 974 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
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H A D | radeon_rv730_dpm.c | 457 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv730_start_dpm() 459 WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv730_start_dpm() 461 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in rv730_start_dpm() 473 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv730_stop_dpm() 475 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv730_stop_dpm() 477 WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); in rv730_stop_dpm()
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H A D | radeon_si_smc.c | 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_set_smc_sram_address() 271 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode() 281 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_uvd_v4_2.c | 270 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start() 283 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start() 311 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start() 334 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start() 348 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start() 350 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start() 374 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start() 416 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop() 429 WREG32_P(0x3D49, 0, ~(1 << 2)); in uvd_v4_2_stop() 431 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v4_2_stop() [all …]
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H A D | amdgpu_vce_v2_0.c | 135 WREG32_P(mmVCE_SOFT_RESET, in vce_v2_0_firmware_loaded() 139 WREG32_P(mmVCE_SOFT_RESET, 0, in vce_v2_0_firmware_loaded() 177 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_mc_resume() 179 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_mc_resume() 183 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_mc_resume() 205 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_mc_resume() 241 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v2_0_start() 270 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v2_0_start() 296 WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8)); in vce_v2_0_stop() 305 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001); in vce_v2_0_stop() [all …]
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H A D | amdgpu_uvd_v5_0.c | 306 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start() 315 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start() 318 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start() 360 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start() 379 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start() 392 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start() 395 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start() 426 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start() 444 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_stop() 455 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_stop() [all …]
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H A D | amdgpu_vce_v4_0.c | 146 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_firmware_loaded() 150 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_firmware_loaded() 375 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001); in vce_v4_0_start() 377 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_start() 398 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); in vce_v4_0_stop() 401 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_stop() 614 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16)); in vce_v4_0_mc_resume() 620 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1); in vce_v4_0_mc_resume() 660 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100); in vce_v4_0_mc_resume() 661 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), in vce_v4_0_mc_resume() [all …]
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H A D | amdgpu_si_smc.c | 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_set_smc_sram_address() 234 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in amdgpu_si_load_smc_ucode() 244 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in amdgpu_si_load_smc_ucode()
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H A D | amdgpu_vce_v3_0.c | 311 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); in vce_v3_0_start() 348 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001); in vce_v3_0_stop() 533 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v3_0_mc_resume() 534 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v3_0_mc_resume() 535 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v3_0_mc_resume() 539 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v3_0_mc_resume() 576 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v3_0_mc_resume() 716 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); in vce_v3_0_set_interrupt_state()
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H A D | amdgpu_vcn_v2_5.c | 925 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start() 929 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start() 980 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start() 987 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start() 1007 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start() 1024 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in vcn_v2_5_start() 1029 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0, in vcn_v2_5_start() 1339 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), in vcn_v2_5_stop() 1344 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop() 1349 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop() [all …]
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H A D | amdgpu_jpeg_v2_5.c | 319 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v2_5_start() 332 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, in jpeg_v2_5_start() 336 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), in jpeg_v2_5_start() 372 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), in jpeg_v2_5_stop() 379 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), in jpeg_v2_5_stop()
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