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Searched refs:X21 (Results 1 – 18 of 18) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td69 // A SwiftError is passed in X21.
70 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
134 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
207 // A SwiftError is passed in X21.
208 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
388 def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
400 def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
413 def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
438 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>;
470 def CSR_Darwin_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21,
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H A DAArch64SLSHardening.cpp171 { "__llvm_slsblr_thunk_x21", AArch64::X21},
H A DAArch64RegisterInfo.td116 def X21 : AArch64Reg<21, "x21", [W21]>, DwarfRegAlias<W21>;
205 def tcGPR64 : RegisterClass<"AArch64", [i64], 64, (sub GPR64common, X19, X20, X21,
/netbsd/sys/external/bsd/gnu-efi/dist/inc/aarch64/
H A Defisetjmp_arch.h12 UINT64 X21; member
/netbsd/external/gpl3/gdb/dist/sim/testsuite/sim/bfin/
H A Dlmu_excpt_illaddr.S198 X21: [ P1 ] = R1; // Exception should occur here label
202 CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!)
/netbsd/external/gpl3/gdb.old/dist/sim/testsuite/sim/bfin/
H A Dlmu_excpt_illaddr.S198 X21: [ P1 ] = R1; // Exception should occur here label
202 CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!)
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp457 MIB.addUse(AArch64::X21, RegState::Implicit); in lowerReturn()
458 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
1146 MIB.addDef(AArch64::X21, RegState::Implicit); in lowerCall()
1147 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h52 case AArch64::X21: return AArch64::W21; in getWRegFromXReg()
92 case AArch64::W21: return AArch64::X21; in getXRegFromWReg()
/netbsd/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dstm32mp15xx-dhcom-pdk2.dtsi167 &i2c5 { /* Header X21 */
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp135 {/*s5*/ RISCV::X21, -7},
H A DRISCVFrameLowering.cpp155 case /*s5*/ RISCV::X21: return 6; in getLibCallID()
H A DRISCVRegisterInfo.td104 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>;
H A DRISCVISelLowering.cpp7170 RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, in CC_RISCV_GHC()
8093 .Case("{s5}", RISCV::X21) in getRegForInlineAsmConstraint()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
H A DAArch64MCTargetDesc.cpp122 {codeview::RegisterId::ARM64_X21, AArch64::X21}, in initLLVMToCVRegMapping()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td298 X21, X22, X23, X24, X25, X26, X27, X28,
H A DPPCFrameLowering.cpp150 {PPC::X21, -88}, \ in getCalleeSavedSpillSlots()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp437 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,