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Searched refs:_reg (Results 1 – 25 of 64) sorted by relevance

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/netbsd/sys/arch/arm/nxp/
H A Dimx6_ccmvar.h189 .reg = (CCM_ANALOG_##_reg), \
202 .reg = (CCM_ANALOG_##_reg), \
218 .reg = (CCM_##_reg), \
219 .mask = (CCM_##_reg##_##_mask), \
232 .reg = (CCM_##_reg), \
233 .mask = (CCM_##_reg##_##_mask), \
248 .reg = (CCM_ANALOG_##_reg), \
262 .reg = (_base##_##_reg), \
277 .reg = (CCM_##_reg), \
294 .reg = (_base##_##_reg), \
[all …]
H A Dimx_ccm.h87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \ argument
88 IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)
97 .u.gate.reg = (_reg), \
102 #define IMX_ROOT_GATE(_id, _name, _pname, _reg) \ argument
103 IMX_ROOT_GATE_INDEX(_id, 0, _name, _pname, _reg)
136 .u.composite.reg = (_reg), \
171 .u.pll.reg = (_reg), \
235 #define IMX_MUX(_id, _name, _parents, _reg, _sel) \ argument
236 IMX_MUX_INDEX(_id, 0, _name, _parents, _reg, _sel)
247 .u.mux.reg = (_reg), \
[all …]
H A Dimx7d_ccm.c101 #define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \ argument
102 IMX_MUX_INDEX(_id, REGIDX_ANATOP, _name, _parents, _reg, _mask)
103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \ argument
104 IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)
105 #define ANATOP_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \ argument
106 IMX_PLL_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _div_mask, _flags)
/netbsd/sys/arch/arm/at91/
H A Dat91rm9200reg.h198 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) argument
199 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) = (_val)… argument
200 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) argument
201 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) = (_val)… argument
202 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg))) argument
203 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg))) = (_val)… argument
204 #define PIOD_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOD_BASE + (_reg))) argument
205 #define PIOD_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOD_BASE + (_reg))) = (_val)… argument
H A Dat91sam9261reg.h211 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) argument
212 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) = (_val… argument
213 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) argument
214 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) = (_val… argument
215 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) argument
216 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) = (_val… argument
H A Dat91sam9260reg.h213 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOA_BASE + (_reg))) argument
214 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOA_BASE + (_reg))) = (_val… argument
215 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOB_BASE + (_reg))) argument
216 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOB_BASE + (_reg))) = (_val… argument
217 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOC_BASE + (_reg))) argument
218 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOC_BASE + (_reg))) = (_val… argument
H A Dat91pio.c69 #define PIO_READ(_sc, _reg) bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg)) argument
70 #define PIO_WRITE(_sc, _reg, _val) bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg), (_val)) argument
/netbsd/sys/external/isc/atheros_hal/ic/
H A Dah_osdep.h93 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) argument
94 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) argument
112 #define OS_REG_WRITE(_ah, _reg, _val) do { \ argument
113 if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
115 (_reg), (_val)); \
118 (_reg), (_val)); \
120 #define OS_REG_READ(_ah, _reg) \ argument
121 (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
122 bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)) : \
125 #define OS_REG_WRITE(_ah, _reg, _val) \ argument
[all …]
/netbsd/sys/arch/alpha/tlsb/
H A Dtlsbreg.h68 #define TLSB_NODE_REG_ADDR(_node, _reg) \ argument
69 KV((long)TLSB_NODE_ADDR((_node)) + (_reg))
72 #define TLSB_GET_NODEREG(_node, _reg) \ argument
73 *(volatile uint32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg)))
74 #define TLSB_PUT_NODEREG(_node, _reg, _val) \ argument
75 *(volatile uint32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg))) = (_val)
83 #define TLSB_BCAST_REG_ADDR(_reg) KV((long)(TLSB_BCASE_BASE + (_reg))) argument
86 #define TLSB_GET_BCASTREG(_reg) \ argument
87 *(volatile uint32_t *)(TLSB_BCAST_REG_ADDR + (_reg))
88 #define TLSB_PUT_BCASTREG(_reg, _val) \ argument
[all …]
/netbsd/sys/arch/arm/sunxi/
H A Dsunxi_ccu.h47 #define SUNXI_CCU_RESET(_id, _reg, _bit) \ argument
49 .reg = (_reg), \
81 #define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \ argument
87 .u.gate.reg = (_reg), \
134 .u.nkmp.reg = (_reg), \
187 .u.nm.reg = (_reg), \
238 .u.div.reg = (_reg), \
298 .u.prediv.reg = (_reg), \
330 .u.phase.reg = (_reg), \
397 .u.fractional.reg = (_reg), \
[all …]
/netbsd/sys/arch/arm/amlogic/
H A Dmeson_clk.h48 #define MESON_CLK_RESET(_id, _reg, _bit) \ argument
50 .reg = (_reg), \
111 .u.gate.reg = (_reg), \
118 #define MESON_CLK_GATE(_id, _name, _pname, _reg, _bit) \ argument
119 MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, 0)
146 .u.div.reg = (_reg), \
199 #define MESON_CLK_MUX_RATE(_id, _name, _parents, _reg, _sel, \ argument
207 .u.mux.reg = (_reg), \
222 .u.mux.reg = (_reg), \
237 #define MESON_CLK_PLL_REG(_reg, _mask) \ argument
[all …]
/netbsd/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dreg.h82 #define REG_50080_TO_PIPE(_reg) ({ \ argument
83 typeof(_reg) (reg) = (_reg); \
89 #define REG_50080_TO_PLANE(_reg) ({ \ argument
90 typeof(_reg) (reg) = (_reg); \
/netbsd/sys/dev/fdt/
H A Dsyscon.h47 #define syscon_read_4(_syscon, _reg) \ argument
48 (_syscon)->read_4((_syscon)->priv, (_reg))
50 #define syscon_write_4(_syscon, _reg, _val) \ argument
51 (_syscon)->write_4((_syscon)->priv, (_reg), (_val))
H A Dfdt_regulator.c40 #define REGULATOR_TO_RC(_reg) \ argument
41 container_of((_reg), struct fdtbus_regulator_controller, rc_reg)
/netbsd/sys/external/isc/atheros_hal/dist/ar5312/
H A Dar5312reg.h31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); argument
32 #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) argument
/netbsd/sys/arch/arm/ti/
H A Dam3_prcm.c129 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \ argument
130 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable)
131 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \ argument
132 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display)
133 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \ argument
134 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable)
H A Dti_prcm.h143 #define TI_PRCM_HWMOD(_name, _reg, _parent, _enable) \ argument
144 TI_PRCM_HWMOD_MASK(_name, _reg, 0, _parent, _enable, 0)
146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \ argument
149 .u.hwmod.reg = (_reg), \
/netbsd/sys/arch/arm/rockchip/
H A Drk_cru.h190 #define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \ argument
198 .u.arm.mux_reg = (_reg), \
202 .u.arm.divs[0].reg = (_reg), \
355 #define RK_GATE(_id, _name, _pname, _reg, _bit) \ argument
362 .u.gate.reg = (_reg), \
391 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \ argument
399 .u.mux.reg = (_reg), \
405 #define RK_MUX(_id, _name, _parents, _reg, _mask) \ argument
406 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0)
407 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \ argument
[all …]
/netbsd/sys/arch/arm/samsung/
H A Dexynos5410_clock.c155 .reg = (_reg), \
161 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \ argument
162 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
164 #define CLK_MUX(_name, _reg, _bits, _p) \ argument
165 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)
167 #define CLK_DIVF(_name, _parent, _reg, _bits, _f) { \ argument
173 .reg = (_reg), \
179 #define CLK_DIV(_name, _parent, _reg, _bits) \ argument
180 CLK_DIVF(_name, _parent, _reg, _bits, 0)
182 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \ argument
[all …]
H A Dexynos5422_clock.c291 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \ argument
299 .reg = (_reg), \
305 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \ argument
306 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
308 #define CLK_MUX(_name, _reg, _bits, _p) \ argument
309 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)
311 #define CLK_DIV(_name, _parent, _reg, _bits) { \ argument
316 .reg = (_reg), \
322 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \ argument
328 .reg = (_reg), \
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
H A Dddc_regs.h37 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
60 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
77 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
/netbsd/sys/dev/marvell/
H A Dif_mvxpevar.h335 uint32_t _reg = MVXPE_READ(sc, MVXPE_PRXS(q)); \
338 q, _reg, MVXPE_PRXS_GET_ODC(_reg), \
339 MVXPE_PRXS_GET_NODC(_reg)); \
/netbsd/external/bsd/pcc/dist/pcc/mip/
H A Dnode.h68 int _reg; member
71 #define n_reg n_3._reg
/netbsd/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_cmd_parser.c579 #define REG32(_reg, ...) \ argument
580 { .addr = (_reg), __VA_ARGS__ }
589 #define REG64(_reg) \ argument
590 { .addr = _reg }, \
591 { .addr = _reg ## _UDW }
593 #define REG64_IDX(_reg, idx) \ argument
594 { .addr = _reg(idx) }, \
595 { .addr = _reg ## _UDW(idx) }
/netbsd/sys/arch/arm/nvidia/
H A Dtegra124_car.c310 #define CLK_MUX(_name, _reg, _bits, _p) { \ argument
316 .reg = (_reg), \
332 #define CLK_DIV(_name, _parent, _reg, _bits) { \ argument
337 .reg = (_reg), \
386 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ argument
387 CLK_GATE(_name, _parent, _reg, _reg, _bits)

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