| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| H A D | amdgpu_dce120_hw_sequencer.c | 82 #define CNTL_ID(controller_id)\ argument
83 controller_id
88 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
157 uint8_t controller_id, in dce120_enable_display_power_gating() argument
177 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { in dce120_enable_display_power_gating()
180 dcb, controller_id + 1, cntl); in dce120_enable_display_power_gating()
186 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id), in dce120_enable_display_power_gating()
191 dce120_init_pte(ctx, controller_id); in dce120_enable_display_power_gating()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| H A D | command_table.h | 78 enum controller_id controller_id,
82 enum controller_id controller_id,
92 enum controller_id crtc_id,
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| H A D | command_table2.h | 78 enum controller_id controller_id,
82 enum controller_id controller_id,
92 enum controller_id crtc_id,
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| H A D | amdgpu_command_table2.c | 364 uint8_t controller_id; in set_pixel_clock_v7() local
371 controller_id, &controller_id)) { in set_pixel_clock_v7()
391 clk.crtc_id = controller_id; in set_pixel_clock_v7()
411 bp_params->target_pixel_clock_100hz, (int)controller_id, in set_pixel_clock_v7()
494 bp_params->controller_id, &atom_controller_id)) in set_crtc_using_dtd_timing_v3()
589 enum controller_id controller_id,
608 enum controller_id controller_id, in enable_crtc_v1() argument
685 enum controller_id crtc_id,
690 enum controller_id crtc_id,
726 enum controller_id crtc_id, in enable_disp_power_gating_v2_1()
[all …]
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| H A D | amdgpu_command_table.c | 1022 uint8_t controller_id; in set_pixel_clock_v5() local
1029 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v5()
1079 uint8_t controller_id; in set_pixel_clock_v6() local
1086 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v6()
1157 uint8_t controller_id; in set_pixel_clock_v7() local
1911 enum controller_id controller_id,
1930 enum controller_id controller_id, in enable_crtc_v1() argument
1963 enum controller_id controller_id,
1980 enum controller_id controller_id, in enable_crtc_mem_req_v1() argument
2243 enum controller_id crtc_id,
[all …]
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| H A D | command_table_helper2.h | 40 enum controller_id id,
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| H A D | command_table_helper.h | 40 enum controller_id id,
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| H A D | command_table_helper_struct.h | 37 bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
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| H A D | amdgpu_command_table_helper2.c | 91 enum controller_id id, in dal_cmd_table_helper_controller_id_to_atom2()
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| H A D | amdgpu_command_table_helper.c | 73 enum controller_id id, in dal_cmd_table_helper_controller_id_to_atom()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
| H A D | bios_parser_types.h | 132 enum controller_id controller_id; member
163 enum controller_id controller_id; member
211 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ member
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| H A D | grph_object_id.h | 76 enum controller_id { enum
250 static inline enum controller_id dal_graphics_object_id_get_controller_id( in dal_graphics_object_id_get_controller_id()
254 return (enum controller_id) id.id; in dal_graphics_object_id_get_controller_id()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| H A D | amdgpu_dce100_hw_sequencer.c | 79 uint8_t controller_id, in dce100_enable_display_power_gating() argument
94 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){ in dce100_enable_display_power_gating()
97 dcb, controller_id + 1, cntl); in dce100_enable_display_power_gating()
103 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id), in dce100_enable_display_power_gating()
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| H A D | dce100_hw_sequencer.h | 47 bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| H A D | amdgpu_dce112_hw_sequencer.c | 120 uint8_t controller_id, in dce112_enable_display_power_gating() argument
138 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ in dce112_enable_display_power_gating()
141 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating()
147 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), in dce112_enable_display_power_gating()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | amdgpu_dce_abm.c | 63 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id) in dce_abm_set_pipe() argument
80 MASTER_COMM_CMD_REG_BYTE1, controller_id); in dce_abm_set_pipe()
209 uint32_t controller_id) in dmcu_set_backlight_level() argument
221 dce_abm_set_pipe(&abm_dce->base, controller_id); in dmcu_set_backlight_level()
231 if (controller_id == 0) in dmcu_set_backlight_level()
427 unsigned int controller_id, in dce_abm_set_backlight_level_pwm() argument
440 controller_id); in dce_abm_set_backlight_level_pwm()
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| H A D | amdgpu_dce_clock_source.c | 864 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce110_program_pix_clk()
915 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dce112_program_pix_clk()
938 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce112_program_pix_clk()
978 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; in dce110_clock_source_power_down()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dc_bios_types.h | 105 enum controller_id id,
128 enum controller_id controller_id,
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| H A D | abm.h | 51 bool (*set_pipe)(struct abm *abm, unsigned int controller_id);
60 unsigned int controller_id,
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | clock_source.h | 94 enum controller_id controller_id; member
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| H A D | dce110_timing_generator.h | 103 enum controller_id controller_id; member
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| H A D | amdgpu_dce110_compressor.c | 466 unsigned int controller_id_to_index(enum controller_id controller_id) in controller_id_to_index() argument
470 switch (controller_id) { in controller_id_to_index()
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| H A D | amdgpu_dce110_timing_generator.c | 151 result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true); in dce110_timing_generator_enable_crtc()
243 result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false); in dce110_timing_generator_disable_crtc()
313 bp_params.controller_id = tg110->controller_id; in dce110_timing_generator_program_timing_generator()
1815 switch (tg110->controller_id) { in dce110_timing_generator_disable_vga()
2260 tg110->controller_id = CONTROLLER_ID_D0 + instance; in dce110_timing_generator_construct()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| H A D | amdgpu_dc_surface.c | 108 uint32_t controller_id) in enable_surface_flip_reporting() argument
110 plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; in enable_surface_flip_reporting()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/ |
| H A D | dm_pp_interface.h | 53 uint32_t controller_id; member
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