| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
|
| H A D | ThumbRegisterInfo.cpp | 76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
|
| H A D | ARMLoadStoreOptimizer.cpp | 809 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
825 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1348 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1529 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1533 .addReg(MO.getReg(), (isLd ? getDefRegState(true) in MergeBaseUpdateLoadStore()
1740 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1811 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1812 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)) in FixInvalidRegPairOp()
|
| H A D | MLxExpansionPass.cpp | 298 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
|
| H A D | ARMBaseRegisterInfo.cpp | 489 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
|
| H A D | Thumb1FrameLowering.cpp | 1061 MIB.addReg(Reg, getDefRegState(true)); in restoreCalleeSavedRegisters()
|
| H A D | ARMFrameLowering.cpp | 1225 MIB.addReg(Regs[i], getDefRegState(true)); in emitPopInst()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 234 MIB.addReg(Reg2, getDefRegState(true)) in emitLoad()
235 .addReg(Reg1, getDefRegState(true)) in emitLoad()
|
| H A D | AArch64FrameLowering.cpp | 2674 MIB.addReg(Reg2, getDefRegState(true)); in restoreCalleeSavedRegisters()
2679 MIB.addReg(Reg1, getDefRegState(true)) in restoreCalleeSavedRegisters()
|
| H A D | AArch64InstrInfo.cpp | 3874 .addReg(DestReg, getDefRegState(true)) in loadRegFromStackSlot()
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 502 inline unsigned getDefRegState(bool B) { in getDefRegState() function
530 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true)); in insertMergedInstruction()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 214 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1150 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
1232 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 363 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 301 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
|
| H A D | X86InstrInfo.cpp | 6342 getDefRegState(ImpOp.isDef()) | in unfoldMemoryOperand()
|