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Searched refs:gfx8 (Results 1 – 10 of 10) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_debug.c146 plane_state->tiling_info.gfx8.num_banks, in pre_surface_trace()
147 plane_state->tiling_info.gfx8.bank_width, in pre_surface_trace()
148 plane_state->tiling_info.gfx8.bank_width_c, in pre_surface_trace()
149 plane_state->tiling_info.gfx8.bank_height, in pre_surface_trace()
151 plane_state->tiling_info.gfx8.tile_aspect, in pre_surface_trace()
153 plane_state->tiling_info.gfx8.tile_split, in pre_surface_trace()
154 plane_state->tiling_info.gfx8.tile_split_c, in pre_surface_trace()
155 plane_state->tiling_info.gfx8.tile_mode, in pre_surface_trace()
156 plane_state->tiling_info.gfx8.tile_mode_c); in pre_surface_trace()
166 plane_state->tiling_info.gfx8.pipe_config, in pre_surface_trace()
[all …]
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_mem_input_v.c177 set_reg_field_value(value, info->gfx8.num_banks, in program_tiling()
180 set_reg_field_value(value, info->gfx8.bank_width, in program_tiling()
183 set_reg_field_value(value, info->gfx8.bank_height, in program_tiling()
186 set_reg_field_value(value, info->gfx8.tile_aspect, in program_tiling()
189 set_reg_field_value(value, info->gfx8.tile_split, in program_tiling()
192 set_reg_field_value(value, info->gfx8.tile_mode, in program_tiling()
195 set_reg_field_value(value, info->gfx8.pipe_config, in program_tiling()
198 set_reg_field_value(value, info->gfx8.array_mode, in program_tiling()
214 set_reg_field_value(value, info->gfx8.bank_width_c, in program_tiling()
226 set_reg_field_value(value, info->gfx8.tile_mode_c, in program_tiling()
[all …]
H A Damdgpu_dce110_hw_sequencer.c1837 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_mem_input.c108 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
379 GRPH_NUM_BANKS, info->gfx8.num_banks, in program_tiling()
380 GRPH_BANK_WIDTH, info->gfx8.bank_width, in program_tiling()
381 GRPH_BANK_HEIGHT, info->gfx8.bank_height, in program_tiling()
382 GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect, in program_tiling()
383 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
384 GRPH_MICRO_TILE_MODE, info->gfx8.tile_mode, in program_tiling()
385 GRPH_PIPE_CONFIG, info->gfx8.pipe_config, in program_tiling()
386 GRPH_ARRAY_MODE, info->gfx8.array_mode, in program_tiling()
/netbsd/external/apache2/llvm/dist/clang/include/clang/Basic/
H A DBuiltinsAMDGPU.def185 TARGET_BUILTIN(__builtin_amdgcn_s_dcache_wb, "v", "n", "gfx8-insts")
186 TARGET_BUILTIN(__builtin_amdgcn_perm, "UiUiUiUi", "nc", "gfx8-insts")
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_hw_types.h344 } gfx8; member
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c3272 tiling_info->gfx8.num_banks = num_banks; in fill_plane_buffer_attributes()
3273 tiling_info->gfx8.array_mode = in fill_plane_buffer_attributes()
3275 tiling_info->gfx8.tile_split = tile_split; in fill_plane_buffer_attributes()
3276 tiling_info->gfx8.bank_width = bankw; in fill_plane_buffer_attributes()
3277 tiling_info->gfx8.bank_height = bankh; in fill_plane_buffer_attributes()
3278 tiling_info->gfx8.tile_aspect = mtaspect; in fill_plane_buffer_attributes()
3279 tiling_info->gfx8.tile_mode = in fill_plane_buffer_attributes()
3283 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in fill_plane_buffer_attributes()
3286 tiling_info->gfx8.pipe_config = in fill_plane_buffer_attributes()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td293 def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
323 def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
H A DMIMGInstructions.td12 // - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8)
13 // - MIMGEncGfx8: encoding introduced with gfx8 for atomics
H A DDSInstructions.td430 // FIXME: Are these really present pre-gfx8?