| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_dpp.c | 409 if (in_taps->h_taps == 0) { in dpp2_get_optimal_number_of_taps()
411 scl_data->taps.h_taps = 8; in dpp2_get_optimal_number_of_taps()
413 scl_data->taps.h_taps = 4; in dpp2_get_optimal_number_of_taps()
415 scl_data->taps.h_taps = in_taps->h_taps; in dpp2_get_optimal_number_of_taps()
443 scl_data->taps.h_taps = 1; in dpp2_get_optimal_number_of_taps()
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| H A D | amdgpu_dcn20_dwb_scl.c | 730 uint32_t h_taps_luma = num_taps.h_taps; in dwb_program_horz_scalar()
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| H A D | amdgpu_dcn20_resource.c | 2157 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; in dcn20_populate_dml_pipes_from_context()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | amdgpu_dce_transform.c | 127 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
137 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in setup_scaling_configuration()
272 dc_fixpt_from_int(data->taps.h_taps + 1)), in calculate_inits()
358 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce_transform_set_scaler()
382 data->taps.h_taps, in dce_transform_set_scaler()
387 data->taps.h_taps, in dce_transform_set_scaler()
927 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); in dce_transform_get_optimal_number_of_taps()
929 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); in dce_transform_get_optimal_number_of_taps()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_dpp_dscl.c | 318 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
340 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
361 dpp, scl_data->taps.h_taps, in dpp1_dscl_set_scl_filter()
574 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, in dpp1_dscl_set_scaler_auto_scale()
734 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
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| H A D | amdgpu_dcn10_dpp.c | 174 if (in_taps->h_taps == 0) in dpp1_get_optimal_number_of_taps()
175 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps()
177 scl_data->taps.h_taps = in_taps->h_taps; in dpp1_get_optimal_number_of_taps()
196 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| H A D | amdgpu_dce110_transform_v.c | 172 set_reg_field_value(value, data->taps.h_taps - 1, in setup_scaling_configuration()
183 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
568 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); in dce110_xfmv_set_scaler()
591 data->taps.h_taps, in dce110_xfmv_set_scaler()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| H A D | amdgpu_dc_debug.c | 90 plane_state->scaling_quality.h_taps, in pre_surface_trace()
294 update->scaling_info->scaling_quality.h_taps, in update_surface_trace()
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| H A D | amdgpu_dc_resource.c | 890 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19); in calculate_inits_and_adj_vp()
909 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps, in calculate_inits_and_adj_vp()
927 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps, in calculate_inits_and_adj_vp()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| H A D | amdgpu_dce_calcs.c | 372 data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
373 data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
426 data->h_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
516 if (bw_mtn(data->hsr[i], data->h_taps[i])) { in calculate_bandwidth()
520 …sr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixe… in calculate_bandwidth()
1703 …data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_t… in calculate_bandwidth()
2807 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2862 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2909 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2960 …data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_t… in populate_initial_data()
[all …]
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| H A D | calcs_logger.h | 432 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i])); in print_bw_calcs_data()
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| H A D | amdgpu_dcn_calcs.c | 389 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
986 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dc_hw_types.h | 581 uint32_t h_taps; member
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 398 struct bw_fixed h_taps[maximum_number_of_surfaces]; member
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