xref: /netbsd/sys/dev/pci/if_bnxreg.h (revision b2c5e200)
1 /*	$NetBSD: if_bnxreg.h,v 1.28 2021/12/12 13:05:14 andvar Exp $	*/
2 /*	$OpenBSD: if_bnxreg.h,v 1.33 2009/09/05 16:02:28 claudio Exp $  */
3 
4 /*-
5  * Copyright (c) 2006 Broadcom Corporation
6  *	David Christensen <davidch@broadcom.com>.  All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written consent.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $
33  */
34 
35 /* General controller flags -- bnx_flags element in bnx_softc */
36 #define BNX_PCIX_FLAG			0x01
37 #define BNX_PCI_32BIT_FLAG		0x02
38 #define BNX_ONE_TDMA_FLAG		0x04		/* Deprecated */
39 #define BNX_NO_WOL_FLAG			0x08
40 #define BNX_USING_DAC_FLAG		0x10
41 #define BNX_USING_MSI_FLAG		0x20
42 #define BNX_MFW_ENABLE_FLAG		0x40
43 #define BNX_ACTIVE_FLAG			0x80
44 #define BNX_ALLOC_PKTS_FLAG		0x100
45 #define BNX_PCIE_FLAG			0x200
46 
47 /* PHY specific flags -- bnx_phy_flags element in bnx_softc */
48 #define BNX_PHY_SERDES_FLAG			0x001
49 #define BNX_PHY_CRC_FIX_FLAG			0x002
50 #define BNX_PHY_PARALLEL_DETECT_FLAG		0x004
51 #define BNX_PHY_2_5G_CAPABLE_FLAG		0x008
52 #define BNX_PHY_INT_MODE_MASK_FLAG		0x300
53 #define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG	0x100
54 #define BNX_PHY_INT_MODE_LINK_READY_FLAG	0x200
55 #define BNX_PHY_IEEE_CLAUSE_45_FLAG		0x400
56 
57 /****************************************************************************/
58 /* Debugging macros and definitions.					    */
59 /****************************************************************************/
60 #define BNX_CP_LOAD		0x00000001
61 #define BNX_CP_SEND		0x00000002
62 #define BNX_CP_RECV		0x00000004
63 #define BNX_CP_INTR		0x00000008
64 #define BNX_CP_UNLOAD		0x00000010
65 #define BNX_CP_RESET		0x00000020
66 #define BNX_CP_PHY		0x00000040
67 #define BNX_CP_ALL		0x00FFFFFF
68 
69 #define BNX_CP_MASK		0x00FFFFFF
70 
71 #define BNX_LEVEL_FATAL		0x00000000
72 #define BNX_LEVEL_WARN		0x01000000
73 #define BNX_LEVEL_INFO		0x02000000
74 #define BNX_LEVEL_VERBOSE	0x03000000
75 #define BNX_LEVEL_EXCESSIVE	0x04000000
76 
77 #define BNX_LEVEL_MASK		0xFF000000
78 
79 #define BNX_WARN_LOAD		(BNX_CP_LOAD | BNX_LEVEL_WARN)
80 #define BNX_INFO_LOAD		(BNX_CP_LOAD | BNX_LEVEL_INFO)
81 #define BNX_VERBOSE_LOAD	(BNX_CP_LOAD | BNX_LEVEL_VERBOSE)
82 #define BNX_EXCESSIVE_LOAD	(BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE)
83 
84 #define BNX_WARN_SEND		(BNX_CP_SEND | BNX_LEVEL_WARN)
85 #define BNX_INFO_SEND		(BNX_CP_SEND | BNX_LEVEL_INFO)
86 #define BNX_VERBOSE_SEND	(BNX_CP_SEND | BNX_LEVEL_VERBOSE)
87 #define BNX_EXCESSIVE_SEND	(BNX_CP_SEND | BNX_LEVEL_EXCESSIVE)
88 
89 #define BNX_WARN_RECV		(BNX_CP_RECV | BNX_LEVEL_WARN)
90 #define BNX_INFO_RECV		(BNX_CP_RECV | BNX_LEVEL_INFO)
91 #define BNX_VERBOSE_RECV	(BNX_CP_RECV | BNX_LEVEL_VERBOSE)
92 #define BNX_EXCESSIVE_RECV	(BNX_CP_RECV | BNX_LEVEL_EXCESSIVE)
93 
94 #define BNX_WARN_INTR		(BNX_CP_INTR | BNX_LEVEL_WARN)
95 #define BNX_INFO_INTR		(BNX_CP_INTR | BNX_LEVEL_INFO)
96 #define BNX_VERBOSE_INTR	(BNX_CP_INTR | BNX_LEVEL_VERBOSE)
97 #define BNX_EXCESSIVE_INTR	(BNX_CP_INTR | BNX_LEVEL_EXCESSIVE)
98 
99 #define BNX_WARN_UNLOAD		(BNX_CP_UNLOAD | BNX_LEVEL_WARN)
100 #define BNX_INFO_UNLOAD		(BNX_CP_UNLOAD | BNX_LEVEL_INFO)
101 #define BNX_VERBOSE_UNLOAD	(BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE)
102 #define BNX_EXCESSIVE_UNLOAD	(BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE)
103 
104 #define BNX_WARN_RESET		(BNX_CP_RESET | BNX_LEVEL_WARN)
105 #define BNX_INFO_RESET		(BNX_CP_RESET | BNX_LEVEL_INFO)
106 #define BNX_VERBOSE_RESET	(BNX_CP_RESET | BNX_LEVEL_VERBOSE)
107 #define BNX_EXCESSIVE_RESET	(BNX_CP_RESET | BNX_LEVEL_EXCESSIVE)
108 
109 #define BNX_WARN_PHY		(BNX_CP_PHY | BNX_LEVEL_WARN)
110 #define BNX_INFO_PHY		(BNX_CP_PHY | BNX_LEVEL_INFO)
111 #define BNX_VERBOSE_PHY		(BNX_CP_PHY | BNX_LEVEL_VERBOSE)
112 #define BNX_EXTREME_PHY		(BNX_CP_PHY | BNX_LEVEL_EXTREME)
113 #define BNX_INSANE_PHY		(BNX_CP_PHY | BNX_LEVEL_INSANE)
114 
115 #define BNX_FATAL		(BNX_CP_ALL | BNX_LEVEL_FATAL)
116 #define BNX_WARN		(BNX_CP_ALL | BNX_LEVEL_WARN)
117 #define BNX_INFO		(BNX_CP_ALL | BNX_LEVEL_INFO)
118 #define BNX_VERBOSE		(BNX_CP_ALL | BNX_LEVEL_VERBOSE)
119 #define BNX_EXCESSIVE		(BNX_CP_ALL | BNX_LEVEL_EXCESSIVE)
120 
121 #define BNX_CODE_PATH(cp)	(((cp) & BNX_CP_MASK) & bnx_debug)
122 #define BNX_MSG_LEVEL(lv)	\
123 	(((lv) & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK))
124 #define BNX_LOG_MSG(m)		(BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m))
125 
126 #ifdef BNX_DEBUG
127 
128 /* Print a message based on the logging level and code path. */
129 #define DBPRINT(sc, level, format, args...)				\
130 	if (BNX_LOG_MSG(level)) {					\
131 		device_printf((sc)->bnx_dev, format, ## args);	\
132 	}
133 
134 /* Runs a particular command based on the logging level and code path. */
135 #define DBRUN(m, args...)					\
136 	if (BNX_LOG_MSG(m)) {					\
137 		args;						\
138 	}
139 
140 /* Runs a particular command based on the logging level. */
141 #define DBRUNLV(level, args...)					\
142 	if (BNX_MSG_LEVEL(level)) {				\
143 		args;						\
144 	}
145 
146 /* Runs a particular command based on the code path. */
147 #define DBRUNCP(cp, args...)					\
148 	if (BNX_CODE_PATH(cp)) {				\
149 		args;						\
150 	}
151 
152 /* Runs a particular command based on a condition. */
153 #define DBRUNIF(cond, args...)					\
154 	if (cond) {						\
155 		args;						\
156 	}
157 #if 0
158 /* Needed for random() function which is only used in debugging. */
159 #include <sys/random.h>
160 #endif
161 
162 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
163 #define DB_RANDOMFALSE(defects)	       (random() > (defects))
164 #define DB_OR_RANDOMFALSE(defects)  || (random() > (defects))
165 #define DB_AND_RANDOMFALSE(defects) && (random() > (defects))
166 
167 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
168 #define DB_RANDOMTRUE(defects)	       (random() < (defects))
169 #define DB_OR_RANDOMTRUE(defects)   || (random() < (defects))
170 #define DB_AND_RANDOMTRUE(defects)  && (random() < (defects))
171 
172 #else
173 
174 #define DBPRINT(level, format, ...)	__nothing
175 #define DBRUN(m, ...)			__nothing
176 #define DBRUNLV(level, ...)		__nothing
177 #define DBRUNCP(cp, ...)		__nothing
178 #define DBRUNIF(cond, ...)		__nothing
179 #define DB_RANDOMFALSE(defects)		__nothing
180 #define DB_OR_RANDOMFALSE(percent)	__nothing
181 #define DB_AND_RANDOMFALSE(percent)	__nothing
182 #define DB_RANDOMTRUE(defects)		__nothing
183 #define DB_OR_RANDOMTRUE(percent)	__nothing
184 #define DB_AND_RANDOMTRUE(percent)	__nothing
185 
186 #endif /* BNX_DEBUG */
187 
188 
189 /****************************************************************************/
190 /* Device identification definitions.					    */
191 /****************************************************************************/
192 #define BRCM_VENDORID			0x14E4
193 #define BRCM_DEVICEID_BCM5706		0x164A
194 #define BRCM_DEVICEID_BCM5706S		0x16AA
195 #define BRCM_DEVICEID_BCM5708		0x164C
196 #define BRCM_DEVICEID_BCM5708S		0x16AC
197 
198 #define HP_VENDORID			0x103C
199 
200 #define PCI_ANY_ID			(uint16_t) (~0U)
201 
202 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
203 
204 #define _BNX_CHIP_NUM(chipid)		((chipid) & 0xffff0000)
205 #define BNX_CHIP_NUM(sc)		_BNX_CHIP_NUM((sc)->bnx_chipid)
206 #define BNX_CHIP_NUM_5706		0x57060000
207 #define BNX_CHIP_NUM_5708		0x57080000
208 #define BNX_CHIP_NUM_5709		0x57090000
209 #define BNX_CHIP_NUM_5716		0x57160000
210 
211 #define _BNX_CHIP_REV(chipid)		((chipid) & 0x0000f000)
212 #define BNX_CHIP_REV(sc)		_BNX_CHIP_REV((sc)->bnx_chipid)
213 #define BNX_CHIP_REV_Ax			0x00000000
214 #define BNX_CHIP_REV_Bx			0x00001000
215 #define BNX_CHIP_REV_Cx			0x00002000
216 
217 #define BNX_CHIP_METAL(sc)		(((sc)->bnx_chipid) & 0x00000ff0)
218 #define BNX_CHIP_BOND(bp)		(((sc)->bnx_chipid) & 0x0000000f)
219 
220 #define _BNX_CHIP_ID(chipid)		((chipid) & 0xfffffff0)
221 #define BNX_CHIP_ID(sc)			_BNX_CHIP_ID((sc)->bnx_chipid)
222 
223 #define BNX_CHIP_ID_5706_A0		0x57060000
224 #define BNX_CHIP_ID_5706_A1		0x57060010
225 #define BNX_CHIP_ID_5706_A2		0x57060020
226 #define BNX_CHIP_ID_5706_A3		0x57060030
227 #define BNX_CHIP_ID_5708_A0		0x57080000
228 #define BNX_CHIP_ID_5708_B0		0x57081000
229 #define BNX_CHIP_ID_5708_B1		0x57081010
230 #define BNX_CHIP_ID_5708_B2		0x57081020
231 #define BNX_CHIP_ID_5709_A0		0x57090000
232 #define BNX_CHIP_ID_5709_A1		0x57090010
233 #define BNX_CHIP_ID_5709_B0		0x57091000
234 #define BNX_CHIP_ID_5709_B1		0x57091010
235 #define BNX_CHIP_ID_5709_B2		0x57091020
236 #define BNX_CHIP_ID_5709_C0		0x57092000
237 #define BNX_CHIP_ID_5716_C0		0x57162000
238 
239 #define BNX_CHIP_BOND_ID(sc)		(((sc)->bnx_chipid) & 0xf)
240 
241 /* A serdes chip will have the first bit of the bond id set. */
242 #define BNX_CHIP_BOND_ID_SERDES_BIT	0x01
243 
244 
245 /* shorthand one */
246 #define BNXNUM(sc)			(BNX_CHIP_NUM(sc) >> 16)
247 #define BNXREV(sc)			(BNX_CHIP_REV(sc) >> 12)
248 #define BNXMETAL(sc)			(BNX_CHIP_METAL(sc) >> 4)
249 
250 struct bnx_type {
251 	uint16_t	bnx_vid;
252 	uint16_t	bnx_did;
253 	uint16_t	bnx_svid;
254 	uint16_t	bnx_sdid;
255 	const char	*bnx_name;
256 };
257 
258 /****************************************************************************/
259 /* NVRAM Access								    */
260 /****************************************************************************/
261 
262 /* Buffered flash (Atmel: AT45DB011B) specific information */
263 #define SEEPROM_PAGE_BITS		2
264 #define SEEPROM_PHY_PAGE_SIZE		(1 << SEEPROM_PAGE_BITS)
265 #define SEEPROM_BYTE_ADDR_MASK		(SEEPROM_PHY_PAGE_SIZE-1)
266 #define SEEPROM_PAGE_SIZE		4
267 #define SEEPROM_TOTAL_SIZE		65536
268 
269 #define BUFFERED_FLASH_PAGE_BITS	9
270 #define BUFFERED_FLASH_PHY_PAGE_SIZE	(1 << BUFFERED_FLASH_PAGE_BITS)
271 #define BUFFERED_FLASH_BYTE_ADDR_MASK	(BUFFERED_FLASH_PHY_PAGE_SIZE-1)
272 #define BUFFERED_FLASH_PAGE_SIZE	264
273 #define BUFFERED_FLASH_TOTAL_SIZE	0x21000
274 
275 #define SAIFUN_FLASH_PAGE_BITS		8
276 #define SAIFUN_FLASH_PHY_PAGE_SIZE	(1 << SAIFUN_FLASH_PAGE_BITS)
277 #define SAIFUN_FLASH_BYTE_ADDR_MASK	(SAIFUN_FLASH_PHY_PAGE_SIZE-1)
278 #define SAIFUN_FLASH_PAGE_SIZE		256
279 #define SAIFUN_FLASH_BASE_TOTAL_SIZE	65536
280 
281 #define ST_MICRO_FLASH_PAGE_BITS	8
282 #define ST_MICRO_FLASH_PHY_PAGE_SIZE	(1 << ST_MICRO_FLASH_PAGE_BITS)
283 #define ST_MICRO_FLASH_BYTE_ADDR_MASK	(ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
284 #define ST_MICRO_FLASH_PAGE_SIZE	256
285 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE	65536
286 
287 #define BCM5709_FLASH_PAGE_BITS		8
288 #define BCM5709_FLASH_PHY_PAGE_SIZE	(1 << BCM5709_FLASH_PAGE_BITS)
289 #define BCM5709_FLASH_BYTE_ADDR_MASK	(BCM5709_FLASH_PHY_PAGE_SIZE-1)
290 #define BCM5709_FLASH_PAGE_SIZE		256
291 
292 #define NVRAM_TIMEOUT_COUNT		30000
293 #define BNX_FLASHDESC_MAX		64
294 
295 #define FLASH_STRAP_MASK		(BNX_NVM_CFG1_FLASH_MODE |	\
296 	    BNX_NVM_CFG1_BUFFER_MODE | BNX_NVM_CFG1_PROTECT_MODE |	\
297 	    BNX_NVM_CFG1_FLASH_SIZE)
298 
299 #define FLASH_BACKUP_STRAP_MASK		(0xf << 26)
300 
301 struct flash_spec {
302 	uint32_t strapping;
303 	uint32_t config1;
304 	uint32_t config2;
305 	uint32_t config3;
306 	uint32_t write1;
307 #define BNX_NV_BUFFERED		0x00000001
308 #define BNX_NV_TRANSLATE	0x00000002
309 #define BNX_NV_WREN		0x00000004
310 	uint32_t flags;
311 	uint32_t page_bits;
312 	uint32_t page_size;
313 	uint32_t addr_mask;
314 	uint32_t total_size;
315 	const uint8_t  *name;
316 };
317 
318 
319 /****************************************************************************/
320 /* Shared Memory layout							    */
321 /* The BNX bootcode will initialize this data area with port configurtion   */
322 /* information which can be accessed by the driver.			    */
323 /****************************************************************************/
324 
325 /*
326  * This value (in milliseconds) determines the frequency of the driver
327  * issuing the PULSE message code.  The firmware monitors this periodic
328  * pulse to determine when to switch to an OS-absent mode.
329  */
330 #define DRV_PULSE_PERIOD_MS		250
331 
332 /*
333  * This value (in milliseconds) determines how long the driver should
334  * wait for an acknowledgement from the firmware before timing out.  Once
335  * the firmware has timed out, the driver will assume there is no firmware
336  * running and there won't be any firmware-driver synchronization during a
337  * driver reset.
338  */
339 #define FW_ACK_TIME_OUT_MS		1000
340 
341 
342 #define BNX_DRV_RESET_SIGNATURE		0x00000000
343 #define BNX_DRV_RESET_SIGNATURE_MAGIC	0x4841564b /* HAVK */
344 
345 #define BNX_DRV_MB			0x00000004
346 #define BNX_DRV_MSG_CODE		 0xff000000
347 #define BNX_DRV_MSG_CODE_RESET		 0x01000000
348 #define BNX_DRV_MSG_CODE_UNLOAD		 0x02000000
349 #define BNX_DRV_MSG_CODE_SHUTDOWN	 0x03000000
350 #define BNX_DRV_MSG_CODE_SUSPEND_WOL	 0x04000000
351 #define BNX_DRV_MSG_CODE_FW_TIMEOUT	 0x05000000
352 #define BNX_DRV_MSG_CODE_PULSE		 0x06000000
353 #define BNX_DRV_MSG_CODE_DIAG		 0x07000000
354 #define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL	 0x09000000
355 
356 #define BNX_DRV_MSG_DATA		0x00ff0000
357 #define BNX_DRV_MSG_DATA_WAIT0		 0x00010000
358 #define BNX_DRV_MSG_DATA_WAIT1		 0x00020000
359 #define BNX_DRV_MSG_DATA_WAIT2		 0x00030000
360 #define BNX_DRV_MSG_DATA_WAIT3		 0x00040000
361 
362 #define BNX_DRV_MSG_SEQ			0x0000ffff
363 
364 #define BNX_FW_MB			0x00000008
365 #define BNX_FW_MSG_ACK			 0x0000ffff
366 #define BNX_FW_MSG_STATUS_MASK		 0x00ff0000
367 #define BNX_FW_MSG_STATUS_OK		 0x00000000
368 #define BNX_FW_MSG_STATUS_FAILURE	 0x00ff0000
369 
370 #define BNX_LINK_STATUS				0x0000000c
371 #define BNX_LINK_STATUS_INIT_VALUE		 0xffffffff
372 #define BNX_LINK_STATUS_LINK_UP			 0x1
373 #define BNX_LINK_STATUS_LINK_DOWN		 0x0
374 #define BNX_LINK_STATUS_SPEED_MASK		 0x1e
375 #define BNX_LINK_STATUS_AN_INCOMPLETE		 (0<<1)
376 #define BNX_LINK_STATUS_10HALF			 (1<<1)
377 #define BNX_LINK_STATUS_10FULL			 (2<<1)
378 #define BNX_LINK_STATUS_100HALF			 (3<<1)
379 #define BNX_LINK_STATUS_100BASE_T4		 (4<<1)
380 #define BNX_LINK_STATUS_100FULL			 (5<<1)
381 #define BNX_LINK_STATUS_1000HALF		 (6<<1)
382 #define BNX_LINK_STATUS_1000FULL		 (7<<1)
383 #define BNX_LINK_STATUS_2500HALF		 (8<<1)
384 #define BNX_LINK_STATUS_2500FULL		 (9<<1)
385 #define BNX_LINK_STATUS_AN_ENABLED		 (1<<5)
386 #define BNX_LINK_STATUS_AN_COMPLETE		 (1<<6)
387 #define BNX_LINK_STATUS_PARALLEL_DET		 (1<<7)
388 #define BNX_LINK_STATUS_RESERVED		 (1<<8)
389 #define BNX_LINK_STATUS_PARTNER_AD_1000FULL	 (1<<9)
390 #define BNX_LINK_STATUS_PARTNER_AD_1000HALF	 (1<<10)
391 #define BNX_LINK_STATUS_PARTNER_AD_100BT4	 (1<<11)
392 #define BNX_LINK_STATUS_PARTNER_AD_100FULL	 (1<<12)
393 #define BNX_LINK_STATUS_PARTNER_AD_100HALF	 (1<<13)
394 #define BNX_LINK_STATUS_PARTNER_AD_10FULL	 (1<<14)
395 #define BNX_LINK_STATUS_PARTNER_AD_10HALF	 (1<<15)
396 #define BNX_LINK_STATUS_TX_FC_ENABLED		 (1<<16)
397 #define BNX_LINK_STATUS_RX_FC_ENABLED		 (1<<17)
398 #define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP	 (1<<18)
399 #define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP	 (1<<19)
400 #define BNX_LINK_STATUS_SERDES_LINK		 (1<<20)
401 #define BNX_LINK_STATUS_PARTNER_AD_2500FULL	 (1<<21)
402 #define BNX_LINK_STATUS_PARTNER_AD_2500HALF	 (1<<22)
403 
404 #define BNX_DRV_PULSE_MB			0x00000010
405 #define BNX_DRV_PULSE_SEQ_MASK			 0x00007fff
406 
407 #define BNX_MB_ARGS_0				0x00000014
408 #define BNX_MB_ARGS_1				0x00000018
409 
410 /* Indicate to the firmware not to go into the
411  * OS absent when it is not getting driver pulse.
412  * This is used for debugging. */
413 #define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE	 0x00080000
414 
415 #define BNX_DEV_INFO_SIGNATURE			0x00000020
416 #define BNX_DEV_INFO_SIGNATURE_MAGIC		 0x44564900
417 #define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK	 0xffffff00
418 #define BNX_DEV_INFO_FEATURE_CFG_VALID		 0x01
419 #define BNX_DEV_INFO_SECONDARY_PORT		 0x80
420 #define BNX_DEV_INFO_DRV_ALWAYS_ALIVE		 0x40
421 
422 #define BNX_SHARED_HW_CFG_PART_NUM		0x00000024
423 
424 #define BNX_SHARED_HW_CFG_POWER_DISSIPATED	0x00000034
425 #define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK	 0xff000000
426 #define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK	 0xff0000
427 #define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK	 0xff00
428 #define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK	 0xff
429 
430 #define BNX_SHARED_HW_CFG_POWER_CONSUMED	0x00000038
431 #define BNX_SHARED_HW_CFG_CONFIG		0x0000003c
432 #define BNX_SHARED_HW_CFG_DESIGN_NIC		 0
433 #define BNX_SHARED_HW_CFG_DESIGN_LOM		 0x1
434 #define BNX_SHARED_HW_CFG_PHY_COPPER		 0
435 #define BNX_SHARED_HW_CFG_PHY_FIBER		 0x2
436 #define BNX_SHARED_HW_CFG_PHY_2_5G		 0x20
437 #define BNX_SHARED_HW_CFG_PHY_BACKPLANE		 0x40
438 #define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS	 8
439 #define BNX_SHARED_HW_CFG_LED_MODE_MASK		 0x300
440 #define BNX_SHARED_HW_CFG_LED_MODE_MAC		 0
441 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY1	 0x100
442 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY2	 0x200
443 
444 #define BNX_SHARED_HW_CFG_CONFIG2		0x00000040
445 #define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK	 0x00fff000
446 
447 #define BNX_DEV_INFO_BC_REV			0x0000004c
448 
449 #define BNX_PORT_HW_CFG_MAC_UPPER		0x00000050
450 #define BNX_PORT_HW_CFG_UPPERMAC_MASK		 0xffff
451 
452 #define BNX_PORT_HW_CFG_MAC_LOWER		0x00000054
453 #define BNX_PORT_HW_CFG_CONFIG			0x00000058
454 #define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK		 0x0000ffff
455 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK	 0x001f0000
456 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN	 0x00000000
457 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G	 0x00030000
458 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G	 0x00040000
459 
460 #define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER		0x00000068
461 #define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER		0x0000006c
462 #define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER		0x00000070
463 #define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER		0x00000074
464 #define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER		0x00000078
465 #define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER		0x0000007c
466 
467 #define BNX_DEV_INFO_PER_PORT_HW_CONFIG2	0x000000b4
468 
469 #define BNX_DEV_INFO_FORMAT_REV		0x000000c4
470 #define BNX_DEV_INFO_FORMAT_REV_MASK	 0xff000000
471 #define BNX_DEV_INFO_FORMAT_REV_ID	 ('A' << 24)
472 
473 #define BNX_SHARED_FEATURE		0x000000c8
474 #define BNX_SHARED_FEATURE_MASK		 0xffffffff
475 
476 #define BNX_PORT_FEATURE			0x000000d8
477 #define BNX_PORT2_FEATURE			0x00000014c
478 #define BNX_PORT_FEATURE_WOL_ENABLED		 0x01000000
479 #define BNX_PORT_FEATURE_MBA_ENABLED		 0x02000000
480 #define BNX_PORT_FEATURE_ASF_ENABLED		 0x04000000
481 #define BNX_PORT_FEATURE_IMD_ENABLED		 0x08000000
482 #define BNX_PORT_FEATURE_BAR1_SIZE_MASK		 0xf
483 #define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED	 0x0
484 #define BNX_PORT_FEATURE_BAR1_SIZE_64K		 0x1
485 #define BNX_PORT_FEATURE_BAR1_SIZE_128K		 0x2
486 #define BNX_PORT_FEATURE_BAR1_SIZE_256K		 0x3
487 #define BNX_PORT_FEATURE_BAR1_SIZE_512K		 0x4
488 #define BNX_PORT_FEATURE_BAR1_SIZE_1M		 0x5
489 #define BNX_PORT_FEATURE_BAR1_SIZE_2M		 0x6
490 #define BNX_PORT_FEATURE_BAR1_SIZE_4M		 0x7
491 #define BNX_PORT_FEATURE_BAR1_SIZE_8M		 0x8
492 #define BNX_PORT_FEATURE_BAR1_SIZE_16M		 0x9
493 #define BNX_PORT_FEATURE_BAR1_SIZE_32M		 0xa
494 #define BNX_PORT_FEATURE_BAR1_SIZE_64M		 0xb
495 #define BNX_PORT_FEATURE_BAR1_SIZE_128M		 0xc
496 #define BNX_PORT_FEATURE_BAR1_SIZE_256M		 0xd
497 #define BNX_PORT_FEATURE_BAR1_SIZE_512M		 0xe
498 #define BNX_PORT_FEATURE_BAR1_SIZE_1G		 0xf
499 
500 #define BNX_PORT_FEATURE_WOL				0xdc
501 #define BNX_PORT2_FEATURE_WOL				0x150
502 #define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS		 4
503 #define BNX_PORT_FEATURE_WOL_DEFAULT_MASK		 0x30
504 #define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE		 0
505 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC		 0x10
506 #define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI		 0x20
507 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI	 0x30
508 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK		 0xf
509 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG		 0
510 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF		 1
511 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL		 2
512 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF		 3
513 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL		 4
514 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF	 5
515 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL	 6
516 #define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000	 0x40
517 #define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP		 0x400
518 #define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP	 0x800
519 
520 #define BNX_PORT_FEATURE_MBA				0xe0
521 #define BNX_PORT2_FEATURE_MBA				0x154
522 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS	 0
523 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK	 0x3
524 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE	 0
525 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL	 1
526 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP	 2
527 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS	 2
528 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK		 0x3c
529 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG		 0
530 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF		 0x4
531 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL		 0x8
532 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF		 0xc
533 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL		 0x10
534 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF	 0x14
535 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL	 0x18
536 #define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE	 0x40
537 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S		 0
538 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B		 0x80
539 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS	 8
540 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK		 0xff00
541 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED	 0
542 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K		 0x100
543 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K		 0x200
544 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K		 0x300
545 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K		 0x400
546 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K		 0x500
547 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K		 0x600
548 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K		 0x700
549 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K		 0x800
550 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K		 0x900
551 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K		 0xa00
552 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M		 0xb00
553 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M		 0xc00
554 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M		 0xd00
555 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M		 0xe00
556 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M		 0xf00
557 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS	 16
558 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK		 0xf0000
559 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS	 20
560 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK	 0x300000
561 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO	 0
562 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS		 0x100000
563 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H	 0x200000
564 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H	 0x300000
565 
566 #define BNX_PORT_FEATURE_IMD				0xe4
567 #define BNX_PORT2_FEATURE_IMD				0x158
568 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT	 0
569 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE	 1
570 
571 #define BNX_PORT_FEATURE_VLAN			0xe8
572 #define BNX_PORT2_FEATURE_VLAN			0x15c
573 #define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK	 0xffff
574 #define BNX_PORT_FEATURE_MBA_VLAN_ENABLE	 0x10000
575 
576 #define BNX_MFW_VER_PTR				0x00000014c
577 
578 #define BNX_BC_STATE_RESET_TYPE			0x000001c0
579 #define BNX_BC_STATE_RESET_TYPE_SIG		 0x00005254
580 #define BNX_BC_STATE_RESET_TYPE_SIG_MASK	 0x0000ffff
581 #define BNX_BC_STATE_RESET_TYPE_NONE			\
582 	(BNX_BC_STATE_RESET_TYPE_SIG | 0x00010000)
583 #define BNX_BC_STATE_RESET_TYPE_PCI			\
584 	(BNX_BC_STATE_RESET_TYPE_SIG | 0x00020000)
585 #define BNX_BC_STATE_RESET_TYPE_VAUX			\
586 	(BNX_BC_STATE_RESET_TYPE_SIG | 0x00030000)
587 #define BNX_BC_STATE_RESET_TYPE_DRV_MASK	DRV_MSG_CODE
588 #define BNX_BC_STATE_RESET_TYPE_DRV_RESET		\
589 	(BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_RESET)
590 #define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD		\
591 	(BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_UNLOAD)
592 #define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN		\
593 	(BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_SHUTDOWN)
594 #define BNX_BC_STATE_RESET_TYPE_DRV_WOL			\
595 	(BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_WOL)
596 #define BNX_BC_STATE_RESET_TYPE_DRV_DIAG		\
597 	(BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_DIAG)
598 #define BNX_BC_STATE_RESET_TYPE_VALUE(msg)		\
599 	(BNX_BC_STATE_RESET_TYPE_SIG | (msg))
600 
601 #define BNX_BC_STATE				0x000001c4
602 #define BNX_BC_STATE_ERR_MASK			 0x0000ff00
603 #define BNX_BC_STATE_SIGN			 0x42530000
604 #define BNX_BC_STATE_SIGN_MASK			 0xffff0000
605 #define BNX_BC_STATE_BC1_START			 (BNX_BC_STATE_SIGN | 0x1)
606 #define BNX_BC_STATE_GET_NVM_CFG1		 (BNX_BC_STATE_SIGN | 0x2)
607 #define BNX_BC_STATE_PROG_BAR			 (BNX_BC_STATE_SIGN | 0x3)
608 #define BNX_BC_STATE_INIT_VID			 (BNX_BC_STATE_SIGN | 0x4)
609 #define BNX_BC_STATE_GET_NVM_CFG2		 (BNX_BC_STATE_SIGN | 0x5)
610 #define BNX_BC_STATE_APPLY_WKARND		 (BNX_BC_STATE_SIGN | 0x6)
611 #define BNX_BC_STATE_LOAD_BC2			 (BNX_BC_STATE_SIGN | 0x7)
612 #define BNX_BC_STATE_GOING_BC2			 (BNX_BC_STATE_SIGN | 0x8)
613 #define BNX_BC_STATE_GOING_DIAG			 (BNX_BC_STATE_SIGN | 0x9)
614 #define BNX_BC_STATE_RT_FINAL_INIT		 (BNX_BC_STATE_SIGN | 0x81)
615 #define BNX_BC_STATE_RT_WKARND			 (BNX_BC_STATE_SIGN | 0x82)
616 #define BNX_BC_STATE_RT_DRV_PULSE		 (BNX_BC_STATE_SIGN | 0x83)
617 #define BNX_BC_STATE_RT_FIOEVTS			 (BNX_BC_STATE_SIGN | 0x84)
618 #define BNX_BC_STATE_RT_DRV_CMD			 (BNX_BC_STATE_SIGN | 0x85)
619 #define BNX_BC_STATE_RT_LOW_POWER		 (BNX_BC_STATE_SIGN | 0x86)
620 #define BNX_BC_STATE_RT_SET_WOL			 (BNX_BC_STATE_SIGN | 0x87)
621 #define BNX_BC_STATE_RT_OTHER_FW		 (BNX_BC_STATE_SIGN | 0x88)
622 #define BNX_BC_STATE_RT_GOING_D3		 (BNX_BC_STATE_SIGN | 0x89)
623 #define BNX_BC_STATE_ERR_BAD_VERSION		 (BNX_BC_STATE_SIGN | 0x0100)
624 #define BNX_BC_STATE_ERR_BAD_BC2_CRC		 (BNX_BC_STATE_SIGN | 0x0200)
625 #define BNX_BC_STATE_ERR_BC1_LOOP		 (BNX_BC_STATE_SIGN | 0x0300)
626 #define BNX_BC_STATE_ERR_UNKNOWN_CMD		 (BNX_BC_STATE_SIGN | 0x0400)
627 #define BNX_BC_STATE_ERR_DRV_DEAD		 (BNX_BC_STATE_SIGN | 0x0500)
628 #define BNX_BC_STATE_ERR_NO_RXP			 (BNX_BC_STATE_SIGN | 0x0600)
629 #define BNX_BC_STATE_ERR_TOO_MANY_RBUF		 (BNX_BC_STATE_SIGN | 0x0700)
630 
631 #define BNX_BC_STATE_CONDITION			0x000001c8
632 #define BNX_CONDITION_INIT_POR			 0x00000001
633 #define BNX_CONDITION_INIT_VAUX_AVAIL		 0x00000002
634 #define BNX_CONDITION_INIT_PCI_AVAIL		 0x00000004
635 #define BNX_CONDITION_INIT_PCI_RESET		 0x00000008
636 #define BNX_CONDITION_INIT_HD_RESET		 0x00000010 /* 5709/16 only */
637 #define BNX_CONDITION_DRV_PRESENT		 0x00000100
638 #define BNX_CONDITION_LOW_POWER_LINK		 0x00000200
639 #define BNX_CONDITION_CORE_RST_OCCURRED		 0x00000400 /* 5709/16 only */
640 #define BNX_CONDITION_UNUSED			 0x00000800
641 #define BNX_CONDITION_BUSY_EXPROM		 0x00001000 /* 5706/08 only */
642 
643 #define BNX_CONDITION_MFW_RUN_UNKNOWN		 0x00000000
644 #define BNX_CONDITION_MFW_RUN_IPMI		 0x00002000
645 #define BNX_CONDITION_MFW_RUN_UMP		 0x00004000
646 #define BNX_CONDITION_MFW_RUN_NCSI		 0x00006000
647 #define BNX_CONDITION_MFW_RUN_NONE		 0x0000e000
648 #define BNX_CONDITION_MFW_RUN_MASK		 0x0000e000
649 
650 /* 5709/16 only */
651 #define BNX_CONDITION_PM_STATE_MASK		 0x00030000
652 #define BNX_CONDITION_PM_STATE_FULL		 0x00030000
653 #define BNX_CONDITION_PM_STATE_PREP		 0x00020000
654 #define BNX_CONDITION_PM_STATE_UNPREP		 0x00010000
655 #define BNX_CONDITION_PM_RESERVED		 0x00000000
656 
657 /* 5709/16 only */
658 #define BNX_CONDITION_RXMODE_KEEP_VLAN		 0x00040000
659 #define BNX_CONDITION_DRV_WOL_ENABLED		 0x00080000
660 #define BNX_CONDITION_PORT_DISABLED		 0x00100000
661 #define BNX_CONDITION_DRV_MAYBE_OUT		 0x00200000
662 #define BNX_CONDITION_DPFW_DEAD			 0x00400000
663 
664 #define BNX_BC_STATE_DEBUG_CMD			0x1dc
665 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE	 0x42440000
666 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK	 0xffff0000
667 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK	 0xffff
668 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE	 0xffff
669 
670 #define HOST_VIEW_SHMEM_BASE			0x167c00
671 
672 /****************************************************************************/
673 /* Convenience definitions.						    */
674 /****************************************************************************/
675 #define	BNX_PRINTF(sc, fmt, ...)	\
676 	device_printf((sc)->bnx_dev, fmt, __VA_ARGS__)
677 #define BNX_STATS(x)			(u_long) stats->stat_ ## x ## _lo
678 
679 /*
680  * The following data structures are generated from RTL code.
681  * Do not modify any values below this line.
682  */
683 
684 /****************************************************************************/
685 /* Do not modify any of the following data structures, they are generated   */
686 /* from RTL code.							    */
687 /*									    */
688 /* Begin machine generated definitions.					    */
689 /****************************************************************************/
690 
691 /*
692  *  tx_bd definition
693  */
694 struct tx_bd {
695 	uint32_t tx_bd_haddr_hi;
696 	uint32_t tx_bd_haddr_lo;
697 	uint32_t tx_bd_mss_nbytes;
698 #if BYTE_ORDER == BIG_ENDIAN
699 	uint16_t tx_bd_vlan_tag;
700 	uint16_t tx_bd_flags;
701 #else
702 	uint16_t tx_bd_flags;
703 	uint16_t tx_bd_vlan_tag;
704 #endif
705 #define TX_BD_FLAGS_CONN_FAULT		(1<<0)
706 #define TX_BD_FLAGS_TCP_UDP_CKSUM	(1<<1)
707 #define TX_BD_FLAGS_IP_CKSUM		(1<<2)
708 #define TX_BD_FLAGS_VLAN_TAG		(1<<3)
709 #define TX_BD_FLAGS_COAL_NOW		(1<<4)
710 #define TX_BD_FLAGS_DONT_GEN_CRC	(1<<5)
711 #define TX_BD_FLAGS_END			(1<<6)
712 #define TX_BD_FLAGS_START		(1<<7)
713 #define TX_BD_FLAGS_SW_OPTION_WORD	(0x1f<<8)
714 #define TX_BD_FLAGS_SW_FLAGS		(1<<13)
715 #define TX_BD_FLAGS_SW_SNAP		(1<<14)
716 #define TX_BD_FLAGS_SW_LSO		(1<<15)
717 };
718 
719 
720 /*
721  *  rx_bd definition
722  */
723 struct rx_bd {
724 	uint32_t rx_bd_haddr_hi;
725 	uint32_t rx_bd_haddr_lo;
726 	uint32_t rx_bd_len;
727 	uint32_t rx_bd_flags;
728 #define RX_BD_FLAGS_NOPUSH		(1<<0)
729 #define RX_BD_FLAGS_DUMMY		(1<<1)
730 #define RX_BD_FLAGS_END			(1<<2)
731 #define RX_BD_FLAGS_START		(1<<3)
732 };
733 
734 
735 /*
736  *  status_block definition
737  */
738 struct status_block {
739 	uint32_t status_attn_bits;
740 #define STATUS_ATTN_BITS_LINK_STATE		(1L<<0)
741 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT	(1L<<1)
742 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT	(1L<<2)
743 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT	(1L<<3)
744 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT	(1L<<4)
745 #define STATUS_ATTN_BITS_TX_DMA_ABORT		(1L<<5)
746 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT	(1L<<6)
747 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT	(1L<<7)
748 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT	(1L<<8)
749 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT	(1L<<9)
750 #define STATUS_ATTN_BITS_RX_MBUF_ABORT		(1L<<10)
751 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT	(1L<<11)
752 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT	(1L<<12)
753 #define STATUS_ATTN_BITS_RX_V2P_ABORT		(1L<<13)
754 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT	(1L<<14)
755 #define STATUS_ATTN_BITS_RX_DMA_ABORT		(1L<<15)
756 #define STATUS_ATTN_BITS_COMPLETION_ABORT	(1L<<16)
757 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT	(1L<<17)
758 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT	(1L<<18)
759 #define STATUS_ATTN_BITS_CONTEXT_ABORT		(1L<<19)
760 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT	(1L<<20)
761 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT	(1L<<21)
762 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT	(1L<<22)
763 #define STATUS_ATTN_BITS_MAC_ABORT		(1L<<23)
764 #define STATUS_ATTN_BITS_TIMER_ABORT		(1L<<24)
765 #define STATUS_ATTN_BITS_DMAE_ABORT		(1L<<25)
766 #define STATUS_ATTN_BITS_FLSH_ABORT		(1L<<26)
767 #define STATUS_ATTN_BITS_GRC_ABORT		(1L<<27)
768 #define STATUS_ATTN_BITS_PARITY_ERROR		(1L<<31)
769 
770 	uint32_t status_attn_bits_ack;
771 #if BYTE_ORDER == BIG_ENDIAN
772 	uint16_t status_tx_quick_consumer_index0;
773 	uint16_t status_tx_quick_consumer_index1;
774 	uint16_t status_tx_quick_consumer_index2;
775 	uint16_t status_tx_quick_consumer_index3;
776 	uint16_t status_rx_quick_consumer_index0;
777 	uint16_t status_rx_quick_consumer_index1;
778 	uint16_t status_rx_quick_consumer_index2;
779 	uint16_t status_rx_quick_consumer_index3;
780 	uint16_t status_rx_quick_consumer_index4;
781 	uint16_t status_rx_quick_consumer_index5;
782 	uint16_t status_rx_quick_consumer_index6;
783 	uint16_t status_rx_quick_consumer_index7;
784 	uint16_t status_rx_quick_consumer_index8;
785 	uint16_t status_rx_quick_consumer_index9;
786 	uint16_t status_rx_quick_consumer_index10;
787 	uint16_t status_rx_quick_consumer_index11;
788 	uint16_t status_rx_quick_consumer_index12;
789 	uint16_t status_rx_quick_consumer_index13;
790 	uint16_t status_rx_quick_consumer_index14;
791 	uint16_t status_rx_quick_consumer_index15;
792 	uint16_t status_completion_producer_index;
793 	uint16_t status_cmd_consumer_index;
794 	uint16_t status_idx;
795 	uint16_t status_unused;
796 #elif BYTE_ORDER == LITTLE_ENDIAN
797 	uint16_t status_tx_quick_consumer_index1;
798 	uint16_t status_tx_quick_consumer_index0;
799 	uint16_t status_tx_quick_consumer_index3;
800 	uint16_t status_tx_quick_consumer_index2;
801 	uint16_t status_rx_quick_consumer_index1;
802 	uint16_t status_rx_quick_consumer_index0;
803 	uint16_t status_rx_quick_consumer_index3;
804 	uint16_t status_rx_quick_consumer_index2;
805 	uint16_t status_rx_quick_consumer_index5;
806 	uint16_t status_rx_quick_consumer_index4;
807 	uint16_t status_rx_quick_consumer_index7;
808 	uint16_t status_rx_quick_consumer_index6;
809 	uint16_t status_rx_quick_consumer_index9;
810 	uint16_t status_rx_quick_consumer_index8;
811 	uint16_t status_rx_quick_consumer_index11;
812 	uint16_t status_rx_quick_consumer_index10;
813 	uint16_t status_rx_quick_consumer_index13;
814 	uint16_t status_rx_quick_consumer_index12;
815 	uint16_t status_rx_quick_consumer_index15;
816 	uint16_t status_rx_quick_consumer_index14;
817 	uint16_t status_cmd_consumer_index;
818 	uint16_t status_completion_producer_index;
819 	uint16_t status_unused;
820 	uint16_t status_idx;
821 #endif
822 };
823 
824 
825 /*
826  *  statistics_block definition
827  */
828 struct statistics_block {
829 	uint32_t stat_IfHCInOctets_hi;
830 	uint32_t stat_IfHCInOctets_lo;
831 	uint32_t stat_IfHCInBadOctets_hi;
832 	uint32_t stat_IfHCInBadOctets_lo;
833 	uint32_t stat_IfHCOutOctets_hi;
834 	uint32_t stat_IfHCOutOctets_lo;
835 	uint32_t stat_IfHCOutBadOctets_hi;
836 	uint32_t stat_IfHCOutBadOctets_lo;
837 	uint32_t stat_IfHCInUcastPkts_hi;
838 	uint32_t stat_IfHCInUcastPkts_lo;
839 	uint32_t stat_IfHCInMulticastPkts_hi;
840 	uint32_t stat_IfHCInMulticastPkts_lo;
841 	uint32_t stat_IfHCInBroadcastPkts_hi;
842 	uint32_t stat_IfHCInBroadcastPkts_lo;
843 	uint32_t stat_IfHCOutUcastPkts_hi;
844 	uint32_t stat_IfHCOutUcastPkts_lo;
845 	uint32_t stat_IfHCOutMulticastPkts_hi;
846 	uint32_t stat_IfHCOutMulticastPkts_lo;
847 	uint32_t stat_IfHCOutBroadcastPkts_hi;
848 	uint32_t stat_IfHCOutBroadcastPkts_lo;
849 	uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
850 	uint32_t stat_Dot3StatsCarrierSenseErrors;
851 	uint32_t stat_Dot3StatsFCSErrors;
852 	uint32_t stat_Dot3StatsAlignmentErrors;
853 	uint32_t stat_Dot3StatsSingleCollisionFrames;
854 	uint32_t stat_Dot3StatsMultipleCollisionFrames;
855 	uint32_t stat_Dot3StatsDeferredTransmissions;
856 	uint32_t stat_Dot3StatsExcessiveCollisions;
857 	uint32_t stat_Dot3StatsLateCollisions;
858 	uint32_t stat_EtherStatsCollisions;
859 	uint32_t stat_EtherStatsFragments;
860 	uint32_t stat_EtherStatsJabbers;
861 	uint32_t stat_EtherStatsUndersizePkts;
862 	uint32_t stat_EtherStatsOverrsizePkts;
863 	uint32_t stat_EtherStatsPktsRx64Octets;
864 	uint32_t stat_EtherStatsPktsRx65Octetsto127Octets;
865 	uint32_t stat_EtherStatsPktsRx128Octetsto255Octets;
866 	uint32_t stat_EtherStatsPktsRx256Octetsto511Octets;
867 	uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
868 	uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
869 	uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
870 	uint32_t stat_EtherStatsPktsTx64Octets;
871 	uint32_t stat_EtherStatsPktsTx65Octetsto127Octets;
872 	uint32_t stat_EtherStatsPktsTx128Octetsto255Octets;
873 	uint32_t stat_EtherStatsPktsTx256Octetsto511Octets;
874 	uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
875 	uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
876 	uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
877 	uint32_t stat_XonPauseFramesReceived;
878 	uint32_t stat_XoffPauseFramesReceived;
879 	uint32_t stat_OutXonSent;
880 	uint32_t stat_OutXoffSent;
881 	uint32_t stat_FlowControlDone;
882 	uint32_t stat_MacControlFramesReceived;
883 	uint32_t stat_XoffStateEntered;
884 	uint32_t stat_IfInFramesL2FilterDiscards;
885 	uint32_t stat_IfInRuleCheckerDiscards;
886 	uint32_t stat_IfInFTQDiscards;
887 	uint32_t stat_IfInMBUFDiscards;
888 	uint32_t stat_IfInRuleCheckerP4Hit;
889 	uint32_t stat_CatchupInRuleCheckerDiscards;
890 	uint32_t stat_CatchupInFTQDiscards;
891 	uint32_t stat_CatchupInMBUFDiscards;
892 	uint32_t stat_CatchupInRuleCheckerP4Hit;
893 	uint32_t stat_GenStat00;
894 	uint32_t stat_GenStat01;
895 	uint32_t stat_GenStat02;
896 	uint32_t stat_GenStat03;
897 	uint32_t stat_GenStat04;
898 	uint32_t stat_GenStat05;
899 	uint32_t stat_GenStat06;
900 	uint32_t stat_GenStat07;
901 	uint32_t stat_GenStat08;
902 	uint32_t stat_GenStat09;
903 	uint32_t stat_GenStat10;
904 	uint32_t stat_GenStat11;
905 	uint32_t stat_GenStat12;
906 	uint32_t stat_GenStat13;
907 	uint32_t stat_GenStat14;
908 	uint32_t stat_GenStat15;
909 };
910 
911 
912 /*
913  *  l2_fhdr definition
914  */
915 struct l2_fhdr {
916 	uint32_t l2_fhdr_status;
917 #define L2_FHDR_STATUS_RULE_CLASS	(0x7<<0)
918 #define L2_FHDR_STATUS_RULE_P2		(1<<3)
919 #define L2_FHDR_STATUS_RULE_P3		(1<<4)
920 #define L2_FHDR_STATUS_RULE_P4		(1<<5)
921 #define L2_FHDR_STATUS_L2_VLAN_TAG	(1<<6)
922 #define L2_FHDR_STATUS_L2_LLC_SNAP	(1<<7)
923 #define L2_FHDR_STATUS_RSS_HASH		(1<<8)
924 #define L2_FHDR_STATUS_IP_DATAGRAM	(1<<13)
925 #define L2_FHDR_STATUS_TCP_SEGMENT	(1<<14)
926 #define L2_FHDR_STATUS_UDP_DATAGRAM	(1<<15)
927 
928 #define L2_FHDR_ERRORS_BAD_CRC		(1<<17)
929 #define L2_FHDR_ERRORS_PHY_DECODE	(1<<18)
930 #define L2_FHDR_ERRORS_ALIGNMENT	(1<<19)
931 #define L2_FHDR_ERRORS_TOO_SHORT	(1<<20)
932 #define L2_FHDR_ERRORS_GIANT_FRAME	(1<<21)
933 #define L2_FHDR_ERRORS_TCP_XSUM		(1<<28)
934 #define L2_FHDR_ERRORS_UDP_XSUM		(1<<31)
935 
936 	uint32_t l2_fhdr_hash;
937 #if BYTE_ORDER == BIG_ENDIAN
938 	uint16_t l2_fhdr_pkt_len;
939 	uint16_t l2_fhdr_vlan_tag;
940 	uint16_t l2_fhdr_ip_xsum;
941 	uint16_t l2_fhdr_tcp_udp_xsum;
942 #elif BYTE_ORDER == LITTLE_ENDIAN
943 	uint16_t l2_fhdr_vlan_tag;
944 	uint16_t l2_fhdr_pkt_len;
945 	uint16_t l2_fhdr_tcp_udp_xsum;
946 	uint16_t l2_fhdr_ip_xsum;
947 #endif
948 };
949 
950 
951 /*
952  *  l2_context definition
953  */
954 #define BNX_L2CTX_TYPE				0x00000000
955 #define BNX_L2CTX_TYPE_SIZE_L2			 ((0xc0/0x20)<<16)
956 #define BNX_L2CTX_TYPE_TYPE			 (0xf<<28)
957 #define BNX_L2CTX_TYPE_TYPE_EMPTY		 (0<<28)
958 #define BNX_L2CTX_TYPE_TYPE_L2			 (1<<28)
959 
960 #define BNX_L2CTX_TYPE_XI			0x00000080
961 #define BNX_L2CTX_TX_HOST_BIDX			0x00000088
962 #define BNX_L2CTX_EST_NBD			0x00000088
963 #define BNX_L2CTX_CMD_TYPE			0x00000088
964 #define BNX_L2CTX_CMD_TYPE_TYPE			 (0xf<<24)
965 #define BNX_L2CTX_CMD_TYPE_TYPE_L2		 (0<<24)
966 #define BNX_L2CTX_CMD_TYPE_TYPE_TCP		 (1<<24)
967 
968 #define BNX_L2CTX_TX_HOST_BSEQ			0x00000090
969 #define BNX_L2CTX_TSCH_BSEQ			0x00000094
970 #define BNX_L2CTX_TBDR_BSEQ			0x00000098
971 #define BNX_L2CTX_TBDR_BOFF			0x0000009c
972 #define BNX_L2CTX_TBDR_BIDX			0x0000009c
973 #define BNX_L2CTX_TBDR_BHADDR_HI		0x000000a0
974 #define BNX_L2CTX_TBDR_BHADDR_LO		0x000000a4
975 #define BNX_L2CTX_TXP_BOFF			0x000000a8
976 #define BNX_L2CTX_TXP_BIDX			0x000000a8
977 #define BNX_L2CTX_TXP_BSEQ			0x000000ac
978 
979 #define BNX_L2CTX_CMD_TYPE_XI			0x00000240
980 #define BNX_L2CTX_TBDR_BHADDR_HI_XI		0x00000258
981 #define BNX_L2CTX_TBDR_BHADDR_LO_XI		0x0000025c
982 
983 /*
984  *  l2_bd_chain_context definition
985  */
986 #define BNX_L2CTX_BD_PRE_READ				0x00000000
987 #define BNX_L2CTX_CTX_SIZE				0x00000000
988 #define BNX_L2CTX_CTX_TYPE				0x00000000
989 #define BNX_L2CTX_CTX_TYPE_SIZE_L2			 ((0x20/20)<<16)
990 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE		 (0xf<<28)
991 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED	 (0<<28)
992 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE	 (1<<28)
993 
994 #define BNX_L2CTX_HOST_BDIDX			0x00000004
995 #define BNX_L2CTX_HOST_BSEQ			0x00000008
996 #define BNX_L2CTX_NX_BSEQ			0x0000000c
997 #define BNX_L2CTX_NX_BDHADDR_HI			0x00000010
998 #define BNX_L2CTX_NX_BDHADDR_LO			0x00000014
999 #define BNX_L2CTX_NX_BDIDX			0x00000018
1000 
1001 /*
1002  *  l2_rx_context definition (5706, 5708, 5709, and 5716)
1003  */
1004 #define BNX_L2CTX_RX_WATER_MARK			0x00000000
1005 #define BNX_L2CTX_RX_LO_WATER_MARK_SHIFT	0
1006 #define BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT	32
1007 #define BNX_L2CTX_RX_LO_WATER_MARK_SCALE	4
1008 #define BNX_L2CTX_RX_LO_WATER_MARK_DIS		0
1009 #define BNX_L2CTX_RX_HI_WATER_MARK_SHIFT	4
1010 #define BNX_L2CTX_RX_HI_WATER_MARK_SCALE	16
1011 #define BNX_L2CTX_RX_WATER_MARKS_MSK		0x000000ff
1012 
1013 #define BNX_L2CTX_RX_BD_PRE_READ		0x00000000
1014 #define BNX_L2CTX_RX_BD_PRE_READ_SHIFT		8
1015 
1016 #define BNX_L2CTX_RX_CTX_SIZE			0x00000000
1017 #define BNX_L2CTX_RX_CTX_SIZE_SHIFT		16
1018 #define BNX_L2CTX_RX_CTX_TYPE_SIZE_L2	\
1019 	((0x20/20)<<BNX_L2CTX_RX_CTX_SIZE_SHIFT)
1020 
1021 #define BNX_L2CTX_RX_CTX_TYPE			0x00000000
1022 #define BNX_L2CTX_RX_CTX_TYPE_SHIFT		24
1023 
1024 #define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE	(0xf<<28)
1025 #define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
1026 #define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE	(1<<28)
1027 
1028 #define BNX_L2CTX_RX_HOST_BDIDX			0x00000004
1029 #define BNX_L2CTX_RX_HOST_BSEQ			0x00000008
1030 #define BNX_L2CTX_RX_NX_BSEQ			0x0000000c
1031 #define BNX_L2CTX_RX_NX_BDHADDR_HI		0x00000010
1032 #define BNX_L2CTX_RX_NX_BDHADDR_LO		0x00000014
1033 #define BNX_L2CTX_RX_NX_BDIDX			0x00000018
1034 
1035 #define BNX_L2CTX_RX_HOST_PG_BDIDX		0x00000044
1036 #define BNX_L2CTX_RX_PG_BUF_SIZE		0x00000048
1037 #define BNX_L2CTX_RX_RBDC_KEY			0x0000004c
1038 #define BNX_L2CTX_RX_RBDC_JUMBO_KEY		0x3ffe
1039 #define BNX_L2CTX_RX_NX_PG_BDHADDR_HI		0x00000050
1040 #define BNX_L2CTX_RX_NX_PG_BDHADDR_LO		0x00000054
1041 #define BNX_L2CTX_RX_NX_PG_BDIDX		0x00000058
1042 
1043 /*
1044  *  pci_config_l definition
1045  *  offset: 0000
1046  */
1047 #define BNX_PCICFG_MISC_CONFIG				0x00000068
1048 #define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP		 (1L<<2)
1049 #define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP	 (1L<<3)
1050 #define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA		 (1L<<5)
1051 #define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP	 (1L<<6)
1052 #define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA		 (1L<<7)
1053 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ		 (1L<<8)
1054 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY		 (1L<<9)
1055 #define BNX_PCICFG_MISC_CONFIG_ASIC_METAL_REV		 (0xffL<<16)
1056 #define BNX_PCICFG_MISC_CONFIG_ASIC_BASE_REV		 (0xfL<<24)
1057 #define BNX_PCICFG_MISC_CONFIG_ASIC_ID			 (0xfL<<28)
1058 #define BNX_PCICFG_MISC_CONFIG_ASIC_REV			 (0xffffL<<16)
1059 
1060 #define BNX_PCICFG_MISC_STATUS				0x0000006c
1061 #define BNX_PCICFG_MISC_STATUS_INTA_VALUE		 (1L<<0)
1062 #define BNX_PCICFG_MISC_STATUS_32BIT_DET		 (1L<<1)
1063 #define BNX_PCICFG_MISC_STATUS_M66EN			 (1L<<2)
1064 #define BNX_PCICFG_MISC_STATUS_PCIX_DET			 (1L<<3)
1065 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED		 (0x3L<<4)
1066 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66		 (0L<<4)
1067 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100		 (1L<<4)
1068 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133		 (2L<<4)
1069 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE	 (3L<<4)
1070 
1071 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS			0x00000070
1072 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
1073 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1074 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1075 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1076 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1077 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1078 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1079 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1080 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1081 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
1082 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
1083 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT		 (1L<<7)
1084 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
1085 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1086 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
1087 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
1088 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
1089 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD		 (1L<<11)
1090 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
1091 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1092 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1093 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1094 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1095 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1096 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
1097 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP		 (1L<<17)
1098 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18		 (1L<<18)
1099 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET		 (1L<<19)
1100 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED		 (0xfffL<<20)
1101 
1102 #define BNX_PCICFG_REG_WINDOW_ADDRESS			0x00000078
1103 #define BNX_PCICFG_REG_WINDOW				0x00000080
1104 #define BNX_PCICFG_INT_ACK_CMD				0x00000084
1105 #define BNX_PCICFG_INT_ACK_CMD_INDEX			 (0xffffL<<0)
1106 #define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID		 (1L<<16)
1107 #define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM		 (1L<<17)
1108 #define BNX_PCICFG_INT_ACK_CMD_MASK_INT			 (1L<<18)
1109 
1110 #define BNX_PCICFG_STATUS_BIT_SET_CMD		0x00000088
1111 #define BNX_PCICFG_STATUS_BIT_CLEAR_CMD		0x0000008c
1112 #define BNX_PCICFG_MAILBOX_QUEUE_ADDR		0x00000090
1113 #define BNX_PCICFG_MAILBOX_QUEUE_DATA		0x00000094
1114 
1115 /* From NetXtremeII-PG203-R.pdf page 182 */
1116 #define BNX_PCICFG_DEVICE_CONTROL			0x000000b4
1117 
1118 
1119 /*
1120  *  pci_reg definition
1121  *  offset: 0x400
1122  */
1123 #define BNX_PCI_GRC_WINDOW_ADDR			0x00000400
1124 #define BNX_PCI_GRC_WINDOW_ADDR_VALUE		 (0x3ffffL<<8)
1125 
1126 #define BNX_PCI_CONFIG_1			0x00000404
1127 #define BNX_PCI_CONFIG_1_READ_BOUNDARY		 (0x7L<<8)
1128 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF	 (0L<<8)
1129 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_16	 (1L<<8)
1130 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_32	 (2L<<8)
1131 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_64	 (3L<<8)
1132 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_128	 (4L<<8)
1133 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_256	 (5L<<8)
1134 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_512	 (6L<<8)
1135 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024	 (7L<<8)
1136 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY		 (0x7L<<11)
1137 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF	 (0L<<11)
1138 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16	 (1L<<11)
1139 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32	 (2L<<11)
1140 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64	 (3L<<11)
1141 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128	 (4L<<11)
1142 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256	 (5L<<11)
1143 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512	 (6L<<11)
1144 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024	 (7L<<11)
1145 
1146 #define BNX_PCI_CONFIG_2			0x00000408
1147 #define BNX_PCI_CONFIG_2_BAR1_SIZE		 (0xfL<<0)
1148 #define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED	 (0L<<0)
1149 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64K		 (1L<<0)
1150 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128K		 (2L<<0)
1151 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256K		 (3L<<0)
1152 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512K		 (4L<<0)
1153 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1M		 (5L<<0)
1154 #define BNX_PCI_CONFIG_2_BAR1_SIZE_2M		 (6L<<0)
1155 #define BNX_PCI_CONFIG_2_BAR1_SIZE_4M		 (7L<<0)
1156 #define BNX_PCI_CONFIG_2_BAR1_SIZE_8M		 (8L<<0)
1157 #define BNX_PCI_CONFIG_2_BAR1_SIZE_16M		 (9L<<0)
1158 #define BNX_PCI_CONFIG_2_BAR1_SIZE_32M		 (10L<<0)
1159 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64M		 (11L<<0)
1160 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128M		 (12L<<0)
1161 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256M		 (13L<<0)
1162 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512M		 (14L<<0)
1163 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1G		 (15L<<0)
1164 #define BNX_PCI_CONFIG_2_BAR1_64ENA		 (1L<<4)
1165 #define BNX_PCI_CONFIG_2_EXP_ROM_RETRY		 (1L<<5)
1166 #define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY	 (1L<<6)
1167 #define BNX_PCI_CONFIG_2_FIRST_CFG_DONE		 (1L<<7)
1168 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE		 (0xffL<<8)
1169 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED	 (0L<<8)
1170 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K	 (1L<<8)
1171 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K	 (2L<<8)
1172 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K	 (3L<<8)
1173 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K	 (4L<<8)
1174 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K	 (5L<<8)
1175 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K	 (6L<<8)
1176 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K	 (7L<<8)
1177 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K	 (8L<<8)
1178 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K	 (9L<<8)
1179 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K	 (10L<<8)
1180 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M	 (11L<<8)
1181 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M	 (12L<<8)
1182 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M	 (13L<<8)
1183 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M	 (14L<<8)
1184 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M	 (15L<<8)
1185 #define BNX_PCI_CONFIG_2_MAX_SPLIT_LIMIT	 (0x1fL<<16)
1186 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT		 (0x3L<<21)
1187 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512	 (0L<<21)
1188 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K	 (1L<<21)
1189 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K	 (2L<<21)
1190 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K	 (3L<<21)
1191 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR	 (1L<<23)
1192 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT	 (1L<<24)
1193 #define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT	 (1L<<25)
1194 
1195 #define BNX_PCI_CONFIG_3			0x0000040c
1196 #define BNX_PCI_CONFIG_3_STICKY_BYTE		 (0xffL<<0)
1197 #define BNX_PCI_CONFIG_3_FORCE_PME		 (1L<<24)
1198 #define BNX_PCI_CONFIG_3_PME_STATUS		 (1L<<25)
1199 #define BNX_PCI_CONFIG_3_PME_ENABLE		 (1L<<26)
1200 #define BNX_PCI_CONFIG_3_PM_STATE		 (0x3L<<27)
1201 #define BNX_PCI_CONFIG_3_VAUX_PRESET		 (1L<<30)
1202 #define BNX_PCI_CONFIG_3_PCI_POWER		 (1L<<31)
1203 
1204 #define BNX_PCI_PM_DATA_A			0x00000410
1205 #define BNX_PCI_PM_DATA_A_PM_DATA_0_PRG		 (0xffL<<0)
1206 #define BNX_PCI_PM_DATA_A_PM_DATA_1_PRG		 (0xffL<<8)
1207 #define BNX_PCI_PM_DATA_A_PM_DATA_2_PRG		 (0xffL<<16)
1208 #define BNX_PCI_PM_DATA_A_PM_DATA_3_PRG		 (0xffL<<24)
1209 
1210 #define BNX_PCI_PM_DATA_B			0x00000414
1211 #define BNX_PCI_PM_DATA_B_PM_DATA_4_PRG		 (0xffL<<0)
1212 #define BNX_PCI_PM_DATA_B_PM_DATA_5_PRG		 (0xffL<<8)
1213 #define BNX_PCI_PM_DATA_B_PM_DATA_6_PRG		 (0xffL<<16)
1214 #define BNX_PCI_PM_DATA_B_PM_DATA_7_PRG		 (0xffL<<24)
1215 
1216 #define BNX_PCI_SWAP_DIAG0			0x00000418
1217 #define BNX_PCI_SWAP_DIAG1			0x0000041c
1218 #define BNX_PCI_EXP_ROM_ADDR			0x00000420
1219 #define BNX_PCI_EXP_ROM_ADDR_ADDRESS		 (0x3fffffL<<2)
1220 #define BNX_PCI_EXP_ROM_ADDR_REQ		 (1L<<31)
1221 
1222 #define BNX_PCI_EXP_ROM_DATA			0x00000424
1223 #define BNX_PCI_VPD_INTF			0x00000428
1224 #define BNX_PCI_VPD_INTF_INTF_REQ		 (1L<<0)
1225 
1226 #define BNX_PCI_VPD_ADDR_FLAG			0x0000042c
1227 #define BNX_PCI_VPD_ADDR_FLAG_ADDRESS		 (0x1fff<<2)
1228 #define BNX_PCI_VPD_ADDR_FLAG_WR		 (1<<15)
1229 
1230 #define BNX_PCI_VPD_DATA			0x00000430
1231 #define BNX_PCI_ID_VAL1				0x00000434
1232 #define BNX_PCI_ID_VAL1_DEVICE_ID		 (0xffffL<<0)
1233 #define BNX_PCI_ID_VAL1_VENDOR_ID		 (0xffffL<<16)
1234 
1235 #define BNX_PCI_ID_VAL2				0x00000438
1236 #define BNX_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID	 (0xffffL<<0)
1237 #define BNX_PCI_ID_VAL2_SUBSYSTEM_ID		 (0xffffL<<16)
1238 
1239 #define BNX_PCI_ID_VAL3				0x0000043c
1240 #define BNX_PCI_ID_VAL3_CLASS_CODE		 (0xffffffL<<0)
1241 #define BNX_PCI_ID_VAL3_REVISION_ID		 (0xffL<<24)
1242 
1243 #define BNX_PCI_ID_VAL4				0x00000440
1244 #define BNX_PCI_ID_VAL4_CAP_ENA			 (0xfL<<0)
1245 #define BNX_PCI_ID_VAL4_CAP_ENA_0		 (0L<<0)
1246 #define BNX_PCI_ID_VAL4_CAP_ENA_1		 (1L<<0)
1247 #define BNX_PCI_ID_VAL4_CAP_ENA_2		 (2L<<0)
1248 #define BNX_PCI_ID_VAL4_CAP_ENA_3		 (3L<<0)
1249 #define BNX_PCI_ID_VAL4_CAP_ENA_4		 (4L<<0)
1250 #define BNX_PCI_ID_VAL4_CAP_ENA_5		 (5L<<0)
1251 #define BNX_PCI_ID_VAL4_CAP_ENA_6		 (6L<<0)
1252 #define BNX_PCI_ID_VAL4_CAP_ENA_7		 (7L<<0)
1253 #define BNX_PCI_ID_VAL4_CAP_ENA_8		 (8L<<0)
1254 #define BNX_PCI_ID_VAL4_CAP_ENA_9		 (9L<<0)
1255 #define BNX_PCI_ID_VAL4_CAP_ENA_10		 (10L<<0)
1256 #define BNX_PCI_ID_VAL4_CAP_ENA_11		 (11L<<0)
1257 #define BNX_PCI_ID_VAL4_CAP_ENA_12		 (12L<<0)
1258 #define BNX_PCI_ID_VAL4_CAP_ENA_13		 (13L<<0)
1259 #define BNX_PCI_ID_VAL4_CAP_ENA_14		 (14L<<0)
1260 #define BNX_PCI_ID_VAL4_CAP_ENA_15		 (15L<<0)
1261 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG		 (0x3L<<6)
1262 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0		 (0L<<6)
1263 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1		 (1L<<6)
1264 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2		 (2L<<6)
1265 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3		 (3L<<6)
1266 #define BNX_PCI_ID_VAL4_MSI_LIMIT		 (0x7L<<9)
1267 #define BNX_PCI_ID_VAL4_MSI_ADVERTIZE		 (0x7L<<12)
1268 #define BNX_PCI_ID_VAL4_MSI_ENABLE		 (1L<<15)
1269 #define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE	 (1L<<16)
1270 #define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE	 (1L<<17)
1271 #define BNX_PCI_ID_VAL4_MAX_MEM_READ_SIZE	 (0x3L<<21)
1272 #define BNX_PCI_ID_VAL4_MAX_SPLIT_SIZE		 (0x7L<<23)
1273 #define BNX_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE	 (0x7L<<26)
1274 
1275 #define BNX_PCI_ID_VAL5				0x00000444
1276 #define BNX_PCI_ID_VAL5_D1_SUPPORT		 (1L<<0)
1277 #define BNX_PCI_ID_VAL5_D2_SUPPORT		 (1L<<1)
1278 #define BNX_PCI_ID_VAL5_PME_IN_D0		 (1L<<2)
1279 #define BNX_PCI_ID_VAL5_PME_IN_D1		 (1L<<3)
1280 #define BNX_PCI_ID_VAL5_PME_IN_D2		 (1L<<4)
1281 #define BNX_PCI_ID_VAL5_PME_IN_D3_HOT		 (1L<<5)
1282 
1283 #define BNX_PCI_PCIX_EXTENDED_STATUS			0x00000448
1284 #define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP		 (1L<<8)
1285 #define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST		 (1L<<9)
1286 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS	 (0xfL<<16)
1287 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX	 (0xffL<<24)
1288 
1289 #define BNX_PCI_ID_VAL6				0x0000044c
1290 #define BNX_PCI_ID_VAL6_MAX_LAT			 (0xffL<<0)
1291 #define BNX_PCI_ID_VAL6_MIN_GNT			 (0xffL<<8)
1292 #define BNX_PCI_ID_VAL6_BIST			 (0xffL<<16)
1293 
1294 #define BNX_PCI_MSI_DATA			0x00000450
1295 #define BNX_PCI_MSI_DATA_PCI_MSI_DATA		 (0xffffL<<0)
1296 
1297 #define BNX_PCI_MSI_ADDR_H			0x00000454
1298 #define BNX_PCI_MSI_ADDR_L			0x00000458
1299 
1300 /*
1301  *  misc_reg definition
1302  *  offset: 0x800
1303  */
1304 #define BNX_MISC_COMMAND			0x00000800
1305 #define BNX_MISC_COMMAND_ENABLE_ALL		 (1L<<0)
1306 #define BNX_MISC_COMMAND_DISABLE_ALL		 (1L<<1)
1307 #define BNX_MISC_COMMAND_SW_RESET		 (1L<<4)
1308 #define BNX_MISC_COMMAND_POR_RESET		 (1L<<5)
1309 #define BNX_MISC_COMMAND_HD_RESET		 (1L<<6)
1310 #define BNX_MISC_COMMAND_CMN_SW_RESET		 (1L<<7)
1311 #define BNX_MISC_COMMAND_PAR_ERROR		 (1L<<8)
1312 #define BNX_MISC_COMMAND_CS16_ERR		 (1L<<9)
1313 #define BNX_MISC_COMMAND_CS16_ERR_LOC		 (0xfL<<12)
1314 #define BNX_MISC_COMMAND_PAR_ERR_RAM		 (0x7fL<<16)
1315 #define BNX_MISC_COMMAND_POWERDOWN_EVENT	 (1L<<23)
1316 #define BNX_MISC_COMMAND_SW_SHUTDOWN		 (1L<<24)
1317 #define BNX_MISC_COMMAND_SHUTDOWN_EN		 (1L<<25)
1318 #define BNX_MISC_COMMAND_DINTEG_ATTN_EN		 (1L<<26)
1319 #define BNX_MISC_COMMAND_PCIE_LINK_IN_L23	 (1L<<27)
1320 #define BNX_MISC_COMMAND_PCIE_DIS		 (1L<<28)
1321 
1322 #define BNX_MISC_CFG				0x00000804
1323 #define BNX_MISC_CFG_PCI_GRC_TMOUT		 (1L<<0)
1324 #define BNX_MISC_CFG_NVM_WR_EN			 (0x3L<<1)
1325 #define BNX_MISC_CFG_NVM_WR_EN_PROTECT		 (0L<<1)
1326 #define BNX_MISC_CFG_NVM_WR_EN_PCI		 (1L<<1)
1327 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW		 (2L<<1)
1328 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW2		 (3L<<1)
1329 #define BNX_MISC_CFG_BIST_EN			 (1L<<3)
1330 #define BNX_MISC_CFG_CK25_OUT_ALT_SRC		 (1L<<4)
1331 #define BNX_MISC_CFG_BYPASS_BSCAN		 (1L<<5)
1332 #define BNX_MISC_CFG_BYPASS_EJTAG		 (1L<<6)
1333 #define BNX_MISC_CFG_CLK_CTL_OVERRIDE		 (1L<<7)
1334 #define BNX_MISC_CFG_LEDMODE			 (0x3L<<8)
1335 #define BNX_MISC_CFG_LEDMODE_MAC		 (0L<<8)
1336 #define BNX_MISC_CFG_LEDMODE_GPHY1		 (1L<<8)
1337 #define BNX_MISC_CFG_LEDMODE_GPHY2		 (2L<<8)
1338 
1339 #define BNX_MISC_ID				0x00000808
1340 #define BNX_MISC_ID_BOND_ID			 (0xfL<<0)
1341 #define BNX_MISC_ID_CHIP_METAL			 (0xffL<<4)
1342 #define BNX_MISC_ID_CHIP_REV			 (0xfL<<12)
1343 #define BNX_MISC_ID_CHIP_NUM			 (0xffffL<<16)
1344 
1345 #define BNX_MISC_ENABLE_STATUS_BITS			0x0000080c
1346 #define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1347 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1348 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1349 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1350 #define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE	 (1L<<4)
1351 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1352 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1353 #define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1354 #define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1355 #define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE		 (1L<<9)
1356 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1357 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1358 #define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE	 (1L<<12)
1359 #define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1360 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1361 #define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE	 (1L<<15)
1362 #define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1363 #define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE	 (1L<<17)
1364 #define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE	 (1L<<18)
1365 #define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1366 #define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1367 #define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE	 (1L<<21)
1368 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1369 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1370 #define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1371 #define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE	 (1L<<25)
1372 #define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1373 #define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE		 (1L<<27)
1374 
1375 #define BNX_MISC_ENABLE_SET_BITS			0x00000810
1376 #define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1377 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1378 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1379 #define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1380 #define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE		 (1L<<4)
1381 #define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1382 #define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1383 #define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1384 #define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1385 #define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE		 (1L<<9)
1386 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1387 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1388 #define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE		 (1L<<12)
1389 #define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1390 #define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1391 #define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE		 (1L<<15)
1392 #define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1393 #define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE		 (1L<<17)
1394 #define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE	 (1L<<18)
1395 #define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1396 #define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1397 #define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE		 (1L<<21)
1398 #define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1399 #define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1400 #define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1401 #define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE		 (1L<<25)
1402 #define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1403 #define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE		 (1L<<27)
1404 
1405 #define BNX_MISC_ENABLE_DEFAULT				0x05ffffff
1406 #define BNX_MISC_ENABLE_DEFAULT_XI			0x17ffffff
1407 
1408 #define BNX_MISC_ENABLE_CLR_BITS			0x00000814
1409 #define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1410 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1411 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1412 #define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1413 #define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE		 (1L<<4)
1414 #define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1415 #define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1416 #define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1417 #define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1418 #define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE		 (1L<<9)
1419 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1420 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1421 #define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE		 (1L<<12)
1422 #define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1423 #define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1424 #define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE		 (1L<<15)
1425 #define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1426 #define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE		 (1L<<17)
1427 #define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE	 (1L<<18)
1428 #define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1429 #define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1430 #define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE		 (1L<<21)
1431 #define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1432 #define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1433 #define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1434 #define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE		 (1L<<25)
1435 #define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1436 #define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE		 (1L<<27)
1437 
1438 #define BNX_MISC_CLOCK_CONTROL_BITS				0x00000818
1439 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET		 (0xfL<<0)
1440 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1441 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1442 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1443 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1444 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1445 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1446 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1447 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1448 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW		 (0xfL<<0)
1449 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE		 (1L<<6)
1450 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT		 (1L<<7)
1451 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC		 (0x7L<<8)
1452 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1453 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12		 (1L<<8)
1454 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6		 (2L<<8)
1455 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62		 (4L<<8)
1456 #define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD			 (1L<<11)
1457 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED		 (0xfL<<12)
1458 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1459 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1460 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1461 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1462 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1463 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP		 (1L<<16)
1464 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP		 (1L<<17)
1465 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18			 (1L<<18)
1466 #define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET			 (1L<<19)
1467 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED			 (0xfffL<<20)
1468 
1469 #define BNX_MISC_GPIO					0x0000081c
1470 #define BNX_MISC_GPIO_VALUE				 (0xffL<<0)
1471 #define BNX_MISC_GPIO_SET				 (0xffL<<8)
1472 #define BNX_MISC_GPIO_CLR				 (0xffL<<16)
1473 #define BNX_MISC_GPIO_FLOAT				 (0xffL<<24)
1474 
1475 #define BNX_MISC_GPIO_INT				0x00000820
1476 #define BNX_MISC_GPIO_INT_INT_STATE			 (0xfL<<0)
1477 #define BNX_MISC_GPIO_INT_OLD_VALUE			 (0xfL<<8)
1478 #define BNX_MISC_GPIO_INT_OLD_SET			 (0xfL<<16)
1479 #define BNX_MISC_GPIO_INT_OLD_CLR			 (0xfL<<24)
1480 
1481 #define BNX_MISC_CONFIG_LFSR				0x00000824
1482 #define BNX_MISC_CONFIG_LFSR_DIV			 (0xffffL<<0)
1483 
1484 #define BNX_MISC_LFSR_MASK_BITS				0x00000828
1485 #define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1486 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1487 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1488 #define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1489 #define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE		 (1L<<4)
1490 #define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1491 #define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1492 #define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1493 #define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1494 #define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE		 (1L<<9)
1495 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1496 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1497 #define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE		 (1L<<12)
1498 #define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1499 #define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1500 #define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE		 (1L<<15)
1501 #define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1502 #define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE		 (1L<<17)
1503 #define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE	 (1L<<18)
1504 #define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1505 #define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1506 #define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE		 (1L<<21)
1507 #define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1508 #define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1509 #define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1510 #define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE		 (1L<<25)
1511 #define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1512 #define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE		 (1L<<27)
1513 
1514 #define BNX_MISC_ARB_REQ0			0x0000082c
1515 #define BNX_MISC_ARB_REQ1			0x00000830
1516 #define BNX_MISC_ARB_REQ2			0x00000834
1517 #define BNX_MISC_ARB_REQ3			0x00000838
1518 #define BNX_MISC_ARB_REQ4			0x0000083c
1519 #define BNX_MISC_ARB_FREE0			0x00000840
1520 #define BNX_MISC_ARB_FREE1			0x00000844
1521 #define BNX_MISC_ARB_FREE2			0x00000848
1522 #define BNX_MISC_ARB_FREE3			0x0000084c
1523 #define BNX_MISC_ARB_FREE4			0x00000850
1524 #define BNX_MISC_ARB_REQ_STATUS0		0x00000854
1525 #define BNX_MISC_ARB_REQ_STATUS1		0x00000858
1526 #define BNX_MISC_ARB_REQ_STATUS2		0x0000085c
1527 #define BNX_MISC_ARB_REQ_STATUS3		0x00000860
1528 #define BNX_MISC_ARB_REQ_STATUS4		0x00000864
1529 #define BNX_MISC_ARB_GNT0			0x00000868
1530 #define BNX_MISC_ARB_GNT0_0			 (0x7L<<0)
1531 #define BNX_MISC_ARB_GNT0_1			 (0x7L<<4)
1532 #define BNX_MISC_ARB_GNT0_2			 (0x7L<<8)
1533 #define BNX_MISC_ARB_GNT0_3			 (0x7L<<12)
1534 #define BNX_MISC_ARB_GNT0_4			 (0x7L<<16)
1535 #define BNX_MISC_ARB_GNT0_5			 (0x7L<<20)
1536 #define BNX_MISC_ARB_GNT0_6			 (0x7L<<24)
1537 #define BNX_MISC_ARB_GNT0_7			 (0x7L<<28)
1538 
1539 #define BNX_MISC_ARB_GNT1			0x0000086c
1540 #define BNX_MISC_ARB_GNT1_8			 (0x7L<<0)
1541 #define BNX_MISC_ARB_GNT1_9			 (0x7L<<4)
1542 #define BNX_MISC_ARB_GNT1_10			 (0x7L<<8)
1543 #define BNX_MISC_ARB_GNT1_11			 (0x7L<<12)
1544 #define BNX_MISC_ARB_GNT1_12			 (0x7L<<16)
1545 #define BNX_MISC_ARB_GNT1_13			 (0x7L<<20)
1546 #define BNX_MISC_ARB_GNT1_14			 (0x7L<<24)
1547 #define BNX_MISC_ARB_GNT1_15			 (0x7L<<28)
1548 
1549 #define BNX_MISC_ARB_GNT2			0x00000870
1550 #define BNX_MISC_ARB_GNT2_16			 (0x7L<<0)
1551 #define BNX_MISC_ARB_GNT2_17			 (0x7L<<4)
1552 #define BNX_MISC_ARB_GNT2_18			 (0x7L<<8)
1553 #define BNX_MISC_ARB_GNT2_19			 (0x7L<<12)
1554 #define BNX_MISC_ARB_GNT2_20			 (0x7L<<16)
1555 #define BNX_MISC_ARB_GNT2_21			 (0x7L<<20)
1556 #define BNX_MISC_ARB_GNT2_22			 (0x7L<<24)
1557 #define BNX_MISC_ARB_GNT2_23			 (0x7L<<28)
1558 
1559 #define BNX_MISC_ARB_GNT3			0x00000874
1560 #define BNX_MISC_ARB_GNT3_24			 (0x7L<<0)
1561 #define BNX_MISC_ARB_GNT3_25			 (0x7L<<4)
1562 #define BNX_MISC_ARB_GNT3_26			 (0x7L<<8)
1563 #define BNX_MISC_ARB_GNT3_27			 (0x7L<<12)
1564 #define BNX_MISC_ARB_GNT3_28			 (0x7L<<16)
1565 #define BNX_MISC_ARB_GNT3_29			 (0x7L<<20)
1566 #define BNX_MISC_ARB_GNT3_30			 (0x7L<<24)
1567 #define BNX_MISC_ARB_GNT3_31			 (0x7L<<28)
1568 
1569 #define BNX_MISC_PRBS_CONTROL			0x00000878
1570 #define BNX_MISC_PRBS_CONTROL_EN		 (1L<<0)
1571 #define BNX_MISC_PRBS_CONTROL_RSTB		 (1L<<1)
1572 #define BNX_MISC_PRBS_CONTROL_INV		 (1L<<2)
1573 #define BNX_MISC_PRBS_CONTROL_ERR_CLR		 (1L<<3)
1574 #define BNX_MISC_PRBS_CONTROL_ORDER		 (0x3L<<4)
1575 #define BNX_MISC_PRBS_CONTROL_ORDER_7TH		 (0L<<4)
1576 #define BNX_MISC_PRBS_CONTROL_ORDER_15TH	 (1L<<4)
1577 #define BNX_MISC_PRBS_CONTROL_ORDER_23RD	 (2L<<4)
1578 #define BNX_MISC_PRBS_CONTROL_ORDER_31ST	 (3L<<4)
1579 
1580 #define BNX_MISC_PRBS_STATUS			0x0000087c
1581 #define BNX_MISC_PRBS_STATUS_LOCK		 (1L<<0)
1582 #define BNX_MISC_PRBS_STATUS_STKY		 (1L<<1)
1583 #define BNX_MISC_PRBS_STATUS_ERRORS		 (0x3fffL<<2)
1584 #define BNX_MISC_PRBS_STATUS_STATE		 (0xfL<<16)
1585 
1586 #define BNX_MISC_SM_ASF_CONTROL				0x00000880
1587 #define BNX_MISC_SM_ASF_CONTROL_ASF_RST			 (1L<<0)
1588 #define BNX_MISC_SM_ASF_CONTROL_TSC_EN			 (1L<<1)
1589 #define BNX_MISC_SM_ASF_CONTROL_WG_TO			 (1L<<2)
1590 #define BNX_MISC_SM_ASF_CONTROL_HB_TO			 (1L<<3)
1591 #define BNX_MISC_SM_ASF_CONTROL_PA_TO			 (1L<<4)
1592 #define BNX_MISC_SM_ASF_CONTROL_PL_TO			 (1L<<5)
1593 #define BNX_MISC_SM_ASF_CONTROL_RT_TO			 (1L<<6)
1594 #define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT		 (1L<<7)
1595 #define BNX_MISC_SM_ASF_CONTROL_RES			 (0xfL<<8)
1596 #define BNX_MISC_SM_ASF_CONTROL_SMB_EN			 (1L<<12)
1597 #define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN		 (1L<<13)
1598 #define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT	 (1L<<14)
1599 #define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD		 (1L<<15)
1600 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1		 (0x3fL<<16)
1601 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2		 (0x3fL<<24)
1602 #define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0	 (1L<<30)
1603 #define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN		 (1L<<31)
1604 
1605 #define BNX_MISC_SMB_IN				0x00000884
1606 #define BNX_MISC_SMB_IN_DAT_IN			 (0xffL<<0)
1607 #define BNX_MISC_SMB_IN_RDY			 (1L<<8)
1608 #define BNX_MISC_SMB_IN_DONE			 (1L<<9)
1609 #define BNX_MISC_SMB_IN_FIRSTBYTE		 (1L<<10)
1610 #define BNX_MISC_SMB_IN_STATUS			 (0x7L<<11)
1611 #define BNX_MISC_SMB_IN_STATUS_OK		 (0x0L<<11)
1612 #define BNX_MISC_SMB_IN_STATUS_PEC		 (0x1L<<11)
1613 #define BNX_MISC_SMB_IN_STATUS_OFLOW		 (0x2L<<11)
1614 #define BNX_MISC_SMB_IN_STATUS_STOP		 (0x3L<<11)
1615 #define BNX_MISC_SMB_IN_STATUS_TIMEOUT		 (0x4L<<11)
1616 
1617 #define BNX_MISC_SMB_OUT				0x00000888
1618 #define BNX_MISC_SMB_OUT_DAT_OUT			 (0xffL<<0)
1619 #define BNX_MISC_SMB_OUT_RDY				 (1L<<8)
1620 #define BNX_MISC_SMB_OUT_START				 (1L<<9)
1621 #define BNX_MISC_SMB_OUT_LAST				 (1L<<10)
1622 #define BNX_MISC_SMB_OUT_ACC_TYPE			 (1L<<11)
1623 #define BNX_MISC_SMB_OUT_ENB_PEC			 (1L<<12)
1624 #define BNX_MISC_SMB_OUT_GET_RX_LEN			 (1L<<13)
1625 #define BNX_MISC_SMB_OUT_SMB_READ_LEN			 (0x3fL<<14)
1626 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS			 (0xfL<<20)
1627 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK		 (0L<<20)
1628 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK	 (1L<<20)
1629 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW		 (2L<<20)
1630 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP		 (3L<<20)
1631 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT		 (4L<<20)
1632 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST	 (5L<<20)
1633 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK		 (6L<<20)
1634 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK	 (9L<<20)
1635 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST	 (0xdL<<20)
1636 #define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE		 (1L<<24)
1637 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN			 (1L<<25)
1638 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN			 (1L<<26)
1639 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN			 (1L<<27)
1640 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN			 (1L<<28)
1641 
1642 #define BNX_MISC_SMB_WATCHDOG			0x0000088c
1643 #define BNX_MISC_SMB_WATCHDOG_WATCHDOG		 (0xffffL<<0)
1644 
1645 #define BNX_MISC_SMB_HEARTBEAT			0x00000890
1646 #define BNX_MISC_SMB_HEARTBEAT_HEARTBEAT	 (0xffffL<<0)
1647 
1648 #define BNX_MISC_SMB_POLL_ASF			0x00000894
1649 #define BNX_MISC_SMB_POLL_ASF_POLL_ASF		 (0xffffL<<0)
1650 
1651 #define BNX_MISC_SMB_POLL_LEGACY		0x00000898
1652 #define BNX_MISC_SMB_POLL_LEGACY_POLL_LEGACY	 (0xffffL<<0)
1653 
1654 #define BNX_MISC_SMB_RETRAN			0x0000089c
1655 #define BNX_MISC_SMB_RETRAN_RETRAN		 (0xffL<<0)
1656 
1657 #define BNX_MISC_SMB_TIMESTAMP			0x000008a0
1658 #define BNX_MISC_SMB_TIMESTAMP_TIMESTAMP	 (0xffffffffL<<0)
1659 
1660 #define BNX_MISC_PERR_ENA0			0x000008a4
1661 #define BNX_MISC_PERR_ENA0_COM_MISC_CTXC	 (1L<<0)
1662 #define BNX_MISC_PERR_ENA0_COM_MISC_REGF	 (1L<<1)
1663 #define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD	 (1L<<2)
1664 #define BNX_MISC_PERR_ENA0_CP_MISC_CTXC		 (1L<<3)
1665 #define BNX_MISC_PERR_ENA0_CP_MISC_REGF		 (1L<<4)
1666 #define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD	 (1L<<5)
1667 #define BNX_MISC_PERR_ENA0_CS_MISC_TMEM		 (1L<<6)
1668 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0	 (1L<<7)
1669 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1	 (1L<<8)
1670 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2	 (1L<<9)
1671 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3	 (1L<<10)
1672 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4	 (1L<<11)
1673 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5	 (1L<<12)
1674 #define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL	 (1L<<13)
1675 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0	 (1L<<14)
1676 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1	 (1L<<15)
1677 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2	 (1L<<16)
1678 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3	 (1L<<17)
1679 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4	 (1L<<18)
1680 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0	 (1L<<19)
1681 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1	 (1L<<20)
1682 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2	 (1L<<21)
1683 #define BNX_MISC_PERR_ENA0_HC_MISC_DMA		 (1L<<22)
1684 #define BNX_MISC_PERR_ENA0_MCP_MISC_REGF	 (1L<<23)
1685 #define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD	 (1L<<24)
1686 #define BNX_MISC_PERR_ENA0_MQ_MISC_CTX		 (1L<<25)
1687 #define BNX_MISC_PERR_ENA0_RBDC_MISC		 (1L<<26)
1688 #define BNX_MISC_PERR_ENA0_RBUF_MISC_MB		 (1L<<27)
1689 #define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR	 (1L<<28)
1690 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPC		 (1L<<29)
1691 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPM		 (1L<<30)
1692 #define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS	 (1L<<31)
1693 
1694 #define BNX_MISC_PERR_ENA1			0x000008a8
1695 #define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS	 (1L<<0)
1696 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM	 (1L<<1)
1697 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM	 (1L<<2)
1698 #define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC	 (1L<<3)
1699 #define BNX_MISC_PERR_ENA1_RXP_MISC_REGF	 (1L<<4)
1700 #define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD	 (1L<<5)
1701 #define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC	 (1L<<6)
1702 #define BNX_MISC_PERR_ENA1_TBDC_MISC		 (1L<<7)
1703 #define BNX_MISC_PERR_ENA1_TDMA_MISC		 (1L<<8)
1704 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0	 (1L<<9)
1705 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1	 (1L<<10)
1706 #define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF	 (1L<<11)
1707 #define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD	 (1L<<12)
1708 #define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB	 (1L<<13)
1709 #define BNX_MISC_PERR_ENA1_TSCH_MISC_LR		 (1L<<14)
1710 #define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC	 (1L<<15)
1711 #define BNX_MISC_PERR_ENA1_TXP_MISC_REGF	 (1L<<16)
1712 #define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD	 (1L<<17)
1713 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX	 (1L<<18)
1714 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX	 (1L<<19)
1715 #define BNX_MISC_PERR_ENA1_UMP_MISC_RX		 (1L<<20)
1716 #define BNX_MISC_PERR_ENA1_UMP_MISC_TX		 (1L<<21)
1717 #define BNX_MISC_PERR_ENA1_RDMAQ_MISC		 (1L<<22)
1718 #define BNX_MISC_PERR_ENA1_CSQ_MISC		 (1L<<23)
1719 #define BNX_MISC_PERR_ENA1_CPQ_MISC		 (1L<<24)
1720 #define BNX_MISC_PERR_ENA1_MCPQ_MISC		 (1L<<25)
1721 #define BNX_MISC_PERR_ENA1_RV2PMQ_MISC		 (1L<<26)
1722 #define BNX_MISC_PERR_ENA1_RV2PPQ_MISC		 (1L<<27)
1723 #define BNX_MISC_PERR_ENA1_RV2PTQ_MISC		 (1L<<28)
1724 #define BNX_MISC_PERR_ENA1_RXPQ_MISC		 (1L<<29)
1725 #define BNX_MISC_PERR_ENA1_RXPCQ_MISC		 (1L<<30)
1726 #define BNX_MISC_PERR_ENA1_RLUPQ_MISC		 (1L<<31)
1727 
1728 #define BNX_MISC_PERR_ENA2			0x000008ac
1729 #define BNX_MISC_PERR_ENA2_COMQ_MISC		 (1L<<0)
1730 #define BNX_MISC_PERR_ENA2_COMXQ_MISC		 (1L<<1)
1731 #define BNX_MISC_PERR_ENA2_COMTQ_MISC		 (1L<<2)
1732 #define BNX_MISC_PERR_ENA2_TSCHQ_MISC		 (1L<<3)
1733 #define BNX_MISC_PERR_ENA2_TBDRQ_MISC		 (1L<<4)
1734 #define BNX_MISC_PERR_ENA2_TXPQ_MISC		 (1L<<5)
1735 #define BNX_MISC_PERR_ENA2_TDMAQ_MISC		 (1L<<6)
1736 #define BNX_MISC_PERR_ENA2_TPATQ_MISC		 (1L<<7)
1737 #define BNX_MISC_PERR_ENA2_TASQ_MISC		 (1L<<8)
1738 
1739 #define BNX_MISC_DEBUG_VECTOR_SEL		0x000008b0
1740 #define BNX_MISC_DEBUG_VECTOR_SEL_0		 (0xfffL<<0)
1741 #define BNX_MISC_DEBUG_VECTOR_SEL_1		 (0xfffL<<12)
1742 
1743 #define BNX_MISC_VREG_CONTROL			0x000008b4
1744 #define BNX_MISC_VREG_CONTROL_1_2		 (0xfL<<0)
1745 #define BNX_MISC_VREG_CONTROL_2_5		 (0xfL<<4)
1746 
1747 #define BNX_MISC_FINAL_CLK_CTL_VAL			0x000008b8
1748 #define BNX_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1749 
1750 #define BNX_MISC_UNUSED0			0x000008bc
1751 
1752 #define BNX_MISC_NEW_CORE_CTL				0x000008c8
1753 #define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS	 (1L<<0)
1754 #define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ		 (1L<<1)
1755 #define BNX_MISC_NEW_CORE_CTL_DMA_ENABLE		 (1L<<16)
1756 #define BNX_MISC_NEW_CORE_CTL_RESERVED_CMN		 (0x3fffL<<2)
1757 #define BNX_MISC_NEW_CORE_CTL_RESERVED_TC		 (0xffffL<<16)
1758 
1759 #define BNX_MISC_DUAL_MEDIA_CTRL			0x000008ec
1760 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID		 (0xffL<<0)
1761 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_X		 (0L<<0)
1762 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C		 (3L<<0)
1763 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S		 (12L<<0)
1764 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP		 (0x7L<<8)
1765 #define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN		 (1L<<11)
1766 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET		 (1L<<12)
1767 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET		 (1L<<13)
1768 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET		 (1L<<14)
1769 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET		 (1L<<15)
1770 #define BNX_MISC_DUAL_MEDIA_CTRL_LCPLL_RST		 (1L<<16)
1771 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_RST		 (1L<<17)
1772 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_RST		 (1L<<18)
1773 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_RST		 (1L<<19)
1774 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_RST		 (1L<<20)
1775 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL		 (0x7L<<21)
1776 #define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP		 (1L<<24)
1777 #define BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE		 (1L<<25)
1778 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ	 (0xfL<<26)
1779 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ	 (1L<<26)
1780 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ	 (2L<<26)
1781 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ	 (4L<<26)
1782 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ	 (8L<<26)
1783 
1784 
1785 /*
1786  *  nvm_reg definition
1787  *  offset: 0x6400
1788  */
1789 #define BNX_NVM_COMMAND				0x00006400
1790 #define BNX_NVM_COMMAND_RST			 (1L<<0)
1791 #define BNX_NVM_COMMAND_DONE			 (1L<<3)
1792 #define BNX_NVM_COMMAND_DOIT			 (1L<<4)
1793 #define BNX_NVM_COMMAND_WR			 (1L<<5)
1794 #define BNX_NVM_COMMAND_ERASE			 (1L<<6)
1795 #define BNX_NVM_COMMAND_FIRST			 (1L<<7)
1796 #define BNX_NVM_COMMAND_LAST			 (1L<<8)
1797 #define BNX_NVM_COMMAND_WREN			 (1L<<16)
1798 #define BNX_NVM_COMMAND_WRDI			 (1L<<17)
1799 #define BNX_NVM_COMMAND_EWSR			 (1L<<18)
1800 #define BNX_NVM_COMMAND_WRSR			 (1L<<19)
1801 
1802 #define BNX_NVM_STATUS				0x00006404
1803 #define BNX_NVM_STATUS_PI_FSM_STATE		 (0xfL<<0)
1804 #define BNX_NVM_STATUS_EE_FSM_STATE		 (0xfL<<4)
1805 #define BNX_NVM_STATUS_EQ_FSM_STATE		 (0xfL<<8)
1806 
1807 #define BNX_NVM_WRITE				0x00006408
1808 #define BNX_NVM_WRITE_NVM_WRITE_VALUE		 (0xffffffffL<<0)
1809 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG	 (0L<<0)
1810 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK	 (1L<<0)
1811 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA	 (2L<<0)
1812 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK	 (4L<<0)
1813 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B	 (8L<<0)
1814 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO	 (16L<<0)
1815 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI	 (32L<<0)
1816 
1817 #define BNX_NVM_ADDR				0x0000640c
1818 #define BNX_NVM_ADDR_NVM_ADDR_VALUE		 (0xffffffL<<0)
1819 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG	 (0L<<0)
1820 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK	 (1L<<0)
1821 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA	 (2L<<0)
1822 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK	 (4L<<0)
1823 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B	 (8L<<0)
1824 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO		 (16L<<0)
1825 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI		 (32L<<0)
1826 
1827 #define BNX_NVM_READ				0x00006410
1828 #define BNX_NVM_READ_NVM_READ_VALUE		 (0xffffffffL<<0)
1829 #define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG	 (0L<<0)
1830 #define BNX_NVM_READ_NVM_READ_VALUE_EECLK	 (1L<<0)
1831 #define BNX_NVM_READ_NVM_READ_VALUE_EEDATA	 (2L<<0)
1832 #define BNX_NVM_READ_NVM_READ_VALUE_SCLK	 (4L<<0)
1833 #define BNX_NVM_READ_NVM_READ_VALUE_CS_B	 (8L<<0)
1834 #define BNX_NVM_READ_NVM_READ_VALUE_SO		 (16L<<0)
1835 #define BNX_NVM_READ_NVM_READ_VALUE_SI		 (32L<<0)
1836 
1837 #define BNX_NVM_CFG1				0x00006414
1838 #define BNX_NVM_CFG1_FLASH_MODE			 (1L<<0)
1839 #define BNX_NVM_CFG1_BUFFER_MODE		 (1L<<1)
1840 #define BNX_NVM_CFG1_PASS_MODE			 (1L<<2)
1841 #define BNX_NVM_CFG1_BITBANG_MODE		 (1L<<3)
1842 #define BNX_NVM_CFG1_STATUS_BIT			 (0x7L<<4)
1843 #define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY	 (0L<<4)
1844 #define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY	 (7L<<4)
1845 #define BNX_NVM_CFG1_SPI_CLK_DIV		 (0xfL<<7)
1846 #define BNX_NVM_CFG1_SEE_CLK_DIV		 (0x7ffL<<11)
1847 #define BNX_NVM_CFG1_PROTECT_MODE		 (1L<<24)
1848 #define BNX_NVM_CFG1_FLASH_SIZE			 (1L<<25)
1849 #define BNX_NVM_CFG1_COMPAT_BYPASSS		 (1L<<31)
1850 
1851 #define BNX_NVM_CFG2				0x00006418
1852 #define BNX_NVM_CFG2_ERASE_CMD			 (0xffL<<0)
1853 #define BNX_NVM_CFG2_DUMMY			 (0xffL<<8)
1854 #define BNX_NVM_CFG2_STATUS_CMD			 (0xffL<<16)
1855 
1856 #define BNX_NVM_CFG3				0x0000641c
1857 #define BNX_NVM_CFG3_BUFFER_RD_CMD		 (0xffL<<0)
1858 #define BNX_NVM_CFG3_WRITE_CMD			 (0xffL<<8)
1859 #define BNX_NVM_CFG3_BUFFER_WRITE_CMD		 (0xffL<<16)
1860 #define BNX_NVM_CFG3_READ_CMD			 (0xffL<<24)
1861 
1862 #define BNX_NVM_SW_ARB				0x00006420
1863 #define BNX_NVM_SW_ARB_ARB_REQ_SET0		 (1L<<0)
1864 #define BNX_NVM_SW_ARB_ARB_REQ_SET1		 (1L<<1)
1865 #define BNX_NVM_SW_ARB_ARB_REQ_SET2		 (1L<<2)
1866 #define BNX_NVM_SW_ARB_ARB_REQ_SET3		 (1L<<3)
1867 #define BNX_NVM_SW_ARB_ARB_REQ_CLR0		 (1L<<4)
1868 #define BNX_NVM_SW_ARB_ARB_REQ_CLR1		 (1L<<5)
1869 #define BNX_NVM_SW_ARB_ARB_REQ_CLR2		 (1L<<6)
1870 #define BNX_NVM_SW_ARB_ARB_REQ_CLR3		 (1L<<7)
1871 #define BNX_NVM_SW_ARB_ARB_ARB0			 (1L<<8)
1872 #define BNX_NVM_SW_ARB_ARB_ARB1			 (1L<<9)
1873 #define BNX_NVM_SW_ARB_ARB_ARB2			 (1L<<10)
1874 #define BNX_NVM_SW_ARB_ARB_ARB3			 (1L<<11)
1875 #define BNX_NVM_SW_ARB_REQ0			 (1L<<12)
1876 #define BNX_NVM_SW_ARB_REQ1			 (1L<<13)
1877 #define BNX_NVM_SW_ARB_REQ2			 (1L<<14)
1878 #define BNX_NVM_SW_ARB_REQ3			 (1L<<15)
1879 
1880 #define BNX_NVM_ACCESS_ENABLE			0x00006424
1881 #define BNX_NVM_ACCESS_ENABLE_EN		 (1L<<0)
1882 #define BNX_NVM_ACCESS_ENABLE_WR_EN		 (1L<<1)
1883 
1884 #define BNX_NVM_WRITE1				0x00006428
1885 #define BNX_NVM_WRITE1_WREN_CMD			 (0xffL<<0)
1886 #define BNX_NVM_WRITE1_WRDI_CMD			 (0xffL<<8)
1887 #define BNX_NVM_WRITE1_SR_DATA			 (0xffL<<16)
1888 
1889 
1890 /*
1891  *  dma_reg definition
1892  *  offset: 0xc00
1893  */
1894 #define BNX_DMA_COMMAND				0x00000c00
1895 #define BNX_DMA_COMMAND_ENABLE			 (1L<<0)
1896 
1897 #define BNX_DMA_STATUS					0x00000c04
1898 #define BNX_DMA_STATUS_PAR_ERROR_STATE			 (1L<<0)
1899 #define BNX_DMA_STATUS_READ_TRANSFERS_STAT		 (1L<<16)
1900 #define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT		 (1L<<17)
1901 #define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT		 (1L<<18)
1902 #define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT	 (1L<<19)
1903 #define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT	 (1L<<20)
1904 #define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT		 (1L<<21)
1905 #define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<22)
1906 #define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT		 (1L<<23)
1907 #define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<24)
1908 #define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT	 (1L<<25)
1909 
1910 #define BNX_DMA_CONFIG				0x00000c08
1911 #define BNX_DMA_CONFIG_DATA_BYTE_SWAP		 (1L<<0)
1912 #define BNX_DMA_CONFIG_DATA_WORD_SWAP		 (1L<<1)
1913 #define BNX_DMA_CONFIG_CNTL_BYTE_SWAP		 (1L<<4)
1914 #define BNX_DMA_CONFIG_CNTL_WORD_SWAP		 (1L<<5)
1915 #define BNX_DMA_CONFIG_ONE_DMA			 (1L<<6)
1916 #define BNX_DMA_CONFIG_CNTL_TWO_DMA		 (1L<<7)
1917 #define BNX_DMA_CONFIG_CNTL_FPGA_MODE		 (1L<<8)
1918 #define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA	 (1L<<10)
1919 #define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY	 (1L<<11)
1920 #define BNX_DMA_CONFIG_NO_RCHANS_IN_USE		 (0xfL<<12)
1921 #define BNX_DMA_CONFIG_NO_WCHANS_IN_USE		 (0xfL<<16)
1922 #define BNX_DMA_CONFIG_PCI_CLK_CMP_BITS		 (0x7L<<20)
1923 #define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP		 (1L<<23)
1924 #define BNX_DMA_CONFIG_BIG_SIZE			 (0xfL<<24)
1925 #define BNX_DMA_CONFIG_BIG_SIZE_NONE		 (0x0L<<24)
1926 #define BNX_DMA_CONFIG_BIG_SIZE_64		 (0x1L<<24)
1927 #define BNX_DMA_CONFIG_BIG_SIZE_128		 (0x2L<<24)
1928 #define BNX_DMA_CONFIG_BIG_SIZE_256		 (0x4L<<24)
1929 #define BNX_DMA_CONFIG_BIG_SIZE_512		 (0x8L<<24)
1930 
1931 #define BNX_DMA_BLACKOUT			0x00000c0c
1932 #define BNX_DMA_BLACKOUT_RD_RETRY_BLACKOUT	 (0xffL<<0)
1933 #define BNX_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT	 (0xffL<<8)
1934 #define BNX_DMA_BLACKOUT_WR_RETRY_BLACKOUT	 (0xffL<<16)
1935 
1936 #define BNX_DMA_RCHAN_STAT			0x00000c30
1937 #define BNX_DMA_RCHAN_STAT_COMP_CODE_0		 (0x7L<<0)
1938 #define BNX_DMA_RCHAN_STAT_PAR_ERR_0		 (1L<<3)
1939 #define BNX_DMA_RCHAN_STAT_COMP_CODE_1		 (0x7L<<4)
1940 #define BNX_DMA_RCHAN_STAT_PAR_ERR_1		 (1L<<7)
1941 #define BNX_DMA_RCHAN_STAT_COMP_CODE_2		 (0x7L<<8)
1942 #define BNX_DMA_RCHAN_STAT_PAR_ERR_2		 (1L<<11)
1943 #define BNX_DMA_RCHAN_STAT_COMP_CODE_3		 (0x7L<<12)
1944 #define BNX_DMA_RCHAN_STAT_PAR_ERR_3		 (1L<<15)
1945 #define BNX_DMA_RCHAN_STAT_COMP_CODE_4		 (0x7L<<16)
1946 #define BNX_DMA_RCHAN_STAT_PAR_ERR_4		 (1L<<19)
1947 #define BNX_DMA_RCHAN_STAT_COMP_CODE_5		 (0x7L<<20)
1948 #define BNX_DMA_RCHAN_STAT_PAR_ERR_5		 (1L<<23)
1949 #define BNX_DMA_RCHAN_STAT_COMP_CODE_6		 (0x7L<<24)
1950 #define BNX_DMA_RCHAN_STAT_PAR_ERR_6		 (1L<<27)
1951 #define BNX_DMA_RCHAN_STAT_COMP_CODE_7		 (0x7L<<28)
1952 #define BNX_DMA_RCHAN_STAT_PAR_ERR_7		 (1L<<31)
1953 
1954 #define BNX_DMA_WCHAN_STAT			0x00000c34
1955 #define BNX_DMA_WCHAN_STAT_COMP_CODE_0		 (0x7L<<0)
1956 #define BNX_DMA_WCHAN_STAT_PAR_ERR_0		 (1L<<3)
1957 #define BNX_DMA_WCHAN_STAT_COMP_CODE_1		 (0x7L<<4)
1958 #define BNX_DMA_WCHAN_STAT_PAR_ERR_1		 (1L<<7)
1959 #define BNX_DMA_WCHAN_STAT_COMP_CODE_2		 (0x7L<<8)
1960 #define BNX_DMA_WCHAN_STAT_PAR_ERR_2		 (1L<<11)
1961 #define BNX_DMA_WCHAN_STAT_COMP_CODE_3		 (0x7L<<12)
1962 #define BNX_DMA_WCHAN_STAT_PAR_ERR_3		 (1L<<15)
1963 #define BNX_DMA_WCHAN_STAT_COMP_CODE_4		 (0x7L<<16)
1964 #define BNX_DMA_WCHAN_STAT_PAR_ERR_4		 (1L<<19)
1965 #define BNX_DMA_WCHAN_STAT_COMP_CODE_5		 (0x7L<<20)
1966 #define BNX_DMA_WCHAN_STAT_PAR_ERR_5		 (1L<<23)
1967 #define BNX_DMA_WCHAN_STAT_COMP_CODE_6		 (0x7L<<24)
1968 #define BNX_DMA_WCHAN_STAT_PAR_ERR_6		 (1L<<27)
1969 #define BNX_DMA_WCHAN_STAT_COMP_CODE_7		 (0x7L<<28)
1970 #define BNX_DMA_WCHAN_STAT_PAR_ERR_7		 (1L<<31)
1971 
1972 #define BNX_DMA_RCHAN_ASSIGNMENT		0x00000c38
1973 #define BNX_DMA_RCHAN_ASSIGNMENT_0		 (0xfL<<0)
1974 #define BNX_DMA_RCHAN_ASSIGNMENT_1		 (0xfL<<4)
1975 #define BNX_DMA_RCHAN_ASSIGNMENT_2		 (0xfL<<8)
1976 #define BNX_DMA_RCHAN_ASSIGNMENT_3		 (0xfL<<12)
1977 #define BNX_DMA_RCHAN_ASSIGNMENT_4		 (0xfL<<16)
1978 #define BNX_DMA_RCHAN_ASSIGNMENT_5		 (0xfL<<20)
1979 #define BNX_DMA_RCHAN_ASSIGNMENT_6		 (0xfL<<24)
1980 #define BNX_DMA_RCHAN_ASSIGNMENT_7		 (0xfL<<28)
1981 
1982 #define BNX_DMA_WCHAN_ASSIGNMENT		0x00000c3c
1983 #define BNX_DMA_WCHAN_ASSIGNMENT_0		 (0xfL<<0)
1984 #define BNX_DMA_WCHAN_ASSIGNMENT_1		 (0xfL<<4)
1985 #define BNX_DMA_WCHAN_ASSIGNMENT_2		 (0xfL<<8)
1986 #define BNX_DMA_WCHAN_ASSIGNMENT_3		 (0xfL<<12)
1987 #define BNX_DMA_WCHAN_ASSIGNMENT_4		 (0xfL<<16)
1988 #define BNX_DMA_WCHAN_ASSIGNMENT_5		 (0xfL<<20)
1989 #define BNX_DMA_WCHAN_ASSIGNMENT_6		 (0xfL<<24)
1990 #define BNX_DMA_WCHAN_ASSIGNMENT_7		 (0xfL<<28)
1991 
1992 #define BNX_DMA_RCHAN_STAT_00				0x00000c40
1993 #define BNX_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
1994 
1995 #define BNX_DMA_RCHAN_STAT_01				0x00000c44
1996 #define BNX_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
1997 
1998 #define BNX_DMA_RCHAN_STAT_02			0x00000c48
1999 #define BNX_DMA_RCHAN_STAT_02_LENGTH		 (0xffffL<<0)
2000 #define BNX_DMA_RCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2001 #define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2002 #define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL	 (1L<<18)
2003 
2004 #define BNX_DMA_RCHAN_STAT_10			0x00000c4c
2005 #define BNX_DMA_RCHAN_STAT_11			0x00000c50
2006 #define BNX_DMA_RCHAN_STAT_12			0x00000c54
2007 #define BNX_DMA_RCHAN_STAT_20			0x00000c58
2008 #define BNX_DMA_RCHAN_STAT_21			0x00000c5c
2009 #define BNX_DMA_RCHAN_STAT_22			0x00000c60
2010 #define BNX_DMA_RCHAN_STAT_30			0x00000c64
2011 #define BNX_DMA_RCHAN_STAT_31			0x00000c68
2012 #define BNX_DMA_RCHAN_STAT_32			0x00000c6c
2013 #define BNX_DMA_RCHAN_STAT_40			0x00000c70
2014 #define BNX_DMA_RCHAN_STAT_41			0x00000c74
2015 #define BNX_DMA_RCHAN_STAT_42			0x00000c78
2016 #define BNX_DMA_RCHAN_STAT_50			0x00000c7c
2017 #define BNX_DMA_RCHAN_STAT_51			0x00000c80
2018 #define BNX_DMA_RCHAN_STAT_52			0x00000c84
2019 #define BNX_DMA_RCHAN_STAT_60			0x00000c88
2020 #define BNX_DMA_RCHAN_STAT_61			0x00000c8c
2021 #define BNX_DMA_RCHAN_STAT_62			0x00000c90
2022 #define BNX_DMA_RCHAN_STAT_70			0x00000c94
2023 #define BNX_DMA_RCHAN_STAT_71			0x00000c98
2024 #define BNX_DMA_RCHAN_STAT_72			0x00000c9c
2025 #define BNX_DMA_WCHAN_STAT_00			0x00000ca0
2026 #define BNX_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
2027 
2028 #define BNX_DMA_WCHAN_STAT_01				0x00000ca4
2029 #define BNX_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
2030 
2031 #define BNX_DMA_WCHAN_STAT_02			0x00000ca8
2032 #define BNX_DMA_WCHAN_STAT_02_LENGTH		 (0xffffL<<0)
2033 #define BNX_DMA_WCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2034 #define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2035 #define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL	 (1L<<18)
2036 
2037 #define BNX_DMA_WCHAN_STAT_10			0x00000cac
2038 #define BNX_DMA_WCHAN_STAT_11			0x00000cb0
2039 #define BNX_DMA_WCHAN_STAT_12			0x00000cb4
2040 #define BNX_DMA_WCHAN_STAT_20			0x00000cb8
2041 #define BNX_DMA_WCHAN_STAT_21			0x00000cbc
2042 #define BNX_DMA_WCHAN_STAT_22			0x00000cc0
2043 #define BNX_DMA_WCHAN_STAT_30			0x00000cc4
2044 #define BNX_DMA_WCHAN_STAT_31			0x00000cc8
2045 #define BNX_DMA_WCHAN_STAT_32			0x00000ccc
2046 #define BNX_DMA_WCHAN_STAT_40			0x00000cd0
2047 #define BNX_DMA_WCHAN_STAT_41			0x00000cd4
2048 #define BNX_DMA_WCHAN_STAT_42			0x00000cd8
2049 #define BNX_DMA_WCHAN_STAT_50			0x00000cdc
2050 #define BNX_DMA_WCHAN_STAT_51			0x00000ce0
2051 #define BNX_DMA_WCHAN_STAT_52			0x00000ce4
2052 #define BNX_DMA_WCHAN_STAT_60			0x00000ce8
2053 #define BNX_DMA_WCHAN_STAT_61			0x00000cec
2054 #define BNX_DMA_WCHAN_STAT_62			0x00000cf0
2055 #define BNX_DMA_WCHAN_STAT_70			0x00000cf4
2056 #define BNX_DMA_WCHAN_STAT_71			0x00000cf8
2057 #define BNX_DMA_WCHAN_STAT_72			0x00000cfc
2058 #define BNX_DMA_ARB_STAT_00			0x00000d00
2059 #define BNX_DMA_ARB_STAT_00_MASTER		 (0xffffL<<0)
2060 #define BNX_DMA_ARB_STAT_00_MASTER_ENC		 (0xffL<<16)
2061 #define BNX_DMA_ARB_STAT_00_CUR_BINMSTR		 (0xffL<<24)
2062 
2063 #define BNX_DMA_ARB_STAT_01			0x00000d04
2064 #define BNX_DMA_ARB_STAT_01_LPR_RPTR		 (0xfL<<0)
2065 #define BNX_DMA_ARB_STAT_01_LPR_WPTR		 (0xfL<<4)
2066 #define BNX_DMA_ARB_STAT_01_LPB_RPTR		 (0xfL<<8)
2067 #define BNX_DMA_ARB_STAT_01_LPB_WPTR		 (0xfL<<12)
2068 #define BNX_DMA_ARB_STAT_01_HPR_RPTR		 (0xfL<<16)
2069 #define BNX_DMA_ARB_STAT_01_HPR_WPTR		 (0xfL<<20)
2070 #define BNX_DMA_ARB_STAT_01_HPB_RPTR		 (0xfL<<24)
2071 #define BNX_DMA_ARB_STAT_01_HPB_WPTR		 (0xfL<<28)
2072 
2073 #define BNX_DMA_FUSE_CTRL0_CMD			0x00000f00
2074 #define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE	 (1L<<0)
2075 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE	 (1L<<1)
2076 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT		 (1L<<2)
2077 #define BNX_DMA_FUSE_CTRL0_CMD_LOAD		 (1L<<3)
2078 #define BNX_DMA_FUSE_CTRL0_CMD_SEL		 (0xfL<<8)
2079 
2080 #define BNX_DMA_FUSE_CTRL0_DATA			0x00000f04
2081 #define BNX_DMA_FUSE_CTRL1_CMD			0x00000f08
2082 #define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE	 (1L<<0)
2083 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE	 (1L<<1)
2084 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT		 (1L<<2)
2085 #define BNX_DMA_FUSE_CTRL1_CMD_LOAD		 (1L<<3)
2086 #define BNX_DMA_FUSE_CTRL1_CMD_SEL		 (0xfL<<8)
2087 
2088 #define BNX_DMA_FUSE_CTRL1_DATA			0x00000f0c
2089 #define BNX_DMA_FUSE_CTRL2_CMD			0x00000f10
2090 #define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE	 (1L<<0)
2091 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE	 (1L<<1)
2092 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT		 (1L<<2)
2093 #define BNX_DMA_FUSE_CTRL2_CMD_LOAD		 (1L<<3)
2094 #define BNX_DMA_FUSE_CTRL2_CMD_SEL		 (0xfL<<8)
2095 
2096 #define BNX_DMA_FUSE_CTRL2_DATA			0x00000f14
2097 
2098 
2099 /*
2100  *  context_reg definition
2101  *  offset: 0x1000
2102  */
2103 #define BNX_CTX_COMMAND				0x00001000
2104 #define BNX_CTX_COMMAND_ENABLED			 (1L<<0)
2105 #define BNX_CTX_COMMAND_DISABLE_USAGE_CNT	 (1L<<1)
2106 #define BNX_CTX_COMMAND_DISABLE_PLRU		 (1L<<2)
2107 #define BNX_CTX_COMMAND_DISABLE_COMBINE_READ	 (1L<<3)
2108 #define BNX_CTX_COMMAND_FLUSH_AHEAD		 (0x1fL<<8)
2109 #define BNX_CTX_COMMAND_MEM_INIT		 (1L<<13)
2110 #define BNX_CTX_COMMAND_PAGE_SIZE		 (0xfL<<16)
2111 #define BNX_CTX_COMMAND_PAGE_SIZE_256		 (0L<<16)
2112 #define BNX_CTX_COMMAND_PAGE_SIZE_512		 (1L<<16)
2113 #define BNX_CTX_COMMAND_PAGE_SIZE_1K		 (2L<<16)
2114 #define BNX_CTX_COMMAND_PAGE_SIZE_2K		 (3L<<16)
2115 #define BNX_CTX_COMMAND_PAGE_SIZE_4K		 (4L<<16)
2116 #define BNX_CTX_COMMAND_PAGE_SIZE_8K		 (5L<<16)
2117 #define BNX_CTX_COMMAND_PAGE_SIZE_16K		 (6L<<16)
2118 #define BNX_CTX_COMMAND_PAGE_SIZE_32K		 (7L<<16)
2119 #define BNX_CTX_COMMAND_PAGE_SIZE_64K		 (8L<<16)
2120 #define BNX_CTX_COMMAND_PAGE_SIZE_128K		 (9L<<16)
2121 #define BNX_CTX_COMMAND_PAGE_SIZE_256K		 (10L<<16)
2122 #define BNX_CTX_COMMAND_PAGE_SIZE_512K		 (11L<<16)
2123 #define BNX_CTX_COMMAND_PAGE_SIZE_1M		 (12L<<16)
2124 
2125 #define BNX_CTX_STATUS				0x00001004
2126 #define BNX_CTX_STATUS_LOCK_WAIT		 (1L<<0)
2127 #define BNX_CTX_STATUS_READ_STAT		 (1L<<16)
2128 #define BNX_CTX_STATUS_WRITE_STAT		 (1L<<17)
2129 #define BNX_CTX_STATUS_ACC_STALL_STAT		 (1L<<18)
2130 #define BNX_CTX_STATUS_LOCK_STALL_STAT		 (1L<<19)
2131 
2132 #define BNX_CTX_VIRT_ADDR			0x00001008
2133 #define BNX_CTX_VIRT_ADDR_VIRT_ADDR		 (0x7fffL<<6)
2134 
2135 #define BNX_CTX_PAGE_TBL			0x0000100c
2136 #define BNX_CTX_PAGE_TBL_PAGE_TBL		 (0x3fffL<<6)
2137 
2138 #define BNX_CTX_DATA_ADR			0x00001010
2139 #define BNX_CTX_DATA_ADR_DATA_ADR		 (0x7ffffL<<2)
2140 
2141 #define BNX_CTX_DATA				0x00001014
2142 #define BNX_CTX_LOCK				0x00001018
2143 #define BNX_CTX_LOCK_TYPE			 (0x7L<<0)
2144 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_VOID	 (0x0L<<0)
2145 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL	 (0x1L<<0)
2146 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TX		 (0x2L<<0)
2147 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TIMER	 (0x4L<<0)
2148 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE	 (0x7L<<0)
2149 #define BNX_CTX_LOCK_CID_VALUE			 (0x3fffL<<7)
2150 #define BNX_CTX_LOCK_GRANTED			 (1L<<26)
2151 #define BNX_CTX_LOCK_MODE			 (0x7L<<27)
2152 #define BNX_CTX_LOCK_MODE_UNLOCK		 (0x0L<<27)
2153 #define BNX_CTX_LOCK_MODE_IMMEDIATE		 (0x1L<<27)
2154 #define BNX_CTX_LOCK_MODE_SURE			 (0x2L<<27)
2155 #define BNX_CTX_LOCK_STATUS			 (1L<<30)
2156 #define BNX_CTX_LOCK_REQ			 (1L<<31)
2157 
2158 #define BNX_CTX_CTX_CTRL			0x0000101c
2159 #define BNX_CTX_CTX_CTRL_CTX_ADDR		(0x7ffffL<<2)
2160 #define BNX_CTX_CTX_CTRL_MOD_USAGE_CNT		(0x3L<<21)
2161 #define BNX_CTX_CTX_CTRL_NO_RAM_ACC		(1L<<23)
2162 #define BNX_CTX_CTX_CTRL_PREFETCH_SIZE		(0x3L<<24)
2163 #define BNX_CTX_CTX_CTRL_ATTR			(1L<<26)
2164 #define BNX_CTX_CTX_CTRL_WRITE_REQ		(1L<<30)
2165 #define BNX_CTX_CTX_CTRL_READ_REQ		(1L<<31)
2166 
2167 #define BNX_CTX_CTX_DATA			0x00001020
2168 
2169 #define BNX_CTX_ACCESS_STATUS				0x00001040
2170 #define BNX_CTX_ACCESS_STATUS_MASTERENCODED		 (0xfL<<0)
2171 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYSM		 (0x3L<<10)
2172 #define BNX_CTX_ACCESS_STATUS_PAGETABLEINITSM		 (0x3L<<12)
2173 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM	 (0x3L<<14)
2174 #define BNX_CTX_ACCESS_STATUS_QUALIFIED_REQUEST		 (0x7ffL<<17)
2175 #define BNX_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI	 (0x1fL<<0)
2176 #define BNX_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI	 (0x1fL<<5)
2177 #define BNX_CTX_ACCESS_STATUS_REQUEST_XI		 (0x3fffffL<<10)
2178 
2179 #define BNX_CTX_DBG_LOCK_STATUS			0x00001044
2180 #define BNX_CTX_DBG_LOCK_STATUS_SM		 (0x3ffL<<0)
2181 #define BNX_CTX_DBG_LOCK_STATUS_MATCH		 (0x3ffL<<22)
2182 
2183 #define BNX_CTX_CHNL_LOCK_STATUS_0		0x00001080
2184 #define BNX_CTX_CHNL_LOCK_STATUS_0_CID		 (0x3fffL<<0)
2185 #define BNX_CTX_CHNL_LOCK_STATUS_0_TYPE		 (0x3L<<14)
2186 #define BNX_CTX_CHNL_LOCK_STATUS_0_MODE		 (1L<<16)
2187 
2188 #define BNX_CTX_CHNL_LOCK_STATUS_1		0x00001084
2189 #define BNX_CTX_CHNL_LOCK_STATUS_2		0x00001088
2190 #define BNX_CTX_CHNL_LOCK_STATUS_3		0x0000108c
2191 #define BNX_CTX_CHNL_LOCK_STATUS_4		0x00001090
2192 #define BNX_CTX_CHNL_LOCK_STATUS_5		0x00001094
2193 #define BNX_CTX_CHNL_LOCK_STATUS_6		0x00001098
2194 #define BNX_CTX_CHNL_LOCK_STATUS_7		0x0000109c
2195 #define BNX_CTX_CHNL_LOCK_STATUS_8		0x000010a0
2196 
2197 #define BNX_CTX_CACHE_DATA				0x000010c4
2198 #define BNX_CTX_HOST_PAGE_TBL_CTRL			0x000010c8
2199 #define BNX_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR	 (0x1ffL<<0)
2200 #define BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ		 (1L<<30)
2201 #define BNX_CTX_HOST_PAGE_TBL_CTRL_READ_REQ		 (1L<<31)
2202 
2203 #define BNX_CTX_HOST_PAGE_TBL_DATA0		0x000010cc
2204 #define BNX_CTX_HOST_PAGE_TBL_DATA0_VALID	 (1L<<0)
2205 #define BNX_CTX_HOST_PAGE_TBL_DATA0_VALUE	 (0xffffffL<<8)
2206 
2207 #define BNX_CTX_HOST_PAGE_TBL_DATA1		0x000010d0
2208 
2209 /*
2210  *  emac_reg definition
2211  *  offset: 0x1400
2212  */
2213 #define BNX_EMAC_MODE				0x00001400
2214 #define BNX_EMAC_MODE_RESET			 (1L<<0)
2215 #define BNX_EMAC_MODE_HALF_DUPLEX		 (1L<<1)
2216 #define BNX_EMAC_MODE_PORT			 (0x3L<<2)
2217 #define BNX_EMAC_MODE_PORT_NONE			 (0L<<2)
2218 #define BNX_EMAC_MODE_PORT_MII			 (1L<<2)
2219 #define BNX_EMAC_MODE_PORT_GMII			 (2L<<2)
2220 #define BNX_EMAC_MODE_PORT_MII_10		 (3L<<2)
2221 #define BNX_EMAC_MODE_MAC_LOOP			 (1L<<4)
2222 #define BNX_EMAC_MODE_25G			 (1L<<5)
2223 #define BNX_EMAC_MODE_TAGGED_MAC_CTL		 (1L<<7)
2224 #define BNX_EMAC_MODE_TX_BURST			 (1L<<8)
2225 #define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA	 (1L<<9)
2226 #define BNX_EMAC_MODE_EXT_LINK_POL		 (1L<<10)
2227 #define BNX_EMAC_MODE_FORCE_LINK		 (1L<<11)
2228 #define BNX_EMAC_MODE_MPKT			 (1L<<18)
2229 #define BNX_EMAC_MODE_MPKT_RCVD			 (1L<<19)
2230 #define BNX_EMAC_MODE_ACPI_RCVD			 (1L<<20)
2231 
2232 #define BNX_EMAC_STATUS				0x00001404
2233 #define BNX_EMAC_STATUS_LINK			 (1L<<11)
2234 #define BNX_EMAC_STATUS_LINK_CHANGE		 (1L<<12)
2235 #define BNX_EMAC_STATUS_MI_COMPLETE		 (1L<<22)
2236 #define BNX_EMAC_STATUS_MI_INT			 (1L<<23)
2237 #define BNX_EMAC_STATUS_AP_ERROR		 (1L<<24)
2238 #define BNX_EMAC_STATUS_PARITY_ERROR_STATE	 (1L<<31)
2239 
2240 #define BNX_EMAC_ATTENTION_ENA			0x00001408
2241 #define BNX_EMAC_ATTENTION_ENA_LINK		 (1L<<11)
2242 #define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE	 (1L<<22)
2243 #define BNX_EMAC_ATTENTION_ENA_MI_INT		 (1L<<23)
2244 #define BNX_EMAC_ATTENTION_ENA_AP_ERROR		 (1L<<24)
2245 
2246 #define BNX_EMAC_LED				0x0000140c
2247 #define BNX_EMAC_LED_OVERRIDE			 (1L<<0)
2248 #define BNX_EMAC_LED_1000MB_OVERRIDE		 (1L<<1)
2249 #define BNX_EMAC_LED_100MB_OVERRIDE		 (1L<<2)
2250 #define BNX_EMAC_LED_10MB_OVERRIDE		 (1L<<3)
2251 #define BNX_EMAC_LED_TRAFFIC_OVERRIDE		 (1L<<4)
2252 #define BNX_EMAC_LED_BLNK_TRAFFIC		 (1L<<5)
2253 #define BNX_EMAC_LED_TRAFFIC			 (1L<<6)
2254 #define BNX_EMAC_LED_1000MB			 (1L<<7)
2255 #define BNX_EMAC_LED_100MB			 (1L<<8)
2256 #define BNX_EMAC_LED_10MB			 (1L<<9)
2257 #define BNX_EMAC_LED_TRAFFIC_STAT		 (1L<<10)
2258 #define BNX_EMAC_LED_BLNK_RATE			 (0xfffL<<19)
2259 #define BNX_EMAC_LED_BLNK_RATE_ENA		 (1L<<31)
2260 
2261 #define BNX_EMAC_MAC_MATCH0			0x00001410
2262 #define BNX_EMAC_MAC_MATCH1			0x00001414
2263 #define BNX_EMAC_MAC_MATCH2			0x00001418
2264 #define BNX_EMAC_MAC_MATCH3			0x0000141c
2265 #define BNX_EMAC_MAC_MATCH4			0x00001420
2266 #define BNX_EMAC_MAC_MATCH5			0x00001424
2267 #define BNX_EMAC_MAC_MATCH6			0x00001428
2268 #define BNX_EMAC_MAC_MATCH7			0x0000142c
2269 #define BNX_EMAC_MAC_MATCH8			0x00001430
2270 #define BNX_EMAC_MAC_MATCH9			0x00001434
2271 #define BNX_EMAC_MAC_MATCH10			0x00001438
2272 #define BNX_EMAC_MAC_MATCH11			0x0000143c
2273 #define BNX_EMAC_MAC_MATCH12			0x00001440
2274 #define BNX_EMAC_MAC_MATCH13			0x00001444
2275 #define BNX_EMAC_MAC_MATCH14			0x00001448
2276 #define BNX_EMAC_MAC_MATCH15			0x0000144c
2277 #define BNX_EMAC_MAC_MATCH16			0x00001450
2278 #define BNX_EMAC_MAC_MATCH17			0x00001454
2279 #define BNX_EMAC_MAC_MATCH18			0x00001458
2280 #define BNX_EMAC_MAC_MATCH19			0x0000145c
2281 #define BNX_EMAC_MAC_MATCH20			0x00001460
2282 #define BNX_EMAC_MAC_MATCH21			0x00001464
2283 #define BNX_EMAC_MAC_MATCH22			0x00001468
2284 #define BNX_EMAC_MAC_MATCH23			0x0000146c
2285 #define BNX_EMAC_MAC_MATCH24			0x00001470
2286 #define BNX_EMAC_MAC_MATCH25			0x00001474
2287 #define BNX_EMAC_MAC_MATCH26			0x00001478
2288 #define BNX_EMAC_MAC_MATCH27			0x0000147c
2289 #define BNX_EMAC_MAC_MATCH28			0x00001480
2290 #define BNX_EMAC_MAC_MATCH29			0x00001484
2291 #define BNX_EMAC_MAC_MATCH30			0x00001488
2292 #define BNX_EMAC_MAC_MATCH31			0x0000148c
2293 #define BNX_EMAC_BACKOFF_SEED			0x00001498
2294 #define BNX_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED	 (0x3ffL<<0)
2295 
2296 #define BNX_EMAC_RX_MTU_SIZE			0x0000149c
2297 #define BNX_EMAC_RX_MTU_SIZE_MTU_SIZE		 (0xffffL<<0)
2298 #define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA		 (1L<<31)
2299 
2300 #define BNX_EMAC_SERDES_CNTL			0x000014a4
2301 #define BNX_EMAC_SERDES_CNTL_RXR		 (0x7L<<0)
2302 #define BNX_EMAC_SERDES_CNTL_RXG		 (0x3L<<3)
2303 #define BNX_EMAC_SERDES_CNTL_RXCKSEL		 (1L<<6)
2304 #define BNX_EMAC_SERDES_CNTL_TXBIAS		 (0x7L<<7)
2305 #define BNX_EMAC_SERDES_CNTL_BGMAX		 (1L<<10)
2306 #define BNX_EMAC_SERDES_CNTL_BGMIN		 (1L<<11)
2307 #define BNX_EMAC_SERDES_CNTL_TXMODE		 (1L<<12)
2308 #define BNX_EMAC_SERDES_CNTL_TXEDGE		 (1L<<13)
2309 #define BNX_EMAC_SERDES_CNTL_SERDES_MODE	 (1L<<14)
2310 #define BNX_EMAC_SERDES_CNTL_PLLTEST		 (1L<<15)
2311 #define BNX_EMAC_SERDES_CNTL_CDET_EN		 (1L<<16)
2312 #define BNX_EMAC_SERDES_CNTL_TBI_LBK		 (1L<<17)
2313 #define BNX_EMAC_SERDES_CNTL_REMOTE_LBK		 (1L<<18)
2314 #define BNX_EMAC_SERDES_CNTL_REV_PHASE		 (1L<<19)
2315 #define BNX_EMAC_SERDES_CNTL_REGCTL12		 (0x3L<<20)
2316 #define BNX_EMAC_SERDES_CNTL_REGCTL25		 (0x3L<<22)
2317 
2318 #define BNX_EMAC_SERDES_STATUS			0x000014a8
2319 #define BNX_EMAC_SERDES_STATUS_RX_STAT		 (0xffL<<0)
2320 #define BNX_EMAC_SERDES_STATUS_COMMA_DET	 (1L<<8)
2321 
2322 #define BNX_EMAC_MDIO_COMM			0x000014ac
2323 #define BNX_EMAC_MDIO_COMM_DATA			 (0xffffL<<0)
2324 #define BNX_EMAC_MDIO_COMM_REG_ADDR		 (0x1fL<<16)
2325 #define BNX_EMAC_MDIO_COMM_PHY_ADDR		 (0x1fL<<21)
2326 #define BNX_EMAC_MDIO_COMM_COMMAND		 (0x3L<<26)
2327 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0	 (0L<<26)
2328 #define BNX_EMAC_MDIO_COMM_COMMAND_WRITE	 (1L<<26)
2329 #define BNX_EMAC_MDIO_COMM_COMMAND_READ		 (2L<<26)
2330 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3	 (3L<<26)
2331 #define BNX_EMAC_MDIO_COMM_FAIL			 (1L<<28)
2332 #define BNX_EMAC_MDIO_COMM_START_BUSY		 (1L<<29)
2333 #define BNX_EMAC_MDIO_COMM_DISEXT		 (1L<<30)
2334 
2335 #define BNX_EMAC_MDIO_STATUS			0x000014b0
2336 #define BNX_EMAC_MDIO_STATUS_LINK		 (1L<<0)
2337 #define BNX_EMAC_MDIO_STATUS_10MB		 (1L<<1)
2338 
2339 #define BNX_EMAC_MDIO_MODE			0x000014b4
2340 #define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE	 (1L<<1)
2341 #define BNX_EMAC_MDIO_MODE_AUTO_POLL		 (1L<<4)
2342 #define BNX_EMAC_MDIO_MODE_BIT_BANG		 (1L<<8)
2343 #define BNX_EMAC_MDIO_MODE_MDIO			 (1L<<9)
2344 #define BNX_EMAC_MDIO_MODE_MDIO_OE		 (1L<<10)
2345 #define BNX_EMAC_MDIO_MODE_MDC			 (1L<<11)
2346 #define BNX_EMAC_MDIO_MODE_MDINT		 (1L<<12)
2347 #define BNX_EMAC_MDIO_MODE_CLOCK_CNT		 (0x1fL<<16)
2348 
2349 #define BNX_EMAC_MDIO_AUTO_STATUS		0x000014b8
2350 #define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR	 (1L<<0)
2351 
2352 #define BNX_EMAC_TX_MODE			0x000014bc
2353 #define BNX_EMAC_TX_MODE_RESET			 (1L<<0)
2354 #define BNX_EMAC_TX_MODE_EXT_PAUSE_EN		 (1L<<3)
2355 #define BNX_EMAC_TX_MODE_FLOW_EN		 (1L<<4)
2356 #define BNX_EMAC_TX_MODE_BIG_BACKOFF		 (1L<<5)
2357 #define BNX_EMAC_TX_MODE_LONG_PAUSE		 (1L<<6)
2358 #define BNX_EMAC_TX_MODE_LINK_AWARE		 (1L<<7)
2359 
2360 #define BNX_EMAC_TX_STATUS			0x000014c0
2361 #define BNX_EMAC_TX_STATUS_XOFFED		 (1L<<0)
2362 #define BNX_EMAC_TX_STATUS_XOFF_SENT		 (1L<<1)
2363 #define BNX_EMAC_TX_STATUS_XON_SENT		 (1L<<2)
2364 #define BNX_EMAC_TX_STATUS_LINK_UP		 (1L<<3)
2365 #define BNX_EMAC_TX_STATUS_UNDERRUN		 (1L<<4)
2366 
2367 #define BNX_EMAC_TX_LENGTHS			0x000014c4
2368 #define BNX_EMAC_TX_LENGTHS_SLOT		 (0xffL<<0)
2369 #define BNX_EMAC_TX_LENGTHS_IPG			 (0xfL<<8)
2370 #define BNX_EMAC_TX_LENGTHS_IPG_CRS		 (0x3L<<12)
2371 
2372 #define BNX_EMAC_RX_MODE			0x000014c8
2373 #define BNX_EMAC_RX_MODE_RESET			 (1L<<0)
2374 #define BNX_EMAC_RX_MODE_FLOW_EN		 (1L<<2)
2375 #define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL	 (1L<<3)
2376 #define BNX_EMAC_RX_MODE_KEEP_PAUSE		 (1L<<4)
2377 #define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE	 (1L<<5)
2378 #define BNX_EMAC_RX_MODE_ACCEPT_RUNTS		 (1L<<6)
2379 #define BNX_EMAC_RX_MODE_LLC_CHK		 (1L<<7)
2380 #define BNX_EMAC_RX_MODE_PROMISCUOUS		 (1L<<8)
2381 #define BNX_EMAC_RX_MODE_NO_CRC_CHK		 (1L<<9)
2382 #define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG		 (1L<<10)
2383 #define BNX_EMAC_RX_MODE_FILT_BROADCAST		 (1L<<11)
2384 #define BNX_EMAC_RX_MODE_SORT_MODE		 (1L<<12)
2385 
2386 #define BNX_EMAC_RX_STATUS			0x000014cc
2387 #define BNX_EMAC_RX_STATUS_FFED			 (1L<<0)
2388 #define BNX_EMAC_RX_STATUS_FF_RECEIVED		 (1L<<1)
2389 #define BNX_EMAC_RX_STATUS_N_RECEIVED		 (1L<<2)
2390 
2391 #define BNX_EMAC_MULTICAST_HASH0			0x000014d0
2392 #define BNX_EMAC_MULTICAST_HASH1			0x000014d4
2393 #define BNX_EMAC_MULTICAST_HASH2			0x000014d8
2394 #define BNX_EMAC_MULTICAST_HASH3			0x000014dc
2395 #define BNX_EMAC_MULTICAST_HASH4			0x000014e0
2396 #define BNX_EMAC_MULTICAST_HASH5			0x000014e4
2397 #define BNX_EMAC_MULTICAST_HASH6			0x000014e8
2398 #define BNX_EMAC_MULTICAST_HASH7			0x000014ec
2399 #define BNX_EMAC_RX_STAT_IFHCINOCTETS			0x00001500
2400 #define BNX_EMAC_RX_STAT_IFHCINBADOCTETS		0x00001504
2401 #define BNX_EMAC_RX_STAT_ETHERSTATSFRAGMENTS		0x00001508
2402 #define BNX_EMAC_RX_STAT_IFHCINUCASTPKTS		0x0000150c
2403 #define BNX_EMAC_RX_STAT_IFHCINMULTICASTPKTS		0x00001510
2404 #define BNX_EMAC_RX_STAT_IFHCINBROADCASTPKTS		0x00001514
2405 #define BNX_EMAC_RX_STAT_DOT3STATSFCSERRORS		0x00001518
2406 #define BNX_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS	0x0000151c
2407 #define BNX_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS	0x00001520
2408 #define BNX_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED		0x00001524
2409 #define BNX_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED	0x00001528
2410 #define BNX_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED	0x0000152c
2411 #define BNX_EMAC_RX_STAT_XOFFSTATEENTERED		0x00001530
2412 #define BNX_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG		0x00001534
2413 #define BNX_EMAC_RX_STAT_ETHERSTATSJABBERS		0x00001538
2414 #define BNX_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS	0x0000153c
2415 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS		0x00001540
2416 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x00001544
2417 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001548
2418 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x0000154c
2419 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001550
2420 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x00001554
2421 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001558
2422 #define BNX_EMAC_RXMAC_DEBUG0				0x0000155c
2423 #define BNX_EMAC_RXMAC_DEBUG1				0x00001560
2424 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT	 (1L<<0)
2425 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE		 (1L<<1)
2426 #define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC			 (1L<<2)
2427 #define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR			 (1L<<3)
2428 #define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR		 (1L<<4)
2429 #define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA			 (1L<<5)
2430 #define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START		 (1L<<6)
2431 #define BNX_EMAC_RXMAC_DEBUG1_BYTE_COUNT		 (0xffffL<<7)
2432 #define BNX_EMAC_RXMAC_DEBUG1_SLOT_TIME			 (0xffL<<23)
2433 
2434 #define BNX_EMAC_RXMAC_DEBUG2			0x00001564
2435 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE		 (0x7L<<0)
2436 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE	 (0x0L<<0)
2437 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SFD	 (0x1L<<0)
2438 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DATA	 (0x2L<<0)
2439 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP	 (0x3L<<0)
2440 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_EXT	 (0x4L<<0)
2441 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DROP	 (0x5L<<0)
2442 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP	 (0x6L<<0)
2443 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_FC	 (0x7L<<0)
2444 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE		 (0xfL<<3)
2445 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE	 (0x0L<<3)
2446 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0	 (0x1L<<3)
2447 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1	 (0x2L<<3)
2448 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2	 (0x3L<<3)
2449 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3	 (0x4L<<3)
2450 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT	 (0x5L<<3)
2451 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT	 (0x6L<<3)
2452 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS	 (0x7L<<3)
2453 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST	 (0x8L<<3)
2454 #define BNX_EMAC_RXMAC_DEBUG2_BYTE_IN		 (0xffL<<7)
2455 #define BNX_EMAC_RXMAC_DEBUG2_FALSEC		 (1L<<15)
2456 #define BNX_EMAC_RXMAC_DEBUG2_TAGGED		 (1L<<16)
2457 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE	 (1L<<18)
2458 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE	 (0L<<18)
2459 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
2460 #define BNX_EMAC_RXMAC_DEBUG2_SE_COUNTER	 (0xfL<<19)
2461 #define BNX_EMAC_RXMAC_DEBUG2_QUANTA		 (0x1fL<<23)
2462 
2463 #define BNX_EMAC_RXMAC_DEBUG3			0x00001568
2464 #define BNX_EMAC_RXMAC_DEBUG3_PAUSE_CTR		 (0xffffL<<0)
2465 #define BNX_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR	 (0xffffL<<16)
2466 
2467 #define BNX_EMAC_RXMAC_DEBUG4			0x0000156c
2468 #define BNX_EMAC_RXMAC_DEBUG4_TYPE_FIELD	 (0xffffL<<0)
2469 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE	 (0x3fL<<16)
2470 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE	 (0x0L<<16)
2471 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2	 (0x1L<<16)
2472 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3	 (0x2L<<16)
2473 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI	 (0x3L<<16)
2474 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2	 (0x7L<<16)
2475 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3	 (0x5L<<16)
2476 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1	 (0x6L<<16)
2477 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2	 (0x7L<<16)
2478 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3	 (0x8L<<16)
2479 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2	 (0x9L<<16)
2480 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3	 (0xaL<<16)
2481 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1	 (0xeL<<16)
2482 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2	 (0xfL<<16)
2483 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK	 (0x10L<<16)
2484 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC	 (0x11L<<16)
2485 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2	 (0x12L<<16)
2486 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3	 (0x13L<<16)
2487 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1	 (0x14L<<16)
2488 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2	 (0x15L<<16)
2489 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3	 (0x16L<<16)
2490 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE	 (0x17L<<16)
2491 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC	 (0x18L<<16)
2492 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE	 (0x19L<<16)
2493 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD	 (0x1aL<<16)
2494 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC	 (0x1bL<<16)
2495 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH	 (0x1cL<<16)
2496 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF	 (0x1dL<<16)
2497 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XON	 (0x1eL<<16)
2498 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED	 (0x1fL<<16)
2499 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
2500 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE	 (0x21L<<16)
2501 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL	 (0x22L<<16)
2502 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1	 (0x23L<<16)
2503 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2	 (0x24L<<16)
2504 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3	 (0x25L<<16)
2505 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE	 (0x26L<<16)
2506 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE	 (0x27L<<16)
2507 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL	 (0x28L<<16)
2508 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE	 (0x29L<<16)
2509 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP	 (0x2aL<<16)
2510 #define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT		 (1L<<22)
2511 #define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED	 (1L<<23)
2512 #define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER	 (1L<<24)
2513 #define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA		 (1L<<25)
2514 #define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND		 (1L<<26)
2515 #define BNX_EMAC_RXMAC_DEBUG4_ADVANCE		 (1L<<27)
2516 #define BNX_EMAC_RXMAC_DEBUG4_START		 (1L<<28)
2517 
2518 #define BNX_EMAC_RXMAC_DEBUG5				0x00001570
2519 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM			 (0x7L<<0)
2520 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE		 (0L<<0)
2521 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF		 (1L<<0)
2522 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT	 (2L<<0)
2523 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC	 (3L<<0)
2524 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE	 (4L<<0)
2525 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL	 (5L<<0)
2526 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT	 (6L<<0)
2527 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1		 (0x7L<<4)
2528 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW		 (0x0L<<4)
2529 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT		 (0x1L<<4)
2530 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF		 (0x2L<<4)
2531 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF		 (0x3L<<4)
2532 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF		 (0x4L<<4)
2533 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF		 (0x6L<<4)
2534 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF		 (0x7L<<4)
2535 #define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED		 (1L<<7)
2536 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF0		 (0x7L<<8)
2537 #define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL		 (1L<<11)
2538 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE		 (1L<<12)
2539 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA			 (1L<<13)
2540 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT			 (1L<<14)
2541 #define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT			 (1L<<15)
2542 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE		 (0x3L<<16)
2543 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT		 (1L<<19)
2544 #define BNX_EMAC_RXMAC_DEBUG5_FMLEN			 (0xfffL<<20)
2545 
2546 #define BNX_EMAC_RX_STAT_AC0			0x00001580
2547 #define BNX_EMAC_RX_STAT_AC1			0x00001584
2548 #define BNX_EMAC_RX_STAT_AC2			0x00001588
2549 #define BNX_EMAC_RX_STAT_AC3			0x0000158c
2550 #define BNX_EMAC_RX_STAT_AC4			0x00001590
2551 #define BNX_EMAC_RX_STAT_AC5			0x00001594
2552 #define BNX_EMAC_RX_STAT_AC6			0x00001598
2553 #define BNX_EMAC_RX_STAT_AC7			0x0000159c
2554 #define BNX_EMAC_RX_STAT_AC8			0x000015a0
2555 #define BNX_EMAC_RX_STAT_AC9			0x000015a4
2556 #define BNX_EMAC_RX_STAT_AC10			0x000015a8
2557 #define BNX_EMAC_RX_STAT_AC11			0x000015ac
2558 #define BNX_EMAC_RX_STAT_AC12			0x000015b0
2559 #define BNX_EMAC_RX_STAT_AC13			0x000015b4
2560 #define BNX_EMAC_RX_STAT_AC14			0x000015b8
2561 #define BNX_EMAC_RX_STAT_AC15			0x000015bc
2562 #define BNX_EMAC_RX_STAT_AC16			0x000015c0
2563 #define BNX_EMAC_RX_STAT_AC17			0x000015c4
2564 #define BNX_EMAC_RX_STAT_AC18			0x000015c8
2565 #define BNX_EMAC_RX_STAT_AC19			0x000015cc
2566 #define BNX_EMAC_RX_STAT_AC20			0x000015d0
2567 #define BNX_EMAC_RX_STAT_AC21			0x000015d4
2568 #define BNX_EMAC_RX_STAT_AC22			0x000015d8
2569 #define BNX_EMAC_RXMAC_SUC_DBG_OVERRUNVEC	0x000015dc
2570 #define BNX_EMAC_TX_STAT_IFHCOUTOCTETS		0x00001600
2571 #define BNX_EMAC_TX_STAT_IFHCOUTBADOCTETS	0x00001604
2572 #define BNX_EMAC_TX_STAT_ETHERSTATSCOLLISIONS	0x00001608
2573 #define BNX_EMAC_TX_STAT_OUTXONSENT		0x0000160c
2574 #define BNX_EMAC_TX_STAT_OUTXOFFSENT		0x00001610
2575 #define BNX_EMAC_TX_STAT_FLOWCONTROLDONE	0x00001614
2576 #define BNX_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES	0x00001618
2577 #define BNX_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES	0x0000161c
2578 #define BNX_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS	0x00001620
2579 #define BNX_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS	0x00001624
2580 #define BNX_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS	0x00001628
2581 #define BNX_EMAC_TX_STAT_IFHCOUTUCASTPKTS		0x0000162c
2582 #define BNX_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS		0x00001630
2583 #define BNX_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS		0x00001634
2584 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS	0x00001638
2585 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x0000163c
2586 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001640
2587 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x00001644
2588 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001648
2589 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x0000164c
2590 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001650
2591 #define BNX_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS	0x00001654
2592 #define BNX_EMAC_TXMAC_DEBUG0			0x00001658
2593 #define BNX_EMAC_TXMAC_DEBUG1			0x0000165c
2594 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE		 (0xfL<<0)
2595 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE	 (0x0L<<0)
2596 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_START0	 (0x1L<<0)
2597 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0	 (0x4L<<0)
2598 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1	 (0x5L<<0)
2599 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2	 (0x6L<<0)
2600 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3	 (0x7L<<0)
2601 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0	 (0x8L<<0)
2602 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1	 (0x9L<<0)
2603 #define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE	 (1L<<4)
2604 #define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC		 (1L<<5)
2605 #define BNX_EMAC_TXMAC_DEBUG1_SE_COUNTER	 (0xfL<<6)
2606 #define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE	 (1L<<10)
2607 #define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION	 (1L<<11)
2608 #define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER		 (1L<<12)
2609 #define BNX_EMAC_TXMAC_DEBUG1_DEFERRED		 (1L<<13)
2610 #define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE		 (1L<<14)
2611 #define BNX_EMAC_TXMAC_DEBUG1_IPG_TIME		 (0xfL<<15)
2612 #define BNX_EMAC_TXMAC_DEBUG1_SLOT_TIME		 (0xffL<<19)
2613 
2614 #define BNX_EMAC_TXMAC_DEBUG2			0x00001660
2615 #define BNX_EMAC_TXMAC_DEBUG2_BACK_OFF		 (0x3ffL<<0)
2616 #define BNX_EMAC_TXMAC_DEBUG2_BYTE_COUNT	 (0xffffL<<10)
2617 #define BNX_EMAC_TXMAC_DEBUG2_COL_COUNT		 (0x1fL<<26)
2618 #define BNX_EMAC_TXMAC_DEBUG2_COL_BIT		 (1L<<31)
2619 
2620 #define BNX_EMAC_TXMAC_DEBUG3			0x00001664
2621 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE		 (0xfL<<0)
2622 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE	 (0x0L<<0)
2623 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1	 (0x1L<<0)
2624 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2	 (0x2L<<0)
2625 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SFD	 (0x3L<<0)
2626 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_DATA	 (0x4L<<0)
2627 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1	 (0x5L<<0)
2628 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2	 (0x6L<<0)
2629 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EXT	 (0x7L<<0)
2630 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATB	 (0x8L<<0)
2631 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATG	 (0x9L<<0)
2632 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_JAM	 (0xaL<<0)
2633 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM	 (0xbL<<0)
2634 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM	 (0xcL<<0)
2635 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT	 (0xdL<<0)
2636 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF	 (0xeL<<0)
2637 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE	 (0x7L<<4)
2638 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE	 (0x0L<<4)
2639 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT	 (0x1L<<4)
2640 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI	 (0x2L<<4)
2641 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_MC	 (0x3L<<4)
2642 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2	 (0x4L<<4)
2643 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3	 (0x5L<<4)
2644 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC	 (0x6L<<4)
2645 #define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE		 (1L<<7)
2646 #define BNX_EMAC_TXMAC_DEBUG3_XOFF		 (1L<<8)
2647 #define BNX_EMAC_TXMAC_DEBUG3_SE_COUNTER	 (0xfL<<9)
2648 #define BNX_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER	 (0x1fL<<13)
2649 
2650 #define BNX_EMAC_TXMAC_DEBUG4			0x00001668
2651 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER	 (0xffffL<<0)
2652 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE	 (0xfL<<16)
2653 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE	 (0x0L<<16)
2654 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1	 (0x2L<<16)
2655 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2	 (0x3L<<16)
2656 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3	 (0x6L<<16)
2657 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1	 (0x7L<<16)
2658 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2	 (0x5L<<16)
2659 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3	 (0x4L<<16)
2660 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE	 (0xcL<<16)
2661 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD	 (0xeL<<16)
2662 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME	 (0xaL<<16)
2663 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1	 (0x8L<<16)
2664 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2	 (0x9L<<16)
2665 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT	 (0xdL<<16)
2666 #define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID	 (1L<<20)
2667 #define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC	 (1L<<21)
2668 #define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED	 (1L<<22)
2669 #define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER		 (1L<<23)
2670 #define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND	 (1L<<24)
2671 #define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING	 (1L<<25)
2672 #define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC		 (1L<<26)
2673 #define BNX_EMAC_TXMAC_DEBUG4_COLLIDING		 (1L<<27)
2674 #define BNX_EMAC_TXMAC_DEBUG4_COL_IN		 (1L<<28)
2675 #define BNX_EMAC_TXMAC_DEBUG4_BURSTING		 (1L<<29)
2676 #define BNX_EMAC_TXMAC_DEBUG4_ADVANCE		 (1L<<30)
2677 #define BNX_EMAC_TXMAC_DEBUG4_GO		 (1L<<31)
2678 
2679 #define BNX_EMAC_TX_STAT_AC0			0x00001680
2680 #define BNX_EMAC_TX_STAT_AC1			0x00001684
2681 #define BNX_EMAC_TX_STAT_AC2			0x00001688
2682 #define BNX_EMAC_TX_STAT_AC3			0x0000168c
2683 #define BNX_EMAC_TX_STAT_AC4			0x00001690
2684 #define BNX_EMAC_TX_STAT_AC5			0x00001694
2685 #define BNX_EMAC_TX_STAT_AC6			0x00001698
2686 #define BNX_EMAC_TX_STAT_AC7			0x0000169c
2687 #define BNX_EMAC_TX_STAT_AC8			0x000016a0
2688 #define BNX_EMAC_TX_STAT_AC9			0x000016a4
2689 #define BNX_EMAC_TX_STAT_AC10			0x000016a8
2690 #define BNX_EMAC_TX_STAT_AC11			0x000016ac
2691 #define BNX_EMAC_TX_STAT_AC12			0x000016b0
2692 #define BNX_EMAC_TX_STAT_AC13			0x000016b4
2693 #define BNX_EMAC_TX_STAT_AC14			0x000016b8
2694 #define BNX_EMAC_TX_STAT_AC15			0x000016bc
2695 #define BNX_EMAC_TX_STAT_AC16			0x000016c0
2696 #define BNX_EMAC_TX_STAT_AC17			0x000016c4
2697 #define BNX_EMAC_TX_STAT_AC18			0x000016c8
2698 #define BNX_EMAC_TX_STAT_AC19			0x000016cc
2699 #define BNX_EMAC_TX_STAT_AC20			0x000016d0
2700 #define BNX_EMAC_TX_STAT_AC21			0x000016d4
2701 #define BNX_EMAC_TXMAC_SUC_DBG_OVERRUNVEC	0x000016d8
2702 
2703 
2704 /*
2705  *  rpm_reg definition
2706  *  offset: 0x1800
2707  */
2708 #define BNX_RPM_COMMAND				0x00001800
2709 #define BNX_RPM_COMMAND_ENABLED			 (1L<<0)
2710 #define BNX_RPM_COMMAND_OVERRUN_ABORT		 (1L<<4)
2711 
2712 #define BNX_RPM_STATUS				0x00001804
2713 #define BNX_RPM_STATUS_MBUF_WAIT		 (1L<<0)
2714 #define BNX_RPM_STATUS_FREE_WAIT		 (1L<<1)
2715 
2716 #define BNX_RPM_CONFIG				0x00001808
2717 #define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM		 (1L<<0)
2718 #define BNX_RPM_CONFIG_ACPI_ENA			 (1L<<1)
2719 #define BNX_RPM_CONFIG_ACPI_KEEP		 (1L<<2)
2720 #define BNX_RPM_CONFIG_MP_KEEP			 (1L<<3)
2721 #define BNX_RPM_CONFIG_SORT_VECT_VAL		 (0xfL<<4)
2722 #define BNX_RPM_CONFIG_IGNORE_VLAN		 (1L<<31)
2723 
2724 #define BNX_RPM_MGMT_PKT_CTRL			0x0000180c
2725 #define BNX_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN	 (1L<<30)
2726 #define BNX_RPM_MGMT_PKT_CTRL_MGMT_EN		 (1L<<31)
2727 
2728 #define BNX_RPM_VLAN_MATCH0			0x00001810
2729 #define BNX_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
2730 
2731 #define BNX_RPM_VLAN_MATCH1			0x00001814
2732 #define BNX_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
2733 
2734 #define BNX_RPM_VLAN_MATCH2			0x00001818
2735 #define BNX_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
2736 
2737 #define BNX_RPM_VLAN_MATCH3			0x0000181c
2738 #define BNX_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
2739 
2740 #define BNX_RPM_SORT_USER0			0x00001820
2741 #define BNX_RPM_SORT_USER0_PM_EN		 (0xffffL<<0)
2742 #define BNX_RPM_SORT_USER0_BC_EN		 (1L<<16)
2743 #define BNX_RPM_SORT_USER0_MC_EN		 (1L<<17)
2744 #define BNX_RPM_SORT_USER0_MC_HSH_EN		 (1L<<18)
2745 #define BNX_RPM_SORT_USER0_PROM_EN		 (1L<<19)
2746 #define BNX_RPM_SORT_USER0_VLAN_EN		 (0xfL<<20)
2747 #define BNX_RPM_SORT_USER0_PROM_VLAN		 (1L<<24)
2748 #define BNX_RPM_SORT_USER0_ENA			 (1L<<31)
2749 
2750 #define BNX_RPM_SORT_USER1			0x00001824
2751 #define BNX_RPM_SORT_USER1_PM_EN		 (0xffffL<<0)
2752 #define BNX_RPM_SORT_USER1_BC_EN		 (1L<<16)
2753 #define BNX_RPM_SORT_USER1_MC_EN		 (1L<<17)
2754 #define BNX_RPM_SORT_USER1_MC_HSH_EN		 (1L<<18)
2755 #define BNX_RPM_SORT_USER1_PROM_EN		 (1L<<19)
2756 #define BNX_RPM_SORT_USER1_VLAN_EN		 (0xfL<<20)
2757 #define BNX_RPM_SORT_USER1_PROM_VLAN		 (1L<<24)
2758 #define BNX_RPM_SORT_USER1_ENA			 (1L<<31)
2759 
2760 #define BNX_RPM_SORT_USER2			0x00001828
2761 #define BNX_RPM_SORT_USER2_PM_EN		 (0xffffL<<0)
2762 #define BNX_RPM_SORT_USER2_BC_EN		 (1L<<16)
2763 #define BNX_RPM_SORT_USER2_MC_EN		 (1L<<17)
2764 #define BNX_RPM_SORT_USER2_MC_HSH_EN		 (1L<<18)
2765 #define BNX_RPM_SORT_USER2_PROM_EN		 (1L<<19)
2766 #define BNX_RPM_SORT_USER2_VLAN_EN		 (0xfL<<20)
2767 #define BNX_RPM_SORT_USER2_PROM_VLAN		 (1L<<24)
2768 #define BNX_RPM_SORT_USER2_ENA			 (1L<<31)
2769 
2770 #define BNX_RPM_SORT_USER3			0x0000182c
2771 #define BNX_RPM_SORT_USER3_PM_EN		 (0xffffL<<0)
2772 #define BNX_RPM_SORT_USER3_BC_EN		 (1L<<16)
2773 #define BNX_RPM_SORT_USER3_MC_EN		 (1L<<17)
2774 #define BNX_RPM_SORT_USER3_MC_HSH_EN		 (1L<<18)
2775 #define BNX_RPM_SORT_USER3_PROM_EN		 (1L<<19)
2776 #define BNX_RPM_SORT_USER3_VLAN_EN		 (0xfL<<20)
2777 #define BNX_RPM_SORT_USER3_PROM_VLAN		 (1L<<24)
2778 #define BNX_RPM_SORT_USER3_ENA			 (1L<<31)
2779 
2780 #define BNX_RPM_STAT_L2_FILTER_DISCARDS		0x00001840
2781 #define BNX_RPM_STAT_RULE_CHECKER_DISCARDS	0x00001844
2782 #define BNX_RPM_STAT_IFINFTQDISCARDS		0x00001848
2783 #define BNX_RPM_STAT_IFINMBUFDISCARD		0x0000184c
2784 #define BNX_RPM_STAT_RULE_CHECKER_P4_HIT	0x00001850
2785 #define BNX_RPM_STAT_AC0			0x00001880
2786 #define BNX_RPM_STAT_AC1			0x00001884
2787 #define BNX_RPM_STAT_AC2			0x00001888
2788 #define BNX_RPM_STAT_AC3			0x0000188c
2789 #define BNX_RPM_STAT_AC4			0x00001890
2790 #define BNX_RPM_RC_CNTL_0			0x00001900
2791 #define BNX_RPM_RC_CNTL_0_OFFSET		 (0xffL<<0)
2792 #define BNX_RPM_RC_CNTL_0_CLASS			 (0x7L<<8)
2793 #define BNX_RPM_RC_CNTL_0_PRIORITY		 (1L<<11)
2794 #define BNX_RPM_RC_CNTL_0_P4			 (1L<<12)
2795 #define BNX_RPM_RC_CNTL_0_HDR_TYPE		 (0x7L<<13)
2796 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_START	 (0L<<13)
2797 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP		 (1L<<13)
2798 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP		 (2L<<13)
2799 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP		 (3L<<13)
2800 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA		 (4L<<13)
2801 #define BNX_RPM_RC_CNTL_0_COMP			 (0x3L<<16)
2802 #define BNX_RPM_RC_CNTL_0_COMP_EQUAL		 (0L<<16)
2803 #define BNX_RPM_RC_CNTL_0_COMP_NEQUAL		 (1L<<16)
2804 #define BNX_RPM_RC_CNTL_0_COMP_GREATER		 (2L<<16)
2805 #define BNX_RPM_RC_CNTL_0_COMP_LESS		 (3L<<16)
2806 #define BNX_RPM_RC_CNTL_0_SBIT			 (1L<<19)
2807 #define BNX_RPM_RC_CNTL_0_CMDSEL		 (0xfL<<20)
2808 #define BNX_RPM_RC_CNTL_0_MAP			 (1L<<24)
2809 #define BNX_RPM_RC_CNTL_0_DISCARD		 (1L<<25)
2810 #define BNX_RPM_RC_CNTL_0_MASK			 (1L<<26)
2811 #define BNX_RPM_RC_CNTL_0_P1			 (1L<<27)
2812 #define BNX_RPM_RC_CNTL_0_P2			 (1L<<28)
2813 #define BNX_RPM_RC_CNTL_0_P3			 (1L<<29)
2814 #define BNX_RPM_RC_CNTL_0_NBIT			 (1L<<30)
2815 
2816 #define BNX_RPM_RC_VALUE_MASK_0			0x00001904
2817 #define BNX_RPM_RC_VALUE_MASK_0_VALUE		 (0xffffL<<0)
2818 #define BNX_RPM_RC_VALUE_MASK_0_MASK		 (0xffffL<<16)
2819 
2820 #define BNX_RPM_RC_CNTL_1			0x00001908
2821 #define BNX_RPM_RC_CNTL_1_A			 (0x3ffffL<<0)
2822 #define BNX_RPM_RC_CNTL_1_B			 (0xfffL<<19)
2823 
2824 #define BNX_RPM_RC_VALUE_MASK_1			0x0000190c
2825 #define BNX_RPM_RC_CNTL_2			0x00001910
2826 #define BNX_RPM_RC_CNTL_2_A			 (0x3ffffL<<0)
2827 #define BNX_RPM_RC_CNTL_2_B			 (0xfffL<<19)
2828 
2829 #define BNX_RPM_RC_VALUE_MASK_2			0x00001914
2830 #define BNX_RPM_RC_CNTL_3			0x00001918
2831 #define BNX_RPM_RC_CNTL_3_A			 (0x3ffffL<<0)
2832 #define BNX_RPM_RC_CNTL_3_B			 (0xfffL<<19)
2833 
2834 #define BNX_RPM_RC_VALUE_MASK_3			0x0000191c
2835 #define BNX_RPM_RC_CNTL_4			0x00001920
2836 #define BNX_RPM_RC_CNTL_4_A			 (0x3ffffL<<0)
2837 #define BNX_RPM_RC_CNTL_4_B			 (0xfffL<<19)
2838 
2839 #define BNX_RPM_RC_VALUE_MASK_4			0x00001924
2840 #define BNX_RPM_RC_CNTL_5			0x00001928
2841 #define BNX_RPM_RC_CNTL_5_A			 (0x3ffffL<<0)
2842 #define BNX_RPM_RC_CNTL_5_B			 (0xfffL<<19)
2843 
2844 #define BNX_RPM_RC_VALUE_MASK_5			0x0000192c
2845 #define BNX_RPM_RC_CNTL_6			0x00001930
2846 #define BNX_RPM_RC_CNTL_6_A			 (0x3ffffL<<0)
2847 #define BNX_RPM_RC_CNTL_6_B			 (0xfffL<<19)
2848 
2849 #define BNX_RPM_RC_VALUE_MASK_6			0x00001934
2850 #define BNX_RPM_RC_CNTL_7			0x00001938
2851 #define BNX_RPM_RC_CNTL_7_A			 (0x3ffffL<<0)
2852 #define BNX_RPM_RC_CNTL_7_B			 (0xfffL<<19)
2853 
2854 #define BNX_RPM_RC_VALUE_MASK_7			0x0000193c
2855 #define BNX_RPM_RC_CNTL_8			0x00001940
2856 #define BNX_RPM_RC_CNTL_8_A			 (0x3ffffL<<0)
2857 #define BNX_RPM_RC_CNTL_8_B			 (0xfffL<<19)
2858 
2859 #define BNX_RPM_RC_VALUE_MASK_8			0x00001944
2860 #define BNX_RPM_RC_CNTL_9			0x00001948
2861 #define BNX_RPM_RC_CNTL_9_A			 (0x3ffffL<<0)
2862 #define BNX_RPM_RC_CNTL_9_B			 (0xfffL<<19)
2863 
2864 #define BNX_RPM_RC_VALUE_MASK_9			0x0000194c
2865 #define BNX_RPM_RC_CNTL_10			0x00001950
2866 #define BNX_RPM_RC_CNTL_10_A			 (0x3ffffL<<0)
2867 #define BNX_RPM_RC_CNTL_10_B			 (0xfffL<<19)
2868 
2869 #define BNX_RPM_RC_VALUE_MASK_10		0x00001954
2870 #define BNX_RPM_RC_CNTL_11			0x00001958
2871 #define BNX_RPM_RC_CNTL_11_A			 (0x3ffffL<<0)
2872 #define BNX_RPM_RC_CNTL_11_B			 (0xfffL<<19)
2873 
2874 #define BNX_RPM_RC_VALUE_MASK_11		0x0000195c
2875 #define BNX_RPM_RC_CNTL_12			0x00001960
2876 #define BNX_RPM_RC_CNTL_12_A			 (0x3ffffL<<0)
2877 #define BNX_RPM_RC_CNTL_12_B			 (0xfffL<<19)
2878 
2879 #define BNX_RPM_RC_VALUE_MASK_12		0x00001964
2880 #define BNX_RPM_RC_CNTL_13			0x00001968
2881 #define BNX_RPM_RC_CNTL_13_A			 (0x3ffffL<<0)
2882 #define BNX_RPM_RC_CNTL_13_B			 (0xfffL<<19)
2883 
2884 #define BNX_RPM_RC_VALUE_MASK_13		0x0000196c
2885 #define BNX_RPM_RC_CNTL_14			0x00001970
2886 #define BNX_RPM_RC_CNTL_14_A			 (0x3ffffL<<0)
2887 #define BNX_RPM_RC_CNTL_14_B			 (0xfffL<<19)
2888 
2889 #define BNX_RPM_RC_VALUE_MASK_14		0x00001974
2890 #define BNX_RPM_RC_CNTL_15			0x00001978
2891 #define BNX_RPM_RC_CNTL_15_A			 (0x3ffffL<<0)
2892 #define BNX_RPM_RC_CNTL_15_B			 (0xfffL<<19)
2893 
2894 #define BNX_RPM_RC_VALUE_MASK_15		0x0000197c
2895 #define BNX_RPM_RC_CONFIG			0x00001980
2896 #define BNX_RPM_RC_CONFIG_RULE_ENABLE		 (0xffffL<<0)
2897 #define BNX_RPM_RC_CONFIG_DEF_CLASS		 (0x7L<<24)
2898 
2899 #define BNX_RPM_DEBUG0				0x00001984
2900 #define BNX_RPM_DEBUG0_FM_BCNT			 (0xffffL<<0)
2901 #define BNX_RPM_DEBUG0_T_DATA_OFST_VLD		 (1L<<16)
2902 #define BNX_RPM_DEBUG0_T_UDP_OFST_VLD		 (1L<<17)
2903 #define BNX_RPM_DEBUG0_T_TCP_OFST_VLD		 (1L<<18)
2904 #define BNX_RPM_DEBUG0_T_IP_OFST_VLD		 (1L<<19)
2905 #define BNX_RPM_DEBUG0_IP_MORE_FRGMT		 (1L<<20)
2906 #define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR	 (1L<<21)
2907 #define BNX_RPM_DEBUG0_LLC_SNAP			 (1L<<22)
2908 #define BNX_RPM_DEBUG0_FM_STARTED		 (1L<<23)
2909 #define BNX_RPM_DEBUG0_DONE			 (1L<<24)
2910 #define BNX_RPM_DEBUG0_WAIT_4_DONE		 (1L<<25)
2911 #define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM		 (1L<<26)
2912 #define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM	 (1L<<27)
2913 #define BNX_RPM_DEBUG0_IGNORE_VLAN		 (1L<<28)
2914 #define BNX_RPM_DEBUG0_RP_ENA_ACTIVE		 (1L<<31)
2915 
2916 #define BNX_RPM_DEBUG1				0x00001988
2917 #define BNX_RPM_DEBUG1_FSM_CUR_ST		 (0xffffL<<0)
2918 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE		 (0L<<0)
2919 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL	 (1L<<0)
2920 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2921 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP	 (4L<<0)
2922 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP	 (8L<<0)
2923 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START	 (16L<<0)
2924 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP		 (32L<<0)
2925 #define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP		 (64L<<0)
2926 #define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP		 (128L<<0)
2927 #define BNX_RPM_DEBUG1_FSM_CUR_ST_AH		 (256L<<0)
2928 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP		 (512L<<0)
2929 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD	 (1024L<<0)
2930 #define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA		 (2048L<<0)
2931 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY	 (0x2000L<<0)
2932 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT	 (0x4000L<<0)
2933 #define BNX_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT	 (0x8000L<<0)
2934 #define BNX_RPM_DEBUG1_HDR_BCNT			 (0x7ffL<<16)
2935 #define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D		 (1L<<28)
2936 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D2		 (1L<<29)
2937 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D1		 (1L<<30)
2938 #define BNX_RPM_DEBUG1_EOF_0XTRA_WD		 (1L<<31)
2939 
2940 #define BNX_RPM_DEBUG2				0x0000198c
2941 #define BNX_RPM_DEBUG2_CMD_HIT_VEC		 (0xffffL<<0)
2942 #define BNX_RPM_DEBUG2_IP_BCNT			 (0xffL<<16)
2943 #define BNX_RPM_DEBUG2_THIS_CMD_M4		 (1L<<24)
2944 #define BNX_RPM_DEBUG2_THIS_CMD_M3		 (1L<<25)
2945 #define BNX_RPM_DEBUG2_THIS_CMD_M2		 (1L<<26)
2946 #define BNX_RPM_DEBUG2_THIS_CMD_M1		 (1L<<27)
2947 #define BNX_RPM_DEBUG2_IPIPE_EMPTY		 (1L<<28)
2948 #define BNX_RPM_DEBUG2_FM_DISCARD		 (1L<<29)
2949 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2	 (1L<<30)
2950 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1	 (1L<<31)
2951 
2952 #define BNX_RPM_DEBUG3				0x00001990
2953 #define BNX_RPM_DEBUG3_AVAIL_MBUF_PTR		 (0x1ffL<<0)
2954 #define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT	 (1L<<9)
2955 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT	 (1L<<10)
2956 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT	 (1L<<11)
2957 #define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ	 (1L<<12)
2958 #define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ	 (1L<<13)
2959 #define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL	 (1L<<14)
2960 #define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP	 (1L<<15)
2961 #define BNX_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT	 (0xfL<<16)
2962 #define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL	 (1L<<21)
2963 #define BNX_RPM_DEBUG3_DROP_NXT_VLD		 (1L<<22)
2964 #define BNX_RPM_DEBUG3_DROP_NXT			 (1L<<23)
2965 #define BNX_RPM_DEBUG3_FTQ_FSM			 (0x3L<<24)
2966 #define BNX_RPM_DEBUG3_FTQ_FSM_IDLE		 (0x0L<<24)
2967 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_ACK		 (0x1L<<24)
2968 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_FREE	 (0x2L<<24)
2969 #define BNX_RPM_DEBUG3_MBWRITE_FSM		 (0x3L<<26)
2970 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF	 (0x0L<<26)
2971 #define BNX_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF	 (0x1L<<26)
2972 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA	 (0x2L<<26)
2973 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA	 (0x3L<<26)
2974 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF	 (0x4L<<26)
2975 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK	 (0x5L<<26)
2976 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD	 (0x6L<<26)
2977 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DONE		 (0x7L<<26)
2978 #define BNX_RPM_DEBUG3_MBFREE_FSM		 (1L<<29)
2979 #define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE		 (0L<<29)
2980 #define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK	 (1L<<29)
2981 #define BNX_RPM_DEBUG3_MBALLOC_FSM		 (1L<<30)
2982 #define BNX_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF	 (0x0L<<30)
2983 #define BNX_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF	 (0x1L<<30)
2984 #define BNX_RPM_DEBUG3_CCODE_EOF_ERROR		 (1L<<31)
2985 
2986 #define BNX_RPM_DEBUG4				0x00001994
2987 #define BNX_RPM_DEBUG4_DFSM_MBUF_CLUSTER	 (0x1ffffffL<<0)
2988 #define BNX_RPM_DEBUG4_DFIFO_CUR_CCODE		 (0x7L<<25)
2989 #define BNX_RPM_DEBUG4_MBWRITE_FSM		 (0x7L<<28)
2990 #define BNX_RPM_DEBUG4_DFIFO_EMPTY		 (1L<<31)
2991 
2992 #define BNX_RPM_DEBUG5				0x00001998
2993 #define BNX_RPM_DEBUG5_RDROP_WPTR		 (0x1fL<<0)
2994 #define BNX_RPM_DEBUG5_RDROP_ACPI_RPTR		 (0x1fL<<5)
2995 #define BNX_RPM_DEBUG5_RDROP_MC_RPTR		 (0x1fL<<10)
2996 #define BNX_RPM_DEBUG5_RDROP_RC_RPTR		 (0x1fL<<15)
2997 #define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY		 (1L<<20)
2998 #define BNX_RPM_DEBUG5_RDROP_MC_EMPTY		 (1L<<21)
2999 #define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR	 (1L<<22)
3000 #define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT	 (1L<<23)
3001 #define BNX_RPM_DEBUG5_HOLDREG_DISCARD		 (1L<<24)
3002 #define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL	 (1L<<25)
3003 #define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY		 (1L<<26)
3004 #define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY		 (1L<<27)
3005 #define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY		 (1L<<28)
3006 #define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY	 (1L<<29)
3007 #define BNX_RPM_DEBUG5_HOLDREG_FULL_T		 (1L<<30)
3008 #define BNX_RPM_DEBUG5_HOLDREG_RD		 (1L<<31)
3009 
3010 #define BNX_RPM_DEBUG6				0x0000199c
3011 #define BNX_RPM_DEBUG6_ACPI_VEC			 (0xffffL<<0)
3012 #define BNX_RPM_DEBUG6_VEC			 (0xffffL<<16)
3013 
3014 #define BNX_RPM_DEBUG7				0x000019a0
3015 #define BNX_RPM_DEBUG7_RPM_DBG7_LAST_CRC	 (0xffffffffL<<0)
3016 
3017 #define BNX_RPM_DEBUG8				0x000019a4
3018 #define BNX_RPM_DEBUG8_PS_ACPI_FSM		 (0xfL<<0)
3019 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE		 (0L<<0)
3020 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR	 (1L<<0)
3021 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR	 (2L<<0)
3022 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR	 (3L<<0)
3023 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF	 (4L<<0)
3024 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA	 (5L<<0)
3025 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR	 (6L<<0)
3026 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR	 (7L<<0)
3027 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR	 (8L<<0)
3028 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR	 (9L<<0)
3029 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF	 (10L<<0)
3030 #define BNX_RPM_DEBUG8_COMPARE_AT_W0		 (1L<<4)
3031 #define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA	 (1L<<5)
3032 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT	 (1L<<6)
3033 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3	 (1L<<7)
3034 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2	 (1L<<8)
3035 #define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES	 (1L<<9)
3036 #define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES	 (1L<<10)
3037 #define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES	 (1L<<11)
3038 #define BNX_RPM_DEBUG8_EOF_DET			 (1L<<12)
3039 #define BNX_RPM_DEBUG8_SOF_DET			 (1L<<13)
3040 #define BNX_RPM_DEBUG8_WAIT_4_SOF		 (1L<<14)
3041 #define BNX_RPM_DEBUG8_ALL_DONE			 (1L<<15)
3042 #define BNX_RPM_DEBUG8_THBUF_ADDR		 (0x7fL<<16)
3043 #define BNX_RPM_DEBUG8_BYTE_CTR			 (0xffL<<24)
3044 
3045 #define BNX_RPM_DEBUG9				0x000019a8
3046 #define BNX_RPM_DEBUG9_OUTFIFO_COUNT		 (0x7L<<0)
3047 #define BNX_RPM_DEBUG9_RDE_ACPI_RDY		 (1L<<3)
3048 #define BNX_RPM_DEBUG9_VLD_RD_ENTRY_CT		 (0x7L<<4)
3049 #define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED	 (1L<<28)
3050 #define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED	 (1L<<29)
3051 #define BNX_RPM_DEBUG9_ACPI_MATCH_INT		 (1L<<30)
3052 #define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN		 (1L<<31)
3053 
3054 #define BNX_RPM_ACPI_DBG_BUF_W00		0x000019c0
3055 #define BNX_RPM_ACPI_DBG_BUF_W01		0x000019c4
3056 #define BNX_RPM_ACPI_DBG_BUF_W02		0x000019c8
3057 #define BNX_RPM_ACPI_DBG_BUF_W03		0x000019cc
3058 #define BNX_RPM_ACPI_DBG_BUF_W10		0x000019d0
3059 #define BNX_RPM_ACPI_DBG_BUF_W11		0x000019d4
3060 #define BNX_RPM_ACPI_DBG_BUF_W12		0x000019d8
3061 #define BNX_RPM_ACPI_DBG_BUF_W13		0x000019dc
3062 #define BNX_RPM_ACPI_DBG_BUF_W20		0x000019e0
3063 #define BNX_RPM_ACPI_DBG_BUF_W21		0x000019e4
3064 #define BNX_RPM_ACPI_DBG_BUF_W22		0x000019e8
3065 #define BNX_RPM_ACPI_DBG_BUF_W23		0x000019ec
3066 #define BNX_RPM_ACPI_DBG_BUF_W30		0x000019f0
3067 #define BNX_RPM_ACPI_DBG_BUF_W31		0x000019f4
3068 #define BNX_RPM_ACPI_DBG_BUF_W32		0x000019f8
3069 #define BNX_RPM_ACPI_DBG_BUF_W33		0x000019fc
3070 
3071 
3072 /*
3073  *  rbuf_reg definition
3074  *  offset: 0x200000
3075  */
3076 #define BNX_RBUF_COMMAND			0x00200000
3077 #define BNX_RBUF_COMMAND_ENABLED		 (1L<<0)
3078 #define BNX_RBUF_COMMAND_FREE_INIT		 (1L<<1)
3079 #define BNX_RBUF_COMMAND_RAM_INIT		 (1L<<2)
3080 #define BNX_RBUF_COMMAND_OVER_FREE		 (1L<<4)
3081 #define BNX_RBUF_COMMAND_ALLOC_REQ		 (1L<<5)
3082 
3083 #define BNX_RBUF_STATUS1			0x00200004
3084 #define BNX_RBUF_STATUS1_FREE_COUNT		 (0x3ffL<<0)
3085 
3086 #define BNX_RBUF_STATUS2			0x00200008
3087 #define BNX_RBUF_STATUS2_FREE_TAIL		 (0x3ffL<<0)
3088 #define BNX_RBUF_STATUS2_FREE_HEAD		 (0x3ffL<<16)
3089 
3090 #define BNX_RBUF_CONFIG				0x0020000c
3091 #define BNX_RBUF_CONFIG_XOFF_TRIP		 (0x3ffL<<0)
3092 #define BNX_RBUF_CONFIG_XON_TRIP		 (0x3ffL<<16)
3093 
3094 #define BNX_RBUF_FW_BUF_ALLOC			0x00200010
3095 #define BNX_RBUF_FW_BUF_ALLOC_VALUE		 (0x1ffL<<7)
3096 
3097 #define BNX_RBUF_FW_BUF_FREE			0x00200014
3098 #define BNX_RBUF_FW_BUF_FREE_COUNT		 (0x7fL<<0)
3099 #define BNX_RBUF_FW_BUF_FREE_TAIL		 (0x1ffL<<7)
3100 #define BNX_RBUF_FW_BUF_FREE_HEAD		 (0x1ffL<<16)
3101 
3102 #define BNX_RBUF_FW_BUF_SEL			0x00200018
3103 #define BNX_RBUF_FW_BUF_SEL_COUNT		 (0x7fL<<0)
3104 #define BNX_RBUF_FW_BUF_SEL_TAIL		 (0x1ffL<<7)
3105 #define BNX_RBUF_FW_BUF_SEL_HEAD		 (0x1ffL<<16)
3106 
3107 #define BNX_RBUF_CONFIG2			0x0020001c
3108 #define BNX_RBUF_CONFIG2_MAC_DROP_TRIP		 (0x3ffL<<0)
3109 #define BNX_RBUF_CONFIG2_MAC_KEEP_TRIP		 (0x3ffL<<16)
3110 
3111 #define BNX_RBUF_CONFIG3			0x00200020
3112 #define BNX_RBUF_CONFIG3_CU_DROP_TRIP		 (0x3ffL<<0)
3113 #define BNX_RBUF_CONFIG3_CU_KEEP_TRIP		 (0x3ffL<<16)
3114 
3115 #define BNX_RBUF_PKT_DATA			0x00208000
3116 #define BNX_RBUF_CLIST_DATA			0x00210000
3117 #define BNX_RBUF_BUF_DATA			0x00220000
3118 
3119 
3120 /*
3121  *  rv2p_reg definition
3122  *  offset: 0x2800
3123  */
3124 #define BNX_RV2P_COMMAND			0x00002800
3125 #define BNX_RV2P_COMMAND_ENABLED		 (1L<<0)
3126 #define BNX_RV2P_COMMAND_PROC1_INTRPT		 (1L<<1)
3127 #define BNX_RV2P_COMMAND_PROC2_INTRPT		 (1L<<2)
3128 #define BNX_RV2P_COMMAND_ABORT0			 (1L<<4)
3129 #define BNX_RV2P_COMMAND_ABORT1			 (1L<<5)
3130 #define BNX_RV2P_COMMAND_ABORT2			 (1L<<6)
3131 #define BNX_RV2P_COMMAND_ABORT3			 (1L<<7)
3132 #define BNX_RV2P_COMMAND_ABORT4			 (1L<<8)
3133 #define BNX_RV2P_COMMAND_ABORT5			 (1L<<9)
3134 #define BNX_RV2P_COMMAND_PROC1_RESET		 (1L<<16)
3135 #define BNX_RV2P_COMMAND_PROC2_RESET		 (1L<<17)
3136 #define BNX_RV2P_COMMAND_CTXIF_RESET		 (1L<<18)
3137 
3138 #define BNX_RV2P_STATUS				0x00002804
3139 #define BNX_RV2P_STATUS_ALWAYS_0		 (1L<<0)
3140 #define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT	 (1L<<8)
3141 #define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT	 (1L<<9)
3142 #define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT	 (1L<<10)
3143 #define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT	 (1L<<11)
3144 #define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT	 (1L<<12)
3145 #define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT	 (1L<<13)
3146 
3147 #define BNX_RV2P_CONFIG				0x00002808
3148 #define BNX_RV2P_CONFIG_STALL_PROC1		 (1L<<0)
3149 #define BNX_RV2P_CONFIG_STALL_PROC2		 (1L<<1)
3150 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0	 (1L<<8)
3151 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1	 (1L<<9)
3152 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2	 (1L<<10)
3153 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3	 (1L<<11)
3154 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4	 (1L<<12)
3155 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5	 (1L<<13)
3156 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0	 (1L<<16)
3157 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1	 (1L<<17)
3158 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2	 (1L<<18)
3159 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3	 (1L<<19)
3160 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4	 (1L<<20)
3161 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5	 (1L<<21)
3162 #define BNX_RV2P_CONFIG_PAGE_SIZE		 (0xfL<<24)
3163 #define BNX_RV2P_CONFIG_PAGE_SIZE_256		 (0L<<24)
3164 #define BNX_RV2P_CONFIG_PAGE_SIZE_512		 (1L<<24)
3165 #define BNX_RV2P_CONFIG_PAGE_SIZE_1K		 (2L<<24)
3166 #define BNX_RV2P_CONFIG_PAGE_SIZE_2K		 (3L<<24)
3167 #define BNX_RV2P_CONFIG_PAGE_SIZE_4K		 (4L<<24)
3168 #define BNX_RV2P_CONFIG_PAGE_SIZE_8K		 (5L<<24)
3169 #define BNX_RV2P_CONFIG_PAGE_SIZE_16K		 (6L<<24)
3170 #define BNX_RV2P_CONFIG_PAGE_SIZE_32K		 (7L<<24)
3171 #define BNX_RV2P_CONFIG_PAGE_SIZE_64K		 (8L<<24)
3172 #define BNX_RV2P_CONFIG_PAGE_SIZE_128K		 (9L<<24)
3173 #define BNX_RV2P_CONFIG_PAGE_SIZE_256K		 (10L<<24)
3174 #define BNX_RV2P_CONFIG_PAGE_SIZE_512K		 (11L<<24)
3175 #define BNX_RV2P_CONFIG_PAGE_SIZE_1M		 (12L<<24)
3176 
3177 #define BNX_RV2P_GEN_BFR_ADDR_0			0x00002810
3178 #define BNX_RV2P_GEN_BFR_ADDR_0_VALUE		 (0xffffL<<16)
3179 
3180 #define BNX_RV2P_GEN_BFR_ADDR_1			0x00002814
3181 #define BNX_RV2P_GEN_BFR_ADDR_1_VALUE		 (0xffffL<<16)
3182 
3183 #define BNX_RV2P_GEN_BFR_ADDR_2			0x00002818
3184 #define BNX_RV2P_GEN_BFR_ADDR_2_VALUE		 (0xffffL<<16)
3185 
3186 #define BNX_RV2P_GEN_BFR_ADDR_3			0x0000281c
3187 #define BNX_RV2P_GEN_BFR_ADDR_3_VALUE		 (0xffffL<<16)
3188 
3189 #define BNX_RV2P_INSTR_HIGH			0x00002830
3190 #define BNX_RV2P_INSTR_HIGH_HIGH		 (0x1fL<<0)
3191 
3192 #define BNX_RV2P_INSTR_LOW			0x00002834
3193 #define BNX_RV2P_PROC1_ADDR_CMD			0x00002838
3194 #define BNX_RV2P_PROC1_ADDR_CMD_ADD		 (0x3ffL<<0)
3195 #define BNX_RV2P_PROC1_ADDR_CMD_RDWR		 (1L<<31)
3196 
3197 #define BNX_RV2P_PROC2_ADDR_CMD			0x0000283c
3198 #define BNX_RV2P_PROC2_ADDR_CMD_ADD		 (0x3ffL<<0)
3199 #define BNX_RV2P_PROC2_ADDR_CMD_RDWR		 (1L<<31)
3200 
3201 #define BNX_RV2P_PROC1_GRC_DEBUG		0x00002840
3202 #define BNX_RV2P_PROC2_GRC_DEBUG		0x00002844
3203 #define BNX_RV2P_GRC_PROC_DEBUG			0x00002848
3204 #define BNX_RV2P_DEBUG_VECT_PEEK		0x0000284c
3205 #define BNX_RV2P_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
3206 #define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
3207 #define BNX_RV2P_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
3208 #define BNX_RV2P_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
3209 #define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
3210 #define BNX_RV2P_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
3211 
3212 #define BNX_RV2P_PFTQ_DATA			0x00002b40
3213 #define BNX_RV2P_PFTQ_CMD			0x00002b78
3214 #define BNX_RV2P_PFTQ_CMD_OFFSET		 (0x3ffL<<0)
3215 #define BNX_RV2P_PFTQ_CMD_WR_TOP		 (1L<<10)
3216 #define BNX_RV2P_PFTQ_CMD_WR_TOP_0		 (0L<<10)
3217 #define BNX_RV2P_PFTQ_CMD_WR_TOP_1		 (1L<<10)
3218 #define BNX_RV2P_PFTQ_CMD_SFT_RESET		 (1L<<25)
3219 #define BNX_RV2P_PFTQ_CMD_RD_DATA		 (1L<<26)
3220 #define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN		 (1L<<27)
3221 #define BNX_RV2P_PFTQ_CMD_ADD_DATA		 (1L<<28)
3222 #define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3223 #define BNX_RV2P_PFTQ_CMD_POP			 (1L<<30)
3224 #define BNX_RV2P_PFTQ_CMD_BUSY			 (1L<<31)
3225 
3226 #define BNX_RV2P_PFTQ_CTL			0x00002b7c
3227 #define BNX_RV2P_PFTQ_CTL_INTERVENE		 (1L<<0)
3228 #define BNX_RV2P_PFTQ_CTL_OVERFLOW		 (1L<<1)
3229 #define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE	 (1L<<2)
3230 #define BNX_RV2P_PFTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
3231 #define BNX_RV2P_PFTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
3232 
3233 #define BNX_RV2P_TFTQ_DATA			0x00002b80
3234 #define BNX_RV2P_TFTQ_CMD			0x00002bb8
3235 #define BNX_RV2P_TFTQ_CMD_OFFSET		 (0x3ffL<<0)
3236 #define BNX_RV2P_TFTQ_CMD_WR_TOP		 (1L<<10)
3237 #define BNX_RV2P_TFTQ_CMD_WR_TOP_0		 (0L<<10)
3238 #define BNX_RV2P_TFTQ_CMD_WR_TOP_1		 (1L<<10)
3239 #define BNX_RV2P_TFTQ_CMD_SFT_RESET		 (1L<<25)
3240 #define BNX_RV2P_TFTQ_CMD_RD_DATA		 (1L<<26)
3241 #define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN		 (1L<<27)
3242 #define BNX_RV2P_TFTQ_CMD_ADD_DATA		 (1L<<28)
3243 #define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3244 #define BNX_RV2P_TFTQ_CMD_POP			 (1L<<30)
3245 #define BNX_RV2P_TFTQ_CMD_BUSY			 (1L<<31)
3246 
3247 #define BNX_RV2P_TFTQ_CTL			0x00002bbc
3248 #define BNX_RV2P_TFTQ_CTL_INTERVENE		 (1L<<0)
3249 #define BNX_RV2P_TFTQ_CTL_OVERFLOW		 (1L<<1)
3250 #define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE	 (1L<<2)
3251 #define BNX_RV2P_TFTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
3252 #define BNX_RV2P_TFTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
3253 
3254 #define BNX_RV2P_MFTQ_DATA			0x00002bc0
3255 #define BNX_RV2P_MFTQ_CMD			0x00002bf8
3256 #define BNX_RV2P_MFTQ_CMD_OFFSET		 (0x3ffL<<0)
3257 #define BNX_RV2P_MFTQ_CMD_WR_TOP		 (1L<<10)
3258 #define BNX_RV2P_MFTQ_CMD_WR_TOP_0		 (0L<<10)
3259 #define BNX_RV2P_MFTQ_CMD_WR_TOP_1		 (1L<<10)
3260 #define BNX_RV2P_MFTQ_CMD_SFT_RESET		 (1L<<25)
3261 #define BNX_RV2P_MFTQ_CMD_RD_DATA		 (1L<<26)
3262 #define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN		 (1L<<27)
3263 #define BNX_RV2P_MFTQ_CMD_ADD_DATA		 (1L<<28)
3264 #define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3265 #define BNX_RV2P_MFTQ_CMD_POP			 (1L<<30)
3266 #define BNX_RV2P_MFTQ_CMD_BUSY			 (1L<<31)
3267 
3268 #define BNX_RV2P_MFTQ_CTL			0x00002bfc
3269 #define BNX_RV2P_MFTQ_CTL_INTERVENE		 (1L<<0)
3270 #define BNX_RV2P_MFTQ_CTL_OVERFLOW		 (1L<<1)
3271 #define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE	 (1L<<2)
3272 #define BNX_RV2P_MFTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
3273 #define BNX_RV2P_MFTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
3274 
3275 
3276 /*
3277  *  mq_reg definition
3278  *  offset: 0x3c00
3279  */
3280 #define BNX_MQ_COMMAND				0x00003c00
3281 #define BNX_MQ_COMMAND_ENABLED			 (1L<<0)
3282 #define BNX_MQ_COMMAND_OVERFLOW			 (1L<<4)
3283 #define BNX_MQ_COMMAND_WR_ERROR			 (1L<<5)
3284 #define BNX_MQ_COMMAND_RD_ERROR			 (1L<<6)
3285 
3286 #define BNX_MQ_STATUS				0x00003c04
3287 #define BNX_MQ_STATUS_CTX_ACCESS_STAT		 (1L<<16)
3288 #define BNX_MQ_STATUS_CTX_ACCESS64_STAT		 (1L<<17)
3289 #define BNX_MQ_STATUS_PCI_STALL_STAT		 (1L<<18)
3290 
3291 #define BNX_MQ_CONFIG				0x00003c08
3292 #define BNX_MQ_CONFIG_TX_HIGH_PRI		 (1L<<0)
3293 #define BNX_MQ_CONFIG_HALT_DIS			 (1L<<1)
3294 #define BNX_MQ_CONFIG_BIN_MQ_MODE		 (1L<<2)
3295 #define BNX_MQ_CONFIG_DIS_IDB_DROP		 (1L<<3)
3296 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE		 (0x7L<<4)
3297 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256	 (0L<<4)
3298 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512	 (1L<<4)
3299 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K	 (2L<<4)
3300 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K	 (3L<<4)
3301 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K	 (4L<<4)
3302 #define BNX_MQ_CONFIG_MAX_DEPTH			 (0x7fL<<8)
3303 #define BNX_MQ_CONFIG_CUR_DEPTH			 (0x7fL<<20)
3304 
3305 #define BNX_MQ_ENQUEUE1				0x00003c0c
3306 #define BNX_MQ_ENQUEUE1_OFFSET			 (0x3fL<<2)
3307 #define BNX_MQ_ENQUEUE1_CID			 (0x3fffL<<8)
3308 #define BNX_MQ_ENQUEUE1_BYTE_MASK		 (0xfL<<24)
3309 #define BNX_MQ_ENQUEUE1_KNL_MODE		 (1L<<28)
3310 
3311 #define BNX_MQ_ENQUEUE2				0x00003c10
3312 #define BNX_MQ_BAD_WR_ADDR			0x00003c14
3313 #define BNX_MQ_BAD_RD_ADDR			0x00003c18
3314 #define BNX_MQ_KNL_BYP_WIND_START		0x00003c1c
3315 #define BNX_MQ_KNL_BYP_WIND_START_VALUE		 (0xfffffL<<12)
3316 
3317 #define BNX_MQ_KNL_WIND_END			0x00003c20
3318 #define BNX_MQ_KNL_WIND_END_VALUE		 (0xffffffL<<8)
3319 
3320 #define BNX_MQ_KNL_WRITE_MASK1			0x00003c24
3321 #define BNX_MQ_KNL_TX_MASK1			0x00003c28
3322 #define BNX_MQ_KNL_CMD_MASK1			0x00003c2c
3323 #define BNX_MQ_KNL_COND_ENQUEUE_MASK1		0x00003c30
3324 #define BNX_MQ_KNL_RX_V2P_MASK1			0x00003c34
3325 #define BNX_MQ_KNL_WRITE_MASK2			0x00003c38
3326 #define BNX_MQ_KNL_TX_MASK2			0x00003c3c
3327 #define BNX_MQ_KNL_CMD_MASK2			0x00003c40
3328 #define BNX_MQ_KNL_COND_ENQUEUE_MASK2		0x00003c44
3329 #define BNX_MQ_KNL_RX_V2P_MASK2			0x00003c48
3330 #define BNX_MQ_KNL_BYP_WRITE_MASK1		0x00003c4c
3331 #define BNX_MQ_KNL_BYP_TX_MASK1			0x00003c50
3332 #define BNX_MQ_KNL_BYP_CMD_MASK1		0x00003c54
3333 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK1	0x00003c58
3334 #define BNX_MQ_KNL_BYP_RX_V2P_MASK1		0x00003c5c
3335 #define BNX_MQ_KNL_BYP_WRITE_MASK2		0x00003c60
3336 #define BNX_MQ_KNL_BYP_TX_MASK2			0x00003c64
3337 #define BNX_MQ_KNL_BYP_CMD_MASK2		0x00003c68
3338 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK2	0x00003c6c
3339 #define BNX_MQ_KNL_BYP_RX_V2P_MASK2		0x00003c70
3340 #define BNX_MQ_MEM_WR_ADDR			0x00003c74
3341 #define BNX_MQ_MEM_WR_ADDR_VALUE		 (0x3fL<<0)
3342 
3343 #define BNX_MQ_MEM_WR_DATA0			0x00003c78
3344 #define BNX_MQ_MEM_WR_DATA0_VALUE		 (0xffffffffL<<0)
3345 
3346 #define BNX_MQ_MEM_WR_DATA1			0x00003c7c
3347 #define BNX_MQ_MEM_WR_DATA1_VALUE		 (0xffffffffL<<0)
3348 
3349 #define BNX_MQ_MEM_WR_DATA2			0x00003c80
3350 #define BNX_MQ_MEM_WR_DATA2_VALUE		 (0x3fffffffL<<0)
3351 
3352 #define BNX_MQ_MEM_RD_ADDR			0x00003c84
3353 #define BNX_MQ_MEM_RD_ADDR_VALUE		 (0x3fL<<0)
3354 
3355 #define BNX_MQ_MEM_RD_DATA0			0x00003c88
3356 #define BNX_MQ_MEM_RD_DATA0_VALUE		 (0xffffffffL<<0)
3357 
3358 #define BNX_MQ_MEM_RD_DATA1			0x00003c8c
3359 #define BNX_MQ_MEM_RD_DATA1_VALUE		 (0xffffffffL<<0)
3360 
3361 #define BNX_MQ_MEM_RD_DATA2			0x00003c90
3362 #define BNX_MQ_MEM_RD_DATA2_VALUE		 (0x3fffffffL<<0)
3363 
3364 #define BNX_MQ_MAP_L2_5				0x00003d34
3365 #define BNX_MQ_MAP_L2_5_MQ_OFFSET		 (0xffL<<0)
3366 #define BNX_MQ_MAP_L2_5_SZ			 (0x3L<<8)
3367 #define BNX_MQ_MAP_L2_5_CTX_OFFSET		 (0x2ffL<<10)
3368 #define BNX_MQ_MAP_L2_5_BIN_OFFSET		 (0x7L<<23)
3369 #define BNX_MQ_MAP_L2_5_ARM			 (0x3L<<26)
3370 #define BNX_MQ_MAP_L2_5_ENA			 (0x1L<<31)
3371 #define BNX_MQ_MAP_L2_5_DEFAULT			0x83000b08
3372 
3373 
3374 /*
3375  *  tbdr_reg definition
3376  *  offset: 0x5000
3377  */
3378 #define BNX_TBDR_COMMAND			0x00005000
3379 #define BNX_TBDR_COMMAND_ENABLE			 (1L<<0)
3380 #define BNX_TBDR_COMMAND_SOFT_RST		 (1L<<1)
3381 #define BNX_TBDR_COMMAND_MSTR_ABORT		 (1L<<4)
3382 
3383 #define BNX_TBDR_STATUS				0x00005004
3384 #define BNX_TBDR_STATUS_DMA_WAIT		 (1L<<0)
3385 #define BNX_TBDR_STATUS_FTQ_WAIT		 (1L<<1)
3386 #define BNX_TBDR_STATUS_FIFO_OVERFLOW		 (1L<<2)
3387 #define BNX_TBDR_STATUS_FIFO_UNDERFLOW		 (1L<<3)
3388 #define BNX_TBDR_STATUS_SEARCHMISS_ERROR	 (1L<<4)
3389 #define BNX_TBDR_STATUS_FTQ_ENTRY_CNT		 (1L<<5)
3390 #define BNX_TBDR_STATUS_BURST_CNT		 (1L<<6)
3391 
3392 #define BNX_TBDR_CONFIG				0x00005008
3393 #define BNX_TBDR_CONFIG_MAX_BDS			 (0xffL<<0)
3394 #define BNX_TBDR_CONFIG_SWAP_MODE		 (1L<<8)
3395 #define BNX_TBDR_CONFIG_PRIORITY		 (1L<<9)
3396 #define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS	 (1L<<10)
3397 #define BNX_TBDR_CONFIG_PAGE_SIZE		 (0xfL<<24)
3398 #define BNX_TBDR_CONFIG_PAGE_SIZE_256		 (0L<<24)
3399 #define BNX_TBDR_CONFIG_PAGE_SIZE_512		 (1L<<24)
3400 #define BNX_TBDR_CONFIG_PAGE_SIZE_1K		 (2L<<24)
3401 #define BNX_TBDR_CONFIG_PAGE_SIZE_2K		 (3L<<24)
3402 #define BNX_TBDR_CONFIG_PAGE_SIZE_4K		 (4L<<24)
3403 #define BNX_TBDR_CONFIG_PAGE_SIZE_8K		 (5L<<24)
3404 #define BNX_TBDR_CONFIG_PAGE_SIZE_16K		 (6L<<24)
3405 #define BNX_TBDR_CONFIG_PAGE_SIZE_32K		 (7L<<24)
3406 #define BNX_TBDR_CONFIG_PAGE_SIZE_64K		 (8L<<24)
3407 #define BNX_TBDR_CONFIG_PAGE_SIZE_128K		 (9L<<24)
3408 #define BNX_TBDR_CONFIG_PAGE_SIZE_256K		 (10L<<24)
3409 #define BNX_TBDR_CONFIG_PAGE_SIZE_512K		 (11L<<24)
3410 #define BNX_TBDR_CONFIG_PAGE_SIZE_1M		 (12L<<24)
3411 
3412 #define BNX_TBDR_DEBUG_VECT_PEEK		0x0000500c
3413 #define BNX_TBDR_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
3414 #define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
3415 #define BNX_TBDR_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
3416 #define BNX_TBDR_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
3417 #define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
3418 #define BNX_TBDR_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
3419 
3420 #define BNX_TBDR_FTQ_DATA			0x000053c0
3421 #define BNX_TBDR_FTQ_CMD			0x000053f8
3422 #define BNX_TBDR_FTQ_CMD_OFFSET			 (0x3ffL<<0)
3423 #define BNX_TBDR_FTQ_CMD_WR_TOP			 (1L<<10)
3424 #define BNX_TBDR_FTQ_CMD_WR_TOP_0		 (0L<<10)
3425 #define BNX_TBDR_FTQ_CMD_WR_TOP_1		 (1L<<10)
3426 #define BNX_TBDR_FTQ_CMD_SFT_RESET		 (1L<<25)
3427 #define BNX_TBDR_FTQ_CMD_RD_DATA		 (1L<<26)
3428 #define BNX_TBDR_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
3429 #define BNX_TBDR_FTQ_CMD_ADD_DATA		 (1L<<28)
3430 #define BNX_TBDR_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
3431 #define BNX_TBDR_FTQ_CMD_POP			 (1L<<30)
3432 #define BNX_TBDR_FTQ_CMD_BUSY			 (1L<<31)
3433 
3434 #define BNX_TBDR_FTQ_CTL			0x000053fc
3435 #define BNX_TBDR_FTQ_CTL_INTERVENE		 (1L<<0)
3436 #define BNX_TBDR_FTQ_CTL_OVERFLOW		 (1L<<1)
3437 #define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
3438 #define BNX_TBDR_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
3439 #define BNX_TBDR_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
3440 
3441 
3442 /*
3443  *  tdma_reg definition
3444  *  offset: 0x5c00
3445  */
3446 #define BNX_TDMA_COMMAND			0x00005c00
3447 #define BNX_TDMA_COMMAND_ENABLED		 (1L<<0)
3448 #define BNX_TDMA_COMMAND_MASTER_ABORT		 (1L<<4)
3449 #define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT	 (1L<<7)
3450 
3451 #define BNX_TDMA_STATUS				0x00005c04
3452 #define BNX_TDMA_STATUS_DMA_WAIT		 (1L<<0)
3453 #define BNX_TDMA_STATUS_PAYLOAD_WAIT		 (1L<<1)
3454 #define BNX_TDMA_STATUS_PATCH_FTQ_WAIT		 (1L<<2)
3455 #define BNX_TDMA_STATUS_LOCK_WAIT		 (1L<<3)
3456 #define BNX_TDMA_STATUS_FTQ_ENTRY_CNT		 (1L<<16)
3457 #define BNX_TDMA_STATUS_BURST_CNT		 (1L<<17)
3458 
3459 #define BNX_TDMA_CONFIG				0x00005c08
3460 #define BNX_TDMA_CONFIG_ONE_DMA			 (1L<<0)
3461 #define BNX_TDMA_CONFIG_ONE_RECORD		 (1L<<1)
3462 #define BNX_TDMA_CONFIG_LIMIT_SZ		 (0xfL<<4)
3463 #define BNX_TDMA_CONFIG_LIMIT_SZ_64		 (0L<<4)
3464 #define BNX_TDMA_CONFIG_LIMIT_SZ_128		 (0x4L<<4)
3465 #define BNX_TDMA_CONFIG_LIMIT_SZ_256		 (0x6L<<4)
3466 #define BNX_TDMA_CONFIG_LIMIT_SZ_512		 (0x8L<<4)
3467 #define BNX_TDMA_CONFIG_LINE_SZ			 (0xfL<<8)
3468 #define BNX_TDMA_CONFIG_LINE_SZ_64		 (0L<<8)
3469 #define BNX_TDMA_CONFIG_LINE_SZ_128		 (4L<<8)
3470 #define BNX_TDMA_CONFIG_LINE_SZ_256		 (6L<<8)
3471 #define BNX_TDMA_CONFIG_LINE_SZ_512		 (8L<<8)
3472 #define BNX_TDMA_CONFIG_ALIGN_ENA		 (1L<<15)
3473 #define BNX_TDMA_CONFIG_CHK_L2_BD		 (1L<<16)
3474 #define BNX_TDMA_CONFIG_FIFO_CMP		 (0xfL<<20)
3475 
3476 #define BNX_TDMA_PAYLOAD_PROD			0x00005c0c
3477 #define BNX_TDMA_PAYLOAD_PROD_VALUE		 (0x1fffL<<3)
3478 
3479 #define BNX_TDMA_DBG_WATCHDOG			0x00005c10
3480 #define BNX_TDMA_DBG_TRIGGER			0x00005c14
3481 #define BNX_TDMA_DMAD_FSM			0x00005c80
3482 #define BNX_TDMA_DMAD_FSM_BD_INVLD		 (1L<<0)
3483 #define BNX_TDMA_DMAD_FSM_PUSH			 (0xfL<<4)
3484 #define BNX_TDMA_DMAD_FSM_ARB_TBDC		 (0x3L<<8)
3485 #define BNX_TDMA_DMAD_FSM_ARB_CTX		 (1L<<12)
3486 #define BNX_TDMA_DMAD_FSM_DR_INTF		 (1L<<16)
3487 #define BNX_TDMA_DMAD_FSM_DMAD			 (0x7L<<20)
3488 #define BNX_TDMA_DMAD_FSM_BD			 (0xfL<<24)
3489 
3490 #define BNX_TDMA_DMAD_STATUS			0x00005c84
3491 #define BNX_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY	 (0x3L<<0)
3492 #define BNX_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY	 (0x3L<<4)
3493 #define BNX_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY	 (0x3L<<8)
3494 #define BNX_TDMA_DMAD_STATUS_IFTQ_ENUM		 (0xfL<<12)
3495 
3496 #define BNX_TDMA_DR_INTF_FSM			0x00005c88
3497 #define BNX_TDMA_DR_INTF_FSM_L2_COMP		 (0x3L<<0)
3498 #define BNX_TDMA_DR_INTF_FSM_TPATQ		 (0x7L<<4)
3499 #define BNX_TDMA_DR_INTF_FSM_TPBUF		 (0x3L<<8)
3500 #define BNX_TDMA_DR_INTF_FSM_DR_BUF		 (0x7L<<12)
3501 #define BNX_TDMA_DR_INTF_FSM_DMAD		 (0x7L<<16)
3502 
3503 #define BNX_TDMA_DR_INTF_STATUS			0x00005c8c
3504 #define BNX_TDMA_DR_INTF_STATUS_HOLE_PHASE	 (0x7L<<0)
3505 #define BNX_TDMA_DR_INTF_STATUS_DATA_AVAIL	 (0x3L<<4)
3506 #define BNX_TDMA_DR_INTF_STATUS_SHIFT_ADDR	 (0x7L<<8)
3507 #define BNX_TDMA_DR_INTF_STATUS_NXT_PNTR	 (0xfL<<12)
3508 #define BNX_TDMA_DR_INTF_STATUS_BYTE_COUNT	 (0x7L<<16)
3509 
3510 #define BNX_TDMA_FTQ_DATA			0x00005fc0
3511 #define BNX_TDMA_FTQ_CMD			0x00005ff8
3512 #define BNX_TDMA_FTQ_CMD_OFFSET			 (0x3ffL<<0)
3513 #define BNX_TDMA_FTQ_CMD_WR_TOP			 (1L<<10)
3514 #define BNX_TDMA_FTQ_CMD_WR_TOP_0		 (0L<<10)
3515 #define BNX_TDMA_FTQ_CMD_WR_TOP_1		 (1L<<10)
3516 #define BNX_TDMA_FTQ_CMD_SFT_RESET		 (1L<<25)
3517 #define BNX_TDMA_FTQ_CMD_RD_DATA		 (1L<<26)
3518 #define BNX_TDMA_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
3519 #define BNX_TDMA_FTQ_CMD_ADD_DATA		 (1L<<28)
3520 #define BNX_TDMA_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
3521 #define BNX_TDMA_FTQ_CMD_POP			 (1L<<30)
3522 #define BNX_TDMA_FTQ_CMD_BUSY			 (1L<<31)
3523 
3524 #define BNX_TDMA_FTQ_CTL			0x00005ffc
3525 #define BNX_TDMA_FTQ_CTL_INTERVENE		 (1L<<0)
3526 #define BNX_TDMA_FTQ_CTL_OVERFLOW		 (1L<<1)
3527 #define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
3528 #define BNX_TDMA_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
3529 #define BNX_TDMA_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
3530 
3531 
3532 /*
3533  *  hc_reg definition
3534  *  offset: 0x6800
3535  */
3536 #define BNX_HC_COMMAND				0x00006800
3537 #define BNX_HC_COMMAND_ENABLE			 (1L<<0)
3538 #define BNX_HC_COMMAND_SKIP_ABORT		 (1L<<4)
3539 #define BNX_HC_COMMAND_COAL_NOW			 (1L<<16)
3540 #define BNX_HC_COMMAND_COAL_NOW_WO_INT		 (1L<<17)
3541 #define BNX_HC_COMMAND_STATS_NOW		 (1L<<18)
3542 #define BNX_HC_COMMAND_FORCE_INT		 (0x3L<<19)
3543 #define BNX_HC_COMMAND_FORCE_INT_NULL		 (0L<<19)
3544 #define BNX_HC_COMMAND_FORCE_INT_HIGH		 (1L<<19)
3545 #define BNX_HC_COMMAND_FORCE_INT_LOW		 (2L<<19)
3546 #define BNX_HC_COMMAND_FORCE_INT_FREE		 (3L<<19)
3547 #define BNX_HC_COMMAND_CLR_STAT_NOW		 (1L<<21)
3548 
3549 #define BNX_HC_STATUS					0x00006804
3550 #define BNX_HC_STATUS_MASTER_ABORT			 (1L<<0)
3551 #define BNX_HC_STATUS_PARITY_ERROR_STATE		 (1L<<1)
3552 #define BNX_HC_STATUS_PCI_CLK_CNT_STAT			 (1L<<16)
3553 #define BNX_HC_STATUS_CORE_CLK_CNT_STAT			 (1L<<17)
3554 #define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT		 (1L<<18)
3555 #define BNX_HC_STATUS_NUM_INT_GEN_STAT			 (1L<<19)
3556 #define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT		 (1L<<20)
3557 #define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT	 (1L<<23)
3558 #define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT	 (1L<<24)
3559 #define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT	 (1L<<25)
3560 
3561 #define BNX_HC_CONFIG				0x00006808
3562 #define BNX_HC_CONFIG_COLLECT_STATS		 (1L<<0)
3563 #define BNX_HC_CONFIG_RX_TMR_MODE		 (1L<<1)
3564 #define BNX_HC_CONFIG_TX_TMR_MODE		 (1L<<2)
3565 #define BNX_HC_CONFIG_COM_TMR_MODE		 (1L<<3)
3566 #define BNX_HC_CONFIG_CMD_TMR_MODE		 (1L<<4)
3567 #define BNX_HC_CONFIG_STATISTIC_PRIORITY	 (1L<<5)
3568 #define BNX_HC_CONFIG_STATUS_PRIORITY		 (1L<<6)
3569 #define BNX_HC_CONFIG_STAT_MEM_ADDR		 (0xffL<<8)
3570 
3571 #define BNX_HC_ATTN_BITS_ENABLE			0x0000680c
3572 #define BNX_HC_STATUS_ADDR_L			0x00006810
3573 #define BNX_HC_STATUS_ADDR_H			0x00006814
3574 #define BNX_HC_STATISTICS_ADDR_L		0x00006818
3575 #define BNX_HC_STATISTICS_ADDR_H		0x0000681c
3576 #define BNX_HC_TX_QUICK_CONS_TRIP		0x00006820
3577 #define BNX_HC_TX_QUICK_CONS_TRIP_VALUE		 (0xffL<<0)
3578 #define BNX_HC_TX_QUICK_CONS_TRIP_INT		 (0xffL<<16)
3579 
3580 #define BNX_HC_COMP_PROD_TRIP			0x00006824
3581 #define BNX_HC_COMP_PROD_TRIP_VALUE		 (0xffL<<0)
3582 #define BNX_HC_COMP_PROD_TRIP_INT		 (0xffL<<16)
3583 
3584 #define BNX_HC_RX_QUICK_CONS_TRIP		0x00006828
3585 #define BNX_HC_RX_QUICK_CONS_TRIP_VALUE		 (0xffL<<0)
3586 #define BNX_HC_RX_QUICK_CONS_TRIP_INT		 (0xffL<<16)
3587 
3588 #define BNX_HC_RX_TICKS				0x0000682c
3589 #define BNX_HC_RX_TICKS_VALUE			 (0x3ffL<<0)
3590 #define BNX_HC_RX_TICKS_INT			 (0x3ffL<<16)
3591 
3592 #define BNX_HC_TX_TICKS				0x00006830
3593 #define BNX_HC_TX_TICKS_VALUE			 (0x3ffL<<0)
3594 #define BNX_HC_TX_TICKS_INT			 (0x3ffL<<16)
3595 
3596 #define BNX_HC_COM_TICKS			0x00006834
3597 #define BNX_HC_COM_TICKS_VALUE			 (0x3ffL<<0)
3598 #define BNX_HC_COM_TICKS_INT			 (0x3ffL<<16)
3599 
3600 #define BNX_HC_CMD_TICKS			0x00006838
3601 #define BNX_HC_CMD_TICKS_VALUE			 (0x3ffL<<0)
3602 #define BNX_HC_CMD_TICKS_INT			 (0x3ffL<<16)
3603 
3604 #define BNX_HC_PERIODIC_TICKS			0x0000683c
3605 #define BNX_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS	 (0xffffL<<0)
3606 
3607 #define BNX_HC_STAT_COLLECT_TICKS			0x00006840
3608 #define BNX_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS	 (0xffL<<4)
3609 
3610 #define BNX_HC_STATS_TICKS			0x00006844
3611 #define BNX_HC_STATS_TICKS_HC_STAT_TICKS	 (0xffffL<<8)
3612 
3613 #define BNX_HC_STAT_MEM_DATA			0x0000684c
3614 #define BNX_HC_STAT_GEN_SEL_0				0x00006850
3615 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0			 (0x7fL<<0)
3616 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0	 (0L<<0)
3617 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1	 (1L<<0)
3618 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2	 (2L<<0)
3619 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3	 (3L<<0)
3620 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4	 (4L<<0)
3621 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5	 (5L<<0)
3622 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6	 (6L<<0)
3623 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7	 (7L<<0)
3624 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8	 (8L<<0)
3625 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9	 (9L<<0)
3626 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10	 (10L<<0)
3627 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11	 (11L<<0)
3628 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0	 (12L<<0)
3629 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1	 (13L<<0)
3630 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2	 (14L<<0)
3631 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3	 (15L<<0)
3632 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4	 (16L<<0)
3633 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5	 (17L<<0)
3634 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6	 (18L<<0)
3635 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7	 (19L<<0)
3636 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0	 (20L<<0)
3637 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1	 (21L<<0)
3638 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2	 (22L<<0)
3639 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3	 (23L<<0)
3640 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4	 (24L<<0)
3641 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5	 (25L<<0)
3642 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6	 (26L<<0)
3643 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7	 (27L<<0)
3644 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8	 (28L<<0)
3645 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9	 (29L<<0)
3646 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10	 (30L<<0)
3647 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11	 (31L<<0)
3648 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0	 (32L<<0)
3649 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1	 (33L<<0)
3650 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2	 (34L<<0)
3651 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3	 (35L<<0)
3652 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0	 (36L<<0)
3653 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1	 (37L<<0)
3654 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2	 (38L<<0)
3655 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3	 (39L<<0)
3656 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4	 (40L<<0)
3657 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5	 (41L<<0)
3658 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6	 (42L<<0)
3659 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7	 (43L<<0)
3660 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0	 (44L<<0)
3661 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1	 (45L<<0)
3662 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2	 (46L<<0)
3663 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3	 (47L<<0)
3664 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4	 (48L<<0)
3665 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5	 (49L<<0)
3666 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6	 (50L<<0)
3667 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7	 (51L<<0)
3668 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT	 (52L<<0)
3669 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT	 (53L<<0)
3670 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS	 (54L<<0)
3671 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN	 (55L<<0)
3672 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR	 (56L<<0)
3673 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK	 (59L<<0)
3674 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK	 (60L<<0)
3675 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK	 (61L<<0)
3676 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT	 (62L<<0)
3677 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT	 (63L<<0)
3678 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT	 (64L<<0)
3679 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT	 (65L<<0)
3680 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT	 (66L<<0)
3681 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT	 (67L<<0)
3682 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT	 (68L<<0)
3683 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
3684 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
3685 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
3686 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT	 (72L<<0)
3687 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT	 (73L<<0)
3688 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT	 (74L<<0)
3689 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT	 (75L<<0)
3690 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT	 (76L<<0)
3691 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT	 (77L<<0)
3692 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT	 (78L<<0)
3693 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT	 (79L<<0)
3694 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT	 (80L<<0)
3695 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT	 (81L<<0)
3696 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT	 (82L<<0)
3697 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT	 (83L<<0)
3698 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT	 (84L<<0)
3699 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT	 (85L<<0)
3700 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT	 (86L<<0)
3701 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT	 (87L<<0)
3702 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT \
3703 							 (88L<<0)
3704 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT \
3705 							 (89L<<0)
3706 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT	 (90L<<0)
3707 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT	 (91L<<0)
3708 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT	 (92L<<0)
3709 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT \
3710 							 (93L<<0)
3711 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT \
3712 							 (94L<<0)
3713 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64	 (95L<<0)
3714 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64	 (96L<<0)
3715 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS	 (97L<<0)
3716 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS	 (98L<<0)
3717 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT	 (99L<<0)
3718 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT	 (100L<<0)
3719 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT	 (101L<<0)
3720 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT	 (102L<<0)
3721 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT	 (103L<<0)
3722 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT	 (104L<<0)
3723 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT	 (105L<<0)
3724 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT	 (106L<<0)
3725 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT	 (107L<<0)
3726 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT	 (108L<<0)
3727 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT	 (109L<<0)
3728 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT	 (110L<<0)
3729 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT	 (111L<<0)
3730 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT	 (112L<<0)
3731 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT	 (113L<<0)
3732 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT	 (114L<<0)
3733 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0	 (115L<<0)
3734 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1	 (116L<<0)
3735 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2	 (117L<<0)
3736 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3	 (118L<<0)
3737 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4	 (119L<<0)
3738 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5	 (120L<<0)
3739 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS	 (121L<<0)
3740 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS	 (122L<<0)
3741 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT	 (127L<<0)
3742 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_1			 (0x7fL<<8)
3743 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_2			 (0x7fL<<16)
3744 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_3			 (0x7fL<<24)
3745 
3746 #define BNX_HC_STAT_GEN_SEL_1			0x00006854
3747 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_4		 (0x7fL<<0)
3748 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_5		 (0x7fL<<8)
3749 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_6		 (0x7fL<<16)
3750 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_7		 (0x7fL<<24)
3751 
3752 #define BNX_HC_STAT_GEN_SEL_2			0x00006858
3753 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_8		 (0x7fL<<0)
3754 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_9		 (0x7fL<<8)
3755 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_10	 (0x7fL<<16)
3756 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_11	 (0x7fL<<24)
3757 
3758 #define BNX_HC_STAT_GEN_SEL_3			0x0000685c
3759 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_12	 (0x7fL<<0)
3760 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_13	 (0x7fL<<8)
3761 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_14	 (0x7fL<<16)
3762 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_15	 (0x7fL<<24)
3763 
3764 #define BNX_HC_STAT_GEN_STAT0			0x00006888
3765 #define BNX_HC_STAT_GEN_STAT1			0x0000688c
3766 #define BNX_HC_STAT_GEN_STAT2			0x00006890
3767 #define BNX_HC_STAT_GEN_STAT3			0x00006894
3768 #define BNX_HC_STAT_GEN_STAT4			0x00006898
3769 #define BNX_HC_STAT_GEN_STAT5			0x0000689c
3770 #define BNX_HC_STAT_GEN_STAT6			0x000068a0
3771 #define BNX_HC_STAT_GEN_STAT7			0x000068a4
3772 #define BNX_HC_STAT_GEN_STAT8			0x000068a8
3773 #define BNX_HC_STAT_GEN_STAT9			0x000068ac
3774 #define BNX_HC_STAT_GEN_STAT10			0x000068b0
3775 #define BNX_HC_STAT_GEN_STAT11			0x000068b4
3776 #define BNX_HC_STAT_GEN_STAT12			0x000068b8
3777 #define BNX_HC_STAT_GEN_STAT13			0x000068bc
3778 #define BNX_HC_STAT_GEN_STAT14			0x000068c0
3779 #define BNX_HC_STAT_GEN_STAT15			0x000068c4
3780 #define BNX_HC_STAT_GEN_STAT_AC0		0x000068c8
3781 #define BNX_HC_STAT_GEN_STAT_AC1		0x000068cc
3782 #define BNX_HC_STAT_GEN_STAT_AC2		0x000068d0
3783 #define BNX_HC_STAT_GEN_STAT_AC3		0x000068d4
3784 #define BNX_HC_STAT_GEN_STAT_AC4		0x000068d8
3785 #define BNX_HC_STAT_GEN_STAT_AC5		0x000068dc
3786 #define BNX_HC_STAT_GEN_STAT_AC6		0x000068e0
3787 #define BNX_HC_STAT_GEN_STAT_AC7		0x000068e4
3788 #define BNX_HC_STAT_GEN_STAT_AC8		0x000068e8
3789 #define BNX_HC_STAT_GEN_STAT_AC9		0x000068ec
3790 #define BNX_HC_STAT_GEN_STAT_AC10		0x000068f0
3791 #define BNX_HC_STAT_GEN_STAT_AC11		0x000068f4
3792 #define BNX_HC_STAT_GEN_STAT_AC12		0x000068f8
3793 #define BNX_HC_STAT_GEN_STAT_AC13		0x000068fc
3794 #define BNX_HC_STAT_GEN_STAT_AC14		0x00006900
3795 #define BNX_HC_STAT_GEN_STAT_AC15		0x00006904
3796 #define BNX_HC_VIS				0x00006908
3797 #define BNX_HC_VIS_STAT_BUILD_STATE		 (0xfL<<0)
3798 #define BNX_HC_VIS_STAT_BUILD_STATE_IDLE	 (0L<<0)
3799 #define BNX_HC_VIS_STAT_BUILD_STATE_START	 (1L<<0)
3800 #define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST	 (2L<<0)
3801 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64	 (3L<<0)
3802 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32	 (4L<<0)
3803 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE	 (5L<<0)
3804 #define BNX_HC_VIS_STAT_BUILD_STATE_DMA		 (6L<<0)
3805 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL	 (7L<<0)
3806 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW	 (8L<<0)
3807 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH	 (9L<<0)
3808 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA	 (10L<<0)
3809 #define BNX_HC_VIS_DMA_STAT_STATE		 (0xfL<<8)
3810 #define BNX_HC_VIS_DMA_STAT_STATE_IDLE		 (0L<<8)
3811 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM	 (1L<<8)
3812 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA	 (2L<<8)
3813 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP	 (3L<<8)
3814 #define BNX_HC_VIS_DMA_STAT_STATE_COMP		 (4L<<8)
3815 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM	 (5L<<8)
3816 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA	 (6L<<8)
3817 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1	 (7L<<8)
3818 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2	 (8L<<8)
3819 #define BNX_HC_VIS_DMA_STAT_STATE_WAIT		 (9L<<8)
3820 #define BNX_HC_VIS_DMA_STAT_STATE_ABORT		 (15L<<8)
3821 #define BNX_HC_VIS_DMA_MSI_STATE		 (0x7L<<12)
3822 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE	 (0x3L<<15)
3823 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE	 (0L<<15)
3824 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT	 (1L<<15)
3825 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START	 (2L<<15)
3826 
3827 #define BNX_HC_VIS_1				0x0000690c
3828 #define BNX_HC_VIS_1_HW_INTACK_STATE		 (1L<<4)
3829 #define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE	 (0L<<4)
3830 #define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT	 (1L<<4)
3831 #define BNX_HC_VIS_1_SW_INTACK_STATE		 (1L<<5)
3832 #define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE	 (0L<<5)
3833 #define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT	 (1L<<5)
3834 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE	 (1L<<6)
3835 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3836 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT	 (1L<<6)
3837 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE	 (1L<<7)
3838 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE	 (0L<<7)
3839 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT	 (1L<<7)
3840 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE		 (0xfL<<17)
3841 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE	 (0L<<17)
3842 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA	 (1L<<17)
3843 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE	 (2L<<17)
3844 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN	 (3L<<17)
3845 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT	 (4L<<17)
3846 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3847 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3848 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT	 (7L<<17)
3849 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE		 (0x3L<<21)
3850 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL	 (0L<<21)
3851 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR	 (1L<<21)
3852 #define BNX_HC_VIS_1_INT_GEN_STATE		 (1L<<23)
3853 #define BNX_HC_VIS_1_INT_GEN_STATE_DLE		 (0L<<23)
3854 #define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT	 (1L<<23)
3855 #define BNX_HC_VIS_1_STAT_CHAN_ID		 (0x7L<<24)
3856 #define BNX_HC_VIS_1_INT_B			 (1L<<27)
3857 
3858 #define BNX_HC_DEBUG_VECT_PEEK			0x00006910
3859 #define BNX_HC_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
3860 #define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
3861 #define BNX_HC_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
3862 #define BNX_HC_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
3863 #define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
3864 #define BNX_HC_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
3865 
3866 
3867 /*
3868  *  txp_reg definition
3869  *  offset: 0x40000
3870  */
3871 #define BNX_TXP_CPU_MODE			0x00045000
3872 #define BNX_TXP_CPU_MODE_LOCAL_RST		 (1L<<0)
3873 #define BNX_TXP_CPU_MODE_STEP_ENA		 (1L<<1)
3874 #define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA	 (1L<<2)
3875 #define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA	 (1L<<3)
3876 #define BNX_TXP_CPU_MODE_MSG_BIT1		 (1L<<6)
3877 #define BNX_TXP_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
3878 #define BNX_TXP_CPU_MODE_SOFT_HALT		 (1L<<10)
3879 #define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA	 (1L<<11)
3880 #define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA	 (1L<<12)
3881 #define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA	 (1L<<13)
3882 #define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3883 
3884 #define BNX_TXP_CPU_STATE			0x00045004
3885 #define BNX_TXP_CPU_STATE_BREAKPOINT		 (1L<<0)
3886 #define BNX_TXP_CPU_STATE_BAD_INST_HALTED	 (1L<<2)
3887 #define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED	 (1L<<3)
3888 #define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED	 (1L<<4)
3889 #define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
3890 #define BNX_TXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
3891 #define BNX_TXP_CPU_STATE_ALIGN_HALTED		 (1L<<7)
3892 #define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED	 (1L<<8)
3893 #define BNX_TXP_CPU_STATE_SOFT_HALTED		 (1L<<10)
3894 #define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW	 (1L<<11)
3895 #define BNX_TXP_CPU_STATE_INTERRRUPT		 (1L<<12)
3896 #define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL	 (1L<<14)
3897 #define BNX_TXP_CPU_STATE_INST_FETCH_STALL	 (1L<<15)
3898 #define BNX_TXP_CPU_STATE_BLOCKED_READ		 (1L<<31)
3899 
3900 #define BNX_TXP_CPU_EVENT_MASK				0x00045008
3901 #define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
3902 #define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
3903 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
3904 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
3905 #define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3906 #define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
3907 #define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
3908 #define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
3909 #define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
3910 #define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
3911 #define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
3912 
3913 #define BNX_TXP_CPU_PROGRAM_COUNTER		0x0004501c
3914 #define BNX_TXP_CPU_INSTRUCTION			0x00045020
3915 #define BNX_TXP_CPU_DATA_ACCESS			0x00045024
3916 #define BNX_TXP_CPU_INTERRUPT_ENABLE		0x00045028
3917 #define BNX_TXP_CPU_INTERRUPT_VECTOR		0x0004502c
3918 #define BNX_TXP_CPU_INTERRUPT_SAVED_PC		0x00045030
3919 #define BNX_TXP_CPU_HW_BREAKPOINT		0x00045034
3920 #define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE	 (1L<<0)
3921 #define BNX_TXP_CPU_HW_BREAKPOINT_ADDRESS	 (0x3fffffffL<<2)
3922 
3923 #define BNX_TXP_CPU_DEBUG_VECT_PEEK		0x00045038
3924 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
3925 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
3926 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_SEL	 (0xfL<<12)
3927 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
3928 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
3929 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_SEL	 (0xfL<<28)
3930 
3931 #define BNX_TXP_CPU_LAST_BRANCH_ADDR		0x00045048
3932 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE	 (1L<<1)
3933 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
3934 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3935 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_LBA	 (0x3fffffffL<<2)
3936 
3937 #define BNX_TXP_CPU_REG_FILE			0x00045200
3938 #define BNX_TXP_FTQ_DATA			0x000453c0
3939 #define BNX_TXP_FTQ_CMD				0x000453f8
3940 #define BNX_TXP_FTQ_CMD_OFFSET			 (0x3ffL<<0)
3941 #define BNX_TXP_FTQ_CMD_WR_TOP			 (1L<<10)
3942 #define BNX_TXP_FTQ_CMD_WR_TOP_0		 (0L<<10)
3943 #define BNX_TXP_FTQ_CMD_WR_TOP_1		 (1L<<10)
3944 #define BNX_TXP_FTQ_CMD_SFT_RESET		 (1L<<25)
3945 #define BNX_TXP_FTQ_CMD_RD_DATA			 (1L<<26)
3946 #define BNX_TXP_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
3947 #define BNX_TXP_FTQ_CMD_ADD_DATA		 (1L<<28)
3948 #define BNX_TXP_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
3949 #define BNX_TXP_FTQ_CMD_POP			 (1L<<30)
3950 #define BNX_TXP_FTQ_CMD_BUSY			 (1L<<31)
3951 
3952 #define BNX_TXP_FTQ_CTL				0x000453fc
3953 #define BNX_TXP_FTQ_CTL_INTERVENE		 (1L<<0)
3954 #define BNX_TXP_FTQ_CTL_OVERFLOW		 (1L<<1)
3955 #define BNX_TXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3956 #define BNX_TXP_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
3957 #define BNX_TXP_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
3958 
3959 #define BNX_TXP_SCRATCH				0x00060000
3960 
3961 
3962 /*
3963  *  tpat_reg definition
3964  *  offset: 0x80000
3965  */
3966 #define BNX_TPAT_CPU_MODE			0x00085000
3967 #define BNX_TPAT_CPU_MODE_LOCAL_RST		 (1L<<0)
3968 #define BNX_TPAT_CPU_MODE_STEP_ENA		 (1L<<1)
3969 #define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA	 (1L<<2)
3970 #define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA	 (1L<<3)
3971 #define BNX_TPAT_CPU_MODE_MSG_BIT1		 (1L<<6)
3972 #define BNX_TPAT_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
3973 #define BNX_TPAT_CPU_MODE_SOFT_HALT		 (1L<<10)
3974 #define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA	 (1L<<11)
3975 #define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA	 (1L<<12)
3976 #define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA	 (1L<<13)
3977 #define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
3978 
3979 #define BNX_TPAT_CPU_STATE			0x00085004
3980 #define BNX_TPAT_CPU_STATE_BREAKPOINT		 (1L<<0)
3981 #define BNX_TPAT_CPU_STATE_BAD_INST_HALTED	 (1L<<2)
3982 #define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED	 (1L<<3)
3983 #define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED	 (1L<<4)
3984 #define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
3985 #define BNX_TPAT_CPU_STATE_BAD_pc_HALTED	 (1L<<6)
3986 #define BNX_TPAT_CPU_STATE_ALIGN_HALTED		 (1L<<7)
3987 #define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED	 (1L<<8)
3988 #define BNX_TPAT_CPU_STATE_SOFT_HALTED		 (1L<<10)
3989 #define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW	 (1L<<11)
3990 #define BNX_TPAT_CPU_STATE_INTERRRUPT		 (1L<<12)
3991 #define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL	 (1L<<14)
3992 #define BNX_TPAT_CPU_STATE_INST_FETCH_STALL	 (1L<<15)
3993 #define BNX_TPAT_CPU_STATE_BLOCKED_READ		 (1L<<31)
3994 
3995 #define BNX_TPAT_CPU_EVENT_MASK				0x00085008
3996 #define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
3997 #define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
3998 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
3999 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4000 #define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4001 #define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4002 #define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4003 #define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4004 #define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4005 #define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4006 #define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4007 
4008 #define BNX_TPAT_CPU_PROGRAM_COUNTER		0x0008501c
4009 #define BNX_TPAT_CPU_INSTRUCTION		0x00085020
4010 #define BNX_TPAT_CPU_DATA_ACCESS		0x00085024
4011 #define BNX_TPAT_CPU_INTERRUPT_ENABLE		0x00085028
4012 #define BNX_TPAT_CPU_INTERRUPT_VECTOR		0x0008502c
4013 #define BNX_TPAT_CPU_INTERRUPT_SAVED_PC		0x00085030
4014 #define BNX_TPAT_CPU_HW_BREAKPOINT		0x00085034
4015 #define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE	 (1L<<0)
4016 #define BNX_TPAT_CPU_HW_BREAKPOINT_ADDRESS	 (0x3fffffffL<<2)
4017 
4018 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK		0x00085038
4019 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
4020 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
4021 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL	 (0xfL<<12)
4022 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
4023 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
4024 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL	 (0xfL<<28)
4025 
4026 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR		0x00085048
4027 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE	 (1L<<1)
4028 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
4029 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4030 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_LBA	 (0x3fffffffL<<2)
4031 
4032 #define BNX_TPAT_CPU_REG_FILE			0x00085200
4033 #define BNX_TPAT_FTQ_DATA			0x000853c0
4034 #define BNX_TPAT_FTQ_CMD			0x000853f8
4035 #define BNX_TPAT_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4036 #define BNX_TPAT_FTQ_CMD_WR_TOP			 (1L<<10)
4037 #define BNX_TPAT_FTQ_CMD_WR_TOP_0		 (0L<<10)
4038 #define BNX_TPAT_FTQ_CMD_WR_TOP_1		 (1L<<10)
4039 #define BNX_TPAT_FTQ_CMD_SFT_RESET		 (1L<<25)
4040 #define BNX_TPAT_FTQ_CMD_RD_DATA		 (1L<<26)
4041 #define BNX_TPAT_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4042 #define BNX_TPAT_FTQ_CMD_ADD_DATA		 (1L<<28)
4043 #define BNX_TPAT_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4044 #define BNX_TPAT_FTQ_CMD_POP			 (1L<<30)
4045 #define BNX_TPAT_FTQ_CMD_BUSY			 (1L<<31)
4046 
4047 #define BNX_TPAT_FTQ_CTL			0x000853fc
4048 #define BNX_TPAT_FTQ_CTL_INTERVENE		 (1L<<0)
4049 #define BNX_TPAT_FTQ_CTL_OVERFLOW		 (1L<<1)
4050 #define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
4051 #define BNX_TPAT_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4052 #define BNX_TPAT_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4053 
4054 #define BNX_TPAT_SCRATCH			0x000a0000
4055 
4056 
4057 /*
4058  *  rxp_reg definition
4059  *  offset: 0xc0000
4060  */
4061 #define BNX_RXP_CPU_MODE			0x000c5000
4062 #define BNX_RXP_CPU_MODE_LOCAL_RST		 (1L<<0)
4063 #define BNX_RXP_CPU_MODE_STEP_ENA		 (1L<<1)
4064 #define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA	 (1L<<2)
4065 #define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA	 (1L<<3)
4066 #define BNX_RXP_CPU_MODE_MSG_BIT1		 (1L<<6)
4067 #define BNX_RXP_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
4068 #define BNX_RXP_CPU_MODE_SOFT_HALT		 (1L<<10)
4069 #define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA	 (1L<<11)
4070 #define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA	 (1L<<12)
4071 #define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA	 (1L<<13)
4072 #define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4073 
4074 #define BNX_RXP_CPU_STATE			0x000c5004
4075 #define BNX_RXP_CPU_STATE_BREAKPOINT		 (1L<<0)
4076 #define BNX_RXP_CPU_STATE_BAD_INST_HALTED	 (1L<<2)
4077 #define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED	 (1L<<3)
4078 #define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED	 (1L<<4)
4079 #define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
4080 #define BNX_RXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4081 #define BNX_RXP_CPU_STATE_ALIGN_HALTED		 (1L<<7)
4082 #define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED	 (1L<<8)
4083 #define BNX_RXP_CPU_STATE_SOFT_HALTED		 (1L<<10)
4084 #define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW	 (1L<<11)
4085 #define BNX_RXP_CPU_STATE_INTERRRUPT		 (1L<<12)
4086 #define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL	 (1L<<14)
4087 #define BNX_RXP_CPU_STATE_INST_FETCH_STALL	 (1L<<15)
4088 #define BNX_RXP_CPU_STATE_BLOCKED_READ		 (1L<<31)
4089 
4090 #define BNX_RXP_CPU_EVENT_MASK				0x000c5008
4091 #define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4092 #define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4093 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4094 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4095 #define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4096 #define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4097 #define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4098 #define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4099 #define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
4100 #define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4101 #define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4102 
4103 #define BNX_RXP_CPU_PROGRAM_COUNTER		0x000c501c
4104 #define BNX_RXP_CPU_INSTRUCTION			0x000c5020
4105 #define BNX_RXP_CPU_DATA_ACCESS			0x000c5024
4106 #define BNX_RXP_CPU_INTERRUPT_ENABLE		0x000c5028
4107 #define BNX_RXP_CPU_INTERRUPT_VECTOR		0x000c502c
4108 #define BNX_RXP_CPU_INTERRUPT_SAVED_PC		0x000c5030
4109 #define BNX_RXP_CPU_HW_BREAKPOINT		0x000c5034
4110 #define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE	 (1L<<0)
4111 #define BNX_RXP_CPU_HW_BREAKPOINT_ADDRESS	 (0x3fffffffL<<2)
4112 
4113 #define BNX_RXP_CPU_DEBUG_VECT_PEEK		0x000c5038
4114 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
4115 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
4116 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_SEL	 (0xfL<<12)
4117 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
4118 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
4119 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_SEL	 (0xfL<<28)
4120 
4121 #define BNX_RXP_CPU_LAST_BRANCH_ADDR		0x000c5048
4122 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE	 (1L<<1)
4123 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
4124 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4125 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_LBA	 (0x3fffffffL<<2)
4126 
4127 #define BNX_RXP_CPU_REG_FILE			0x000c5200
4128 #define BNX_RXP_CFTQ_DATA			0x000c5380
4129 #define BNX_RXP_CFTQ_CMD			0x000c53b8
4130 #define BNX_RXP_CFTQ_CMD_OFFSET			 (0x3ffL<<0)
4131 #define BNX_RXP_CFTQ_CMD_WR_TOP			 (1L<<10)
4132 #define BNX_RXP_CFTQ_CMD_WR_TOP_0		 (0L<<10)
4133 #define BNX_RXP_CFTQ_CMD_WR_TOP_1		 (1L<<10)
4134 #define BNX_RXP_CFTQ_CMD_SFT_RESET		 (1L<<25)
4135 #define BNX_RXP_CFTQ_CMD_RD_DATA		 (1L<<26)
4136 #define BNX_RXP_CFTQ_CMD_ADD_INTERVEN		 (1L<<27)
4137 #define BNX_RXP_CFTQ_CMD_ADD_DATA		 (1L<<28)
4138 #define BNX_RXP_CFTQ_CMD_INTERVENE_CLR		 (1L<<29)
4139 #define BNX_RXP_CFTQ_CMD_POP			 (1L<<30)
4140 #define BNX_RXP_CFTQ_CMD_BUSY			 (1L<<31)
4141 
4142 #define BNX_RXP_CFTQ_CTL			0x000c53bc
4143 #define BNX_RXP_CFTQ_CTL_INTERVENE		 (1L<<0)
4144 #define BNX_RXP_CFTQ_CTL_OVERFLOW		 (1L<<1)
4145 #define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE	 (1L<<2)
4146 #define BNX_RXP_CFTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4147 #define BNX_RXP_CFTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4148 
4149 #define BNX_RXP_FTQ_DATA			0x000c53c0
4150 #define BNX_RXP_FTQ_CMD				0x000c53f8
4151 #define BNX_RXP_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4152 #define BNX_RXP_FTQ_CMD_WR_TOP			 (1L<<10)
4153 #define BNX_RXP_FTQ_CMD_WR_TOP_0		 (0L<<10)
4154 #define BNX_RXP_FTQ_CMD_WR_TOP_1		 (1L<<10)
4155 #define BNX_RXP_FTQ_CMD_SFT_RESET		 (1L<<25)
4156 #define BNX_RXP_FTQ_CMD_RD_DATA			 (1L<<26)
4157 #define BNX_RXP_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4158 #define BNX_RXP_FTQ_CMD_ADD_DATA		 (1L<<28)
4159 #define BNX_RXP_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4160 #define BNX_RXP_FTQ_CMD_POP			 (1L<<30)
4161 #define BNX_RXP_FTQ_CMD_BUSY			 (1L<<31)
4162 
4163 #define BNX_RXP_FTQ_CTL				0x000c53fc
4164 #define BNX_RXP_FTQ_CTL_INTERVENE		 (1L<<0)
4165 #define BNX_RXP_FTQ_CTL_OVERFLOW		 (1L<<1)
4166 #define BNX_RXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4167 #define BNX_RXP_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4168 #define BNX_RXP_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4169 
4170 #define BNX_RXP_SCRATCH				0x000e0000
4171 
4172 
4173 /*
4174  *  com_reg definition
4175  *  offset: 0x100000
4176  */
4177 #define BNX_COM_CPU_MODE				0x00105000
4178 #define BNX_COM_CPU_MODE_LOCAL_RST			 (1L<<0)
4179 #define BNX_COM_CPU_MODE_STEP_ENA			 (1L<<1)
4180 #define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4181 #define BNX_COM_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4182 #define BNX_COM_CPU_MODE_MSG_BIT1			 (1L<<6)
4183 #define BNX_COM_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4184 #define BNX_COM_CPU_MODE_SOFT_HALT			 (1L<<10)
4185 #define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4186 #define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4187 #define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4188 #define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4189 
4190 #define BNX_COM_CPU_STATE			0x00105004
4191 #define BNX_COM_CPU_STATE_BREAKPOINT		 (1L<<0)
4192 #define BNX_COM_CPU_STATE_BAD_INST_HALTED	 (1L<<2)
4193 #define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED	 (1L<<3)
4194 #define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED	 (1L<<4)
4195 #define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
4196 #define BNX_COM_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4197 #define BNX_COM_CPU_STATE_ALIGN_HALTED		 (1L<<7)
4198 #define BNX_COM_CPU_STATE_FIO_ABORT_HALTED	 (1L<<8)
4199 #define BNX_COM_CPU_STATE_SOFT_HALTED		 (1L<<10)
4200 #define BNX_COM_CPU_STATE_SPAD_UNDERFLOW	 (1L<<11)
4201 #define BNX_COM_CPU_STATE_INTERRRUPT		 (1L<<12)
4202 #define BNX_COM_CPU_STATE_DATA_ACCESS_STALL	 (1L<<14)
4203 #define BNX_COM_CPU_STATE_INST_FETCH_STALL	 (1L<<15)
4204 #define BNX_COM_CPU_STATE_BLOCKED_READ		 (1L<<31)
4205 
4206 #define BNX_COM_CPU_EVENT_MASK				0x00105008
4207 #define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4208 #define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4209 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4210 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4211 #define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4212 #define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4213 #define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4214 #define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4215 #define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
4216 #define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4217 #define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4218 
4219 #define BNX_COM_CPU_PROGRAM_COUNTER		0x0010501c
4220 #define BNX_COM_CPU_INSTRUCTION			0x00105020
4221 #define BNX_COM_CPU_DATA_ACCESS			0x00105024
4222 #define BNX_COM_CPU_INTERRUPT_ENABLE		0x00105028
4223 #define BNX_COM_CPU_INTERRUPT_VECTOR		0x0010502c
4224 #define BNX_COM_CPU_INTERRUPT_SAVED_PC		0x00105030
4225 #define BNX_COM_CPU_HW_BREAKPOINT		0x00105034
4226 #define BNX_COM_CPU_HW_BREAKPOINT_DISABLE	 (1L<<0)
4227 #define BNX_COM_CPU_HW_BREAKPOINT_ADDRESS	 (0x3fffffffL<<2)
4228 
4229 #define BNX_COM_CPU_DEBUG_VECT_PEEK		0x00105038
4230 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
4231 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
4232 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_SEL	 (0xfL<<12)
4233 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
4234 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
4235 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_SEL	 (0xfL<<28)
4236 
4237 #define BNX_COM_CPU_LAST_BRANCH_ADDR		0x00105048
4238 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE	 (1L<<1)
4239 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
4240 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4241 #define BNX_COM_CPU_LAST_BRANCH_ADDR_LBA	 (0x3fffffffL<<2)
4242 
4243 #define BNX_COM_CPU_REG_FILE			0x00105200
4244 #define BNX_COM_COMXQ_FTQ_DATA			0x00105340
4245 #define BNX_COM_COMXQ_FTQ_CMD			0x00105378
4246 #define BNX_COM_COMXQ_FTQ_CMD_OFFSET		 (0x3ffL<<0)
4247 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP		 (1L<<10)
4248 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0		 (0L<<10)
4249 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1		 (1L<<10)
4250 #define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4251 #define BNX_COM_COMXQ_FTQ_CMD_RD_DATA		 (1L<<26)
4252 #define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN	 (1L<<27)
4253 #define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA		 (1L<<28)
4254 #define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR	 (1L<<29)
4255 #define BNX_COM_COMXQ_FTQ_CMD_POP		 (1L<<30)
4256 #define BNX_COM_COMXQ_FTQ_CMD_BUSY		 (1L<<31)
4257 
4258 #define BNX_COM_COMXQ_FTQ_CTL			0x0010537c
4259 #define BNX_COM_COMXQ_FTQ_CTL_INTERVENE		 (1L<<0)
4260 #define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW		 (1L<<1)
4261 #define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
4262 #define BNX_COM_COMXQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4263 #define BNX_COM_COMXQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4264 
4265 #define BNX_COM_COMTQ_FTQ_DATA			0x00105380
4266 #define BNX_COM_COMTQ_FTQ_CMD			0x001053b8
4267 #define BNX_COM_COMTQ_FTQ_CMD_OFFSET		 (0x3ffL<<0)
4268 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP		 (1L<<10)
4269 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0		 (0L<<10)
4270 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1		 (1L<<10)
4271 #define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4272 #define BNX_COM_COMTQ_FTQ_CMD_RD_DATA		 (1L<<26)
4273 #define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN	 (1L<<27)
4274 #define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA		 (1L<<28)
4275 #define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR	 (1L<<29)
4276 #define BNX_COM_COMTQ_FTQ_CMD_POP		 (1L<<30)
4277 #define BNX_COM_COMTQ_FTQ_CMD_BUSY		 (1L<<31)
4278 
4279 #define BNX_COM_COMTQ_FTQ_CTL			0x001053bc
4280 #define BNX_COM_COMTQ_FTQ_CTL_INTERVENE		 (1L<<0)
4281 #define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW		 (1L<<1)
4282 #define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
4283 #define BNX_COM_COMTQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4284 #define BNX_COM_COMTQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4285 
4286 #define BNX_COM_COMQ_FTQ_DATA			0x001053c0
4287 #define BNX_COM_COMQ_FTQ_CMD			0x001053f8
4288 #define BNX_COM_COMQ_FTQ_CMD_OFFSET		 (0x3ffL<<0)
4289 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP		 (1L<<10)
4290 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0		 (0L<<10)
4291 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1		 (1L<<10)
4292 #define BNX_COM_COMQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4293 #define BNX_COM_COMQ_FTQ_CMD_RD_DATA		 (1L<<26)
4294 #define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN	 (1L<<27)
4295 #define BNX_COM_COMQ_FTQ_CMD_ADD_DATA		 (1L<<28)
4296 #define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR	 (1L<<29)
4297 #define BNX_COM_COMQ_FTQ_CMD_POP		 (1L<<30)
4298 #define BNX_COM_COMQ_FTQ_CMD_BUSY		 (1L<<31)
4299 
4300 #define BNX_COM_COMQ_FTQ_CTL			0x001053fc
4301 #define BNX_COM_COMQ_FTQ_CTL_INTERVENE		 (1L<<0)
4302 #define BNX_COM_COMQ_FTQ_CTL_OVERFLOW		 (1L<<1)
4303 #define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
4304 #define BNX_COM_COMQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4305 #define BNX_COM_COMQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4306 
4307 #define BNX_COM_SCRATCH				0x00120000
4308 
4309 
4310 /*
4311  *  cp_reg definition
4312  *  offset: 0x180000
4313  */
4314 #define BNX_CP_CPU_MODE				0x00185000
4315 #define BNX_CP_CPU_MODE_LOCAL_RST		 (1L<<0)
4316 #define BNX_CP_CPU_MODE_STEP_ENA		 (1L<<1)
4317 #define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4318 #define BNX_CP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4319 #define BNX_CP_CPU_MODE_MSG_BIT1		 (1L<<6)
4320 #define BNX_CP_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
4321 #define BNX_CP_CPU_MODE_SOFT_HALT		 (1L<<10)
4322 #define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA	 (1L<<11)
4323 #define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA	 (1L<<12)
4324 #define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA	 (1L<<13)
4325 #define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4326 
4327 #define BNX_CP_CPU_STATE			0x00185004
4328 #define BNX_CP_CPU_STATE_BREAKPOINT		 (1L<<0)
4329 #define BNX_CP_CPU_STATE_BAD_INST_HALTED	 (1L<<2)
4330 #define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED	 (1L<<3)
4331 #define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED	 (1L<<4)
4332 #define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
4333 #define BNX_CP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4334 #define BNX_CP_CPU_STATE_ALIGN_HALTED		 (1L<<7)
4335 #define BNX_CP_CPU_STATE_FIO_ABORT_HALTED	 (1L<<8)
4336 #define BNX_CP_CPU_STATE_SOFT_HALTED		 (1L<<10)
4337 #define BNX_CP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4338 #define BNX_CP_CPU_STATE_INTERRRUPT		 (1L<<12)
4339 #define BNX_CP_CPU_STATE_DATA_ACCESS_STALL	 (1L<<14)
4340 #define BNX_CP_CPU_STATE_INST_FETCH_STALL	 (1L<<15)
4341 #define BNX_CP_CPU_STATE_BLOCKED_READ		 (1L<<31)
4342 
4343 #define BNX_CP_CPU_EVENT_MASK				0x00185008
4344 #define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4345 #define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4346 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4347 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4348 #define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4349 #define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4350 #define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK		 (1L<<7)
4351 #define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4352 #define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
4353 #define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4354 #define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4355 
4356 #define BNX_CP_CPU_PROGRAM_COUNTER		0x0018501c
4357 #define BNX_CP_CPU_INSTRUCTION			0x00185020
4358 #define BNX_CP_CPU_DATA_ACCESS			0x00185024
4359 #define BNX_CP_CPU_INTERRUPT_ENABLE		0x00185028
4360 #define BNX_CP_CPU_INTERRUPT_VECTOR		0x0018502c
4361 #define BNX_CP_CPU_INTERRUPT_SAVED_PC		0x00185030
4362 #define BNX_CP_CPU_HW_BREAKPOINT		0x00185034
4363 #define BNX_CP_CPU_HW_BREAKPOINT_DISABLE	 (1L<<0)
4364 #define BNX_CP_CPU_HW_BREAKPOINT_ADDRESS	 (0x3fffffffL<<2)
4365 
4366 #define BNX_CP_CPU_DEBUG_VECT_PEEK		0x00185038
4367 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
4368 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
4369 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_SEL	 (0xfL<<12)
4370 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
4371 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
4372 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_SEL	 (0xfL<<28)
4373 
4374 #define BNX_CP_CPU_LAST_BRANCH_ADDR		0x00185048
4375 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE	 (1L<<1)
4376 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
4377 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4378 #define BNX_CP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)
4379 
4380 #define BNX_CP_CPU_REG_FILE			0x00185200
4381 #define BNX_CP_CPQ_FTQ_DATA			0x001853c0
4382 #define BNX_CP_CPQ_FTQ_CMD			0x001853f8
4383 #define BNX_CP_CPQ_FTQ_CMD_OFFSET		 (0x3ffL<<0)
4384 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP		 (1L<<10)
4385 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0		 (0L<<10)
4386 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1		 (1L<<10)
4387 #define BNX_CP_CPQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4388 #define BNX_CP_CPQ_FTQ_CMD_RD_DATA		 (1L<<26)
4389 #define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4390 #define BNX_CP_CPQ_FTQ_CMD_ADD_DATA		 (1L<<28)
4391 #define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR	 (1L<<29)
4392 #define BNX_CP_CPQ_FTQ_CMD_POP			 (1L<<30)
4393 #define BNX_CP_CPQ_FTQ_CMD_BUSY			 (1L<<31)
4394 
4395 #define BNX_CP_CPQ_FTQ_CTL			0x001853fc
4396 #define BNX_CP_CPQ_FTQ_CTL_INTERVENE		 (1L<<0)
4397 #define BNX_CP_CPQ_FTQ_CTL_OVERFLOW		 (1L<<1)
4398 #define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
4399 #define BNX_CP_CPQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4400 #define BNX_CP_CPQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4401 
4402 #define BNX_CP_SCRATCH				0x001a0000
4403 
4404 
4405 /*
4406  *  mcp_reg definition
4407  *  offset: 0x140000
4408  */
4409 #define BNX_MCP_CPU_MODE			0x00145000
4410 #define BNX_MCP_CPU_MODE_LOCAL_RST		 (1L<<0)
4411 #define BNX_MCP_CPU_MODE_STEP_ENA		 (1L<<1)
4412 #define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA	 (1L<<2)
4413 #define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA	 (1L<<3)
4414 #define BNX_MCP_CPU_MODE_MSG_BIT1		 (1L<<6)
4415 #define BNX_MCP_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
4416 #define BNX_MCP_CPU_MODE_SOFT_HALT		 (1L<<10)
4417 #define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA	 (1L<<11)
4418 #define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA	 (1L<<12)
4419 #define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA	 (1L<<13)
4420 #define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4421 
4422 #define BNX_MCP_CPU_STATE			0x00145004
4423 #define BNX_MCP_CPU_STATE_BREAKPOINT		 (1L<<0)
4424 #define BNX_MCP_CPU_STATE_BAD_INST_HALTED	 (1L<<2)
4425 #define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED	 (1L<<3)
4426 #define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED	 (1L<<4)
4427 #define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
4428 #define BNX_MCP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4429 #define BNX_MCP_CPU_STATE_ALIGN_HALTED		 (1L<<7)
4430 #define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED	 (1L<<8)
4431 #define BNX_MCP_CPU_STATE_SOFT_HALTED		 (1L<<10)
4432 #define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW	 (1L<<11)
4433 #define BNX_MCP_CPU_STATE_INTERRRUPT		 (1L<<12)
4434 #define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL	 (1L<<14)
4435 #define BNX_MCP_CPU_STATE_INST_FETCH_STALL	 (1L<<15)
4436 #define BNX_MCP_CPU_STATE_BLOCKED_READ		 (1L<<31)
4437 
4438 #define BNX_MCP_CPU_EVENT_MASK				0x00145008
4439 #define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4440 #define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4441 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4442 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4443 #define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4444 #define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4445 #define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4446 #define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4447 #define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
4448 #define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4449 #define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4450 
4451 #define BNX_MCP_CPU_PROGRAM_COUNTER		0x0014501c
4452 #define BNX_MCP_CPU_INSTRUCTION			0x00145020
4453 #define BNX_MCP_CPU_DATA_ACCESS			0x00145024
4454 #define BNX_MCP_CPU_INTERRUPT_ENABLE		0x00145028
4455 #define BNX_MCP_CPU_INTERRUPT_VECTOR		0x0014502c
4456 #define BNX_MCP_CPU_INTERRUPT_SAVED_PC		0x00145030
4457 #define BNX_MCP_CPU_HW_BREAKPOINT		0x00145034
4458 #define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE	 (1L<<0)
4459 #define BNX_MCP_CPU_HW_BREAKPOINT_ADDRESS	 (0x3fffffffL<<2)
4460 
4461 #define BNX_MCP_CPU_DEBUG_VECT_PEEK		0x00145038
4462 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE	 (0x7ffL<<0)
4463 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN	 (1L<<11)
4464 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_SEL	 (0xfL<<12)
4465 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE	 (0x7ffL<<16)
4466 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN	 (1L<<27)
4467 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_SEL	 (0xfL<<28)
4468 
4469 #define BNX_MCP_CPU_LAST_BRANCH_ADDR		0x00145048
4470 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE	 (1L<<1)
4471 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
4472 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4473 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_LBA	 (0x3fffffffL<<2)
4474 
4475 #define BNX_MCP_CPU_REG_FILE			0x00145200
4476 #define BNX_MCP_MCPQ_FTQ_DATA			0x001453c0
4477 #define BNX_MCP_MCPQ_FTQ_CMD			0x001453f8
4478 #define BNX_MCP_MCPQ_FTQ_CMD_OFFSET		 (0x3ffL<<0)
4479 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP		 (1L<<10)
4480 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0		 (0L<<10)
4481 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1		 (1L<<10)
4482 #define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4483 #define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA		 (1L<<26)
4484 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN	 (1L<<27)
4485 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA		 (1L<<28)
4486 #define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR	 (1L<<29)
4487 #define BNX_MCP_MCPQ_FTQ_CMD_POP		 (1L<<30)
4488 #define BNX_MCP_MCPQ_FTQ_CMD_BUSY		 (1L<<31)
4489 
4490 #define BNX_MCP_MCPQ_FTQ_CTL			0x001453fc
4491 #define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE		 (1L<<0)
4492 #define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW		 (1L<<1)
4493 #define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE	 (1L<<2)
4494 #define BNX_MCP_MCPQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4495 #define BNX_MCP_MCPQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4496 
4497 #define BNX_MCP_ROM				0x00150000
4498 #define BNX_MCP_SCRATCH				0x00160000
4499 
4500 #define BNX_SHM_HDR_SIGNATURE			BNX_MCP_SCRATCH
4501 #define BNX_SHM_HDR_SIGNATURE_SIG_MASK		0xffff0000
4502 #define BNX_SHM_HDR_SIGNATURE_SIG		0x53530000
4503 #define BNX_SHM_HDR_SIGNATURE_VER_MASK		0x000000ff
4504 #define BNX_SHM_HDR_SIGNATURE_VER_ONE		0x00000001
4505 
4506 #define BNX_SHM_HDR_ADDR_0			BNX_MCP_SCRATCH + 4
4507 #define BNX_SHM_HDR_ADDR_1			BNX_MCP_SCRATCH + 8
4508 
4509 /****************************************************************************/
4510 /* End machine generated definitions.					  */
4511 /****************************************************************************/
4512 
4513 #define NUM_MC_HASH_REGISTERS	8
4514 
4515 
4516 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0.  */
4517 #define PHY_BCM5706_PHY_ID			0x00206160
4518 
4519 #define PHY_ID(id)				((id) & 0xfffffff0)
4520 #define PHY_REV_ID(id)				((id) & 0xf)
4521 
4522 /* 5708 Serdes PHY registers */
4523 
4524 #define BCM5708S_UP1				0xb
4525 
4526 #define BCM5708S_UP1_2G5			0x1
4527 
4528 #define BCM5708S_BLK_ADDR			0x1f
4529 
4530 #define BCM5708S_BLK_ADDR_DIG			0x0000
4531 #define BCM5708S_BLK_ADDR_DIG3			0x0002
4532 #define BCM5708S_BLK_ADDR_TX_MISC		0x0005
4533 
4534 /* Digital Block */
4535 #define BCM5708S_1000X_CTL1			0x10
4536 
4537 #define BCM5708S_1000X_CTL1_FIBER_MODE		0x0001
4538 #define BCM5708S_1000X_CTL1_AUTODET_EN		0x0010
4539 
4540 #define BCM5708S_1000X_CTL2			0x11
4541 
4542 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN	0x0001
4543 
4544 #define BCM5708S_1000X_STAT1			0x14
4545 
4546 #define BCM5708S_1000X_STAT1_SGMII		0x0001
4547 #define BCM5708S_1000X_STAT1_LINK		0x0002
4548 #define BCM5708S_1000X_STAT1_FD			0x0004
4549 #define BCM5708S_1000X_STAT1_SPEED_MASK		0x0018
4550 #define BCM5708S_1000X_STAT1_SPEED_10		0x0000
4551 #define BCM5708S_1000X_STAT1_SPEED_100		0x0008
4552 #define BCM5708S_1000X_STAT1_SPEED_1G		0x0010
4553 #define BCM5708S_1000X_STAT1_SPEED_2G5		0x0018
4554 #define BCM5708S_1000X_STAT1_TX_PAUSE		0x0020
4555 #define BCM5708S_1000X_STAT1_RX_PAUSE		0x0040
4556 
4557 /* Digital3 Block */
4558 #define BCM5708S_DIG_3_0			0x10
4559 
4560 #define BCM5708S_DIG_3_0_USE_IEEE		0x0001
4561 
4562 /* Tx/Misc Block */
4563 #define BCM5708S_TX_ACTL1			0x15
4564 
4565 #define BCM5708S_TX_ACTL1_DRIVER_VCM		0x30
4566 
4567 #define BCM5708S_TX_ACTL3			0x17
4568 
4569 #define RX_COPY_THRESH			92
4570 
4571 #define DMA_READ_CHANS		5
4572 #define DMA_WRITE_CHANS		3
4573 
4574 /* Use the natural page size of the host CPU. */
4575 #define BCM_PAGE_BITS		PAGE_SHIFT
4576 #define BCM_PAGE_SIZE		PAGE_SIZE
4577 
4578 #define TX_PAGES		2
4579 #define TOTAL_TX_BD_PER_PAGE	(BCM_PAGE_SIZE / sizeof(struct tx_bd))
4580 #define USABLE_TX_BD_PER_PAGE	(TOTAL_TX_BD_PER_PAGE - 1)
4581 #define TOTAL_TX_BD		(TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4582 #define USABLE_TX_BD		(USABLE_TX_BD_PER_PAGE * TX_PAGES)
4583 #define MAX_TX_BD		(TOTAL_TX_BD - 1)
4584 
4585 #define RX_PAGES		2
4586 #define TOTAL_RX_BD_PER_PAGE	(BCM_PAGE_SIZE / sizeof(struct rx_bd))
4587 #define USABLE_RX_BD_PER_PAGE	(TOTAL_RX_BD_PER_PAGE - 1)
4588 #define TOTAL_RX_BD		(TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4589 #define USABLE_RX_BD		(USABLE_RX_BD_PER_PAGE * RX_PAGES)
4590 #define MAX_RX_BD		(TOTAL_RX_BD - 1)
4591 
4592 #define NEXT_TX_BD(x)	(((x) & USABLE_TX_BD_PER_PAGE) ==	\
4593 	    (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1
4594 
4595 #define TX_CHAIN_IDX(x)	((x) & MAX_TX_BD)
4596 
4597 #define TX_PAGE(x)	(((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4598 #define TX_IDX(x)	((x) & USABLE_TX_BD_PER_PAGE)
4599 
4600 #define NEXT_RX_BD(x)	(((x) & USABLE_RX_BD_PER_PAGE) ==	\
4601 	    (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1
4602 
4603 #define RX_CHAIN_IDX(x)	((x) & MAX_RX_BD)
4604 
4605 #define RX_PAGE(x)	(((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4606 #define RX_IDX(x)	((x) & USABLE_RX_BD_PER_PAGE)
4607 
4608 /* Context size. */
4609 #define BNX_CTX_SHIFT			7
4610 #define BNX_CTX_SIZE			(1 << BNX_CTX_SHIFT)
4611 #define BNX_CTX_MASK			(BNX_CTX_SIZE - 1)
4612 #define GET_CID_ADDR(_cid)		((_cid) << BNX_CTX_SHIFT)
4613 #define GET_CID(_cid_addr)		((_cid_addr) >> BNX_CTX_SHIFT)
4614 
4615 #define BNX_PHY_CTX_SHIFT		6
4616 #define BNX_PHY_CTX_SIZE		(1 << BNX_PHY_CTX_SHIFT)
4617 #define BNX_PHY_CTX_MASK		(BNX_PHY_CTX_SIZE - 1)
4618 #define GET_PCID_ADDR(_pcid)		((_pcid) << PHY_BNX_CTX_SHIFT)
4619 #define GET_PCID(_pcid_addr)		((_pcid_addr) >> PHY_BNX_CTX_SHIFT)
4620 
4621 #define BNX_MB_KERNEL_CTX_SHIFT		8
4622 #define BNX_MB_KERNEL_CTX_SIZE		(1 << BNX_MB_KERNEL_CTX_SHIFT)
4623 #define BNX_MB_KERNEL_CTX_MASK		(BNX_MB_KERNEL_CTX_SIZE - 1)
4624 #define BNX_MB_GET_CID_ADDR(_cid)	(0x10000 + ((_cid) << BNX_MB_KERNEL_CTX_SHIFT))
4625 
4626 #define MAX_CID_CNT		0x4000
4627 #define MAX_CID_ADDR		(GET_CID_ADDR(MAX_CID_CNT))
4628 #define INVALID_CID_ADDR	0xffffffff
4629 
4630 #define TX_CID			16
4631 #define RX_CID			0
4632 
4633 #define MB_TX_CID_ADDR		BNX_MB_GET_CID_ADDR(TX_CID)
4634 #define MB_RX_CID_ADDR		BNX_MB_GET_CID_ADDR(RX_CID)
4635 
4636 /****************************************************************************/
4637 /* BNX Processor Firmware Load Definitions				    */
4638 /****************************************************************************/
4639 
4640 struct cpu_reg {
4641 	uint32_t mode;
4642 	uint32_t mode_value_halt;
4643 	uint32_t mode_value_sstep;
4644 
4645 	uint32_t state;
4646 	uint32_t state_value_clear;
4647 
4648 	uint32_t gpr0;
4649 	uint32_t evmask;
4650 	uint32_t pc;
4651 	uint32_t inst;
4652 	uint32_t bp;
4653 
4654 	uint32_t spad_base;
4655 
4656 	uint32_t mips_view_base;
4657 };
4658 
4659 struct fw_info {
4660 	uint32_t ver_major;
4661 	uint32_t ver_minor;
4662 	uint32_t ver_fix;
4663 
4664 	uint32_t start_addr;
4665 
4666 	/* Text section. */
4667 	uint32_t text_addr;
4668 	uint32_t text_len;
4669 	uint32_t text_index;
4670 	const uint32_t *text;
4671 
4672 	/* Data section. */
4673 	uint32_t data_addr;
4674 	uint32_t data_len;
4675 	uint32_t data_index;
4676 	const uint32_t *data;
4677 
4678 	/* SBSS section. */
4679 	uint32_t sbss_addr;
4680 	uint32_t sbss_len;
4681 	uint32_t sbss_index;
4682 	const uint32_t *sbss;
4683 
4684 	/* BSS section. */
4685 	uint32_t bss_addr;
4686 	uint32_t bss_len;
4687 	uint32_t bss_index;
4688 	const uint32_t *bss;
4689 
4690 	/* Read-only section. */
4691 	uint32_t rodata_addr;
4692 	uint32_t rodata_len;
4693 	uint32_t rodata_index;
4694 	const uint32_t *rodata;
4695 };
4696 
4697 struct bnx_rv2p_header {
4698 	int		bnx_rv2p_proc1len;
4699 	int		bnx_rv2p_proc2len;
4700 
4701 	/*
4702 	 * Followed by blocks of data, each sized according to
4703 	 * the (rather obvious) block length stated above.
4704 	 */
4705 };
4706 
4707 /*
4708  * The RV2P block must be configured for the system
4709  * page size, or more specifically, the number of
4710  * usable rx_bd's per page, and should be called
4711  * as follows prior to loading the RV2P firmware:
4712  *
4713  * BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE)
4714  *
4715  * The default value is 0xFF.
4716  */
4717 #define BNX_RV2P_PROC2_MAX_BD_PAGE_LOC	5
4718 #define BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(_rv2p, _v) {			\
4719 	_rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] =				\
4720 	(_rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (_v);	\
4721 }
4722 
4723 #define RV2P_PROC1			0
4724 #define RV2P_PROC2			1
4725 
4726 #define BNX_MIREG(x)			(((x) & 0x1F) << 16)
4727 #define BNX_MIPHY(x)			(((x) & 0x1F) << 21)
4728 #define BNX_PHY_TIMEOUT			50
4729 
4730 #define BNX_NVRAM_SIZE			0x200
4731 #define BNX_NVRAM_MAGIC			0x669955aa
4732 #define BNX_CRC32_RESIDUAL		0xdebb20e3
4733 
4734 #define BNX_TX_TIMEOUT			5
4735 
4736 #define BNX_MAX_SEGMENTS		8
4737 #define BNX_DMA_ALIGN			8
4738 #define BNX_DMA_BOUNDARY		0
4739 
4740 #define BNX_MIN_MTU			60
4741 #define BNX_MIN_ETHER_MTU		64
4742 
4743 #define BNX_MAX_STD_MTU			1500
4744 #define BNX_MAX_STD_ETHER_MTU		1518
4745 #define BNX_MAX_STD_ETHER_MTU_VLAN	1522
4746 
4747 #define BNX_MAX_JUMBO_MTU		9000
4748 #define BNX_MAX_JUMBO_ETHER_MTU		9018
4749 #define BNX_MAX_JUMBO_ETHER_MTU_VLAN	9022
4750 
4751 #define BNX_MAX_MRU			MCLBYTES
4752 #define BNX_MAX_JUMBO_MRU		9216
4753