| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| H A D | amdgpu_dc_link_dp.c | 145 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
178 lt_settings->link_settings.link_rate, in dpcd_set_link_settings()
659 link_settings.lane_count); in dpcd_set_lane_settings()
1631 link_settings, in dc_link_dp_sync_lt_attempt()
1645 dp_cs_id, link_settings); in dc_link_dp_sync_lt_attempt()
2029 link_settings.lane_count = in get_common_supported_link_settings()
2034 link_settings.link_rate = in get_common_supported_link_settings()
2061 return link_settings; in get_common_supported_link_settings()
2513 memset(&link_settings, 0, sizeof(link_settings)); in dp_test_send_phy_test_pattern()
2601 link_settings.lane_settings[i]; in dp_test_send_phy_test_pattern()
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| H A D | amdgpu_dc_link_hwss.c | 100 const struct dc_link_settings *link_settings) in dp_enable_link_phy() argument
137 link_settings, in dp_enable_link_phy()
142 link_settings, in dp_enable_link_phy()
149 link->cur_link_settings = *link_settings; in dp_enable_link_phy()
282 const struct link_training_settings *link_settings, in dp_set_hw_lane_settings() argument
291 encoder->funcs->dp_set_lane_settings(encoder, link_settings); in dp_set_hw_lane_settings()
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| H A D | amdgpu_dc_link.c | 1496 struct dc_link_settings link_settings = {0}; in enable_link_dp() local
1510 decide_link_settings(stream, &link_settings); in enable_link_dp()
1519 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; in enable_link_dp()
1525 if (link_settings.link_rate == LINK_RATE_LOW) in enable_link_dp()
1529 &link_settings, in enable_link_dp()
1534 link->cur_link_settings = link_settings; in enable_link_dp()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| H A D | amdgpu_dcn21_link_encoder.c | 177 const struct dc_link_settings *link_settings, in update_cfg_data() argument
189 switch (link_settings->link_rate) { in update_cfg_data()
204 __func__, link_settings->link_rate); in update_cfg_data()
212 struct dc_link_settings *link_settings) in dcn21_link_encoder_get_max_link_cap() argument
219 if (!value && link_settings->lane_count > LANE_COUNT_TWO) in dcn21_link_encoder_get_max_link_cap()
220 link_settings->lane_count = LANE_COUNT_TWO; in dcn21_link_encoder_get_max_link_cap()
284 const struct dc_link_settings *link_settings, in dcn21_link_encoder_enable_dp_output() argument
295 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); in dcn21_link_encoder_enable_dp_output()
299 if (!update_cfg_data(enc10, link_settings, cfg)) in dcn21_link_encoder_enable_dp_output()
302 enc1_configure_encoder(enc10, link_settings); in dcn21_link_encoder_enable_dp_output()
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| H A D | dcn21_link_encoder.h | 89 const struct dc_link_settings *link_settings,
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | amdgpu_dce_link_encoder.c | 486 const struct dc_link_settings *link_settings) in configure_encoder() argument
992 const struct dc_link_settings *link_settings, in dce110_link_encoder_enable_dp_output() argument
1005 configure_encoder(enc110, link_settings); in dce110_link_encoder_enable_dp_output()
1014 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_output()
1044 configure_encoder(enc110, link_settings); in dce110_link_encoder_enable_dp_mst_output()
1053 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_mst_output()
1122 if (!link_settings) { in dce110_link_encoder_dp_set_lane_settings()
1130 cntl.lanes_number = link_settings->link_settings.lane_count; in dce110_link_encoder_dp_set_lane_settings()
1132 cntl.pixel_clock = link_settings->link_settings.link_rate * in dce110_link_encoder_dp_set_lane_settings()
1135 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
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| H A D | dce_link_encoder.h | 221 const struct dc_link_settings *link_settings,
227 const struct dc_link_settings *link_settings,
244 const struct link_training_settings *link_settings);
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| H A D | dce_clk_mgr.c | 532 cfg->link_settings.lane_count = in dce110_fill_display_configs()
534 cfg->link_settings.link_rate = in dce110_fill_display_configs()
536 cfg->link_settings.link_spread = in dce110_fill_display_configs()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_link_encoder.c | 497 const struct dc_link_settings *link_settings) in enc1_configure_encoder() argument
954 const struct dc_link_settings *link_settings, in dcn10_link_encoder_enable_dp_output() argument
967 enc1_configure_encoder(enc10, link_settings); in dcn10_link_encoder_enable_dp_output()
976 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_output()
993 const struct dc_link_settings *link_settings, in dcn10_link_encoder_enable_dp_mst_output() argument
1015 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_mst_output()
1088 if (!link_settings) { in dcn10_link_encoder_dp_set_lane_settings()
1096 cntl.lanes_number = link_settings->link_settings.lane_count; in dcn10_link_encoder_dp_set_lane_settings()
1098 cntl.pixel_clock = link_settings->link_settings.link_rate * in dcn10_link_encoder_dp_set_lane_settings()
1101 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dcn10_link_encoder_dp_set_lane_settings()
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| H A D | dcn10_link_encoder.h | 511 const struct dc_link_settings *link_settings);
525 const struct dc_link_settings *link_settings,
531 const struct dc_link_settings *link_settings,
542 const struct link_training_settings *link_settings);
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| H A D | dcn10_hw_sequencer.h | 59 struct dc_link_settings *link_settings);
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| H A D | amdgpu_dcn10_stream_encoder.c | 937 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { in enc1_stream_encoder_dp_unblank()
954 param->link_settings.link_rate in enc1_stream_encoder_dp_unblank()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_link_encoder.c | 213 const struct dc_link_settings *link_settings, in update_cfg_data() argument
220 for (i = 0; i < link_settings->lane_count; i++) in update_cfg_data()
223 switch (link_settings->link_rate) { in update_cfg_data()
238 __func__, link_settings->link_rate); in update_cfg_data()
247 const struct dc_link_settings *link_settings, in dcn20_link_encoder_enable_dp_output() argument
255 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); in dcn20_link_encoder_enable_dp_output()
259 if (!update_cfg_data(enc10, link_settings, cfg)) in dcn20_link_encoder_enable_dp_output()
262 enc1_configure_encoder(enc10, link_settings); in dcn20_link_encoder_enable_dp_output()
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| H A D | amdgpu_dcn20_stream_encoder.c | 457 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { in enc2_stream_encoder_dp_unblank()
474 param->link_settings.link_rate in enc2_stream_encoder_dp_unblank()
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| H A D | dcn20_hwseq.h | 53 struct dc_link_settings *link_settings);
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| H A D | link_encoder.h | 144 const struct dc_link_settings *link_settings,
147 const struct dc_link_settings *link_settings,
155 const struct link_training_settings *link_settings);
184 struct dc_link_settings *link_settings);
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| H A D | stream_encoder.h | 91 struct dc_link_settings link_settings; member
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/virtual/ |
| H A D | amdgpu_virtual_link_encoder.c | 57 const struct dc_link_settings *link_settings, in virtual_link_encoder_enable_dp_output() argument
62 const struct dc_link_settings *link_settings, in virtual_link_encoder_enable_dp_mst_output() argument
71 const struct link_training_settings *link_settings) {} in virtual_link_encoder_dp_set_lane_settings() argument
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_debugfs.c | 395 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
397 link_lane_settings.link_settings.link_rate = in dp_phy_settings_write()
399 link_lane_settings.link_settings.link_spread = in dp_phy_settings_write()
402 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
404 link_lane_settings.link_settings.link_rate = in dp_phy_settings_write()
406 link_lane_settings.link_settings.link_spread = in dp_phy_settings_write()
411 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { in dp_phy_settings_write()
648 link_training_settings.link_settings = cur_link_settings; in dp_phy_test_pattern_debugfs_write()
656 link_training_settings.link_settings = prefer_link_settings; in dp_phy_test_pattern_debugfs_write()
659 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) in dp_phy_test_pattern_debugfs_write()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | link_hwss.h | 53 const struct dc_link_settings *link_settings);
70 const struct link_training_settings *link_settings,
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| H A D | hw_sequencer.h | 114 struct dc_link_settings *link_settings);
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | amdgpu_dce110_clk_mgr.c | 160 cfg->link_settings.lane_count = in dce110_fill_display_configs()
162 cfg->link_settings.link_rate = in dce110_fill_display_configs()
164 cfg->link_settings.link_spread = in dce110_fill_display_configs()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| H A D | dce110_hw_sequencer.h | 50 struct dc_link_settings *link_settings);
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
| H A D | link_service_types.h | 74 struct dc_link_settings link_settings; member
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dm_services_types.h | 133 struct dc_link_settings link_settings; /* DP only */ member
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