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Searched refs:max_pix_clk (Results 1 – 4 of 4) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
H A Damdgpu_dce_clk_mgr.c172 uint32_t max_pix_clk = 0; in dce_get_max_pixel_clock_for_all_paths() local
185 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
186 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths()
192 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
193 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
196 return max_pix_clk; in dce_get_max_pixel_clock_for_all_paths()
206 int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context); in dce_get_required_clocks_state() local
215 || max_pix_clk > in dce_get_required_clocks_state()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/
H A Damdgpu_dce120_clk_mgr.c95 int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context); in dce12_update_clocks() local
117 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
119 clock_voltage_req.clocks_in_khz = max_pix_clk; in dce12_update_clocks()
120 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c191 uint32_t max_pix_clk = 0; in get_max_pixel_clock_for_all_paths() local
205 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in get_max_pixel_clock_for_all_paths()
211 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in get_max_pixel_clock_for_all_paths()
212 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in get_max_pixel_clock_for_all_paths()
215 return max_pix_clk; in get_max_pixel_clock_for_all_paths()
225 int max_pix_clk = get_max_pixel_clock_for_all_paths(context); in dce_get_required_clocks_state() local
234 || max_pix_clk > in dce_get_required_clocks_state()
760 int max_pix_clk = get_max_pixel_clock_for_all_paths(context); in dce12_update_clocks() local
782 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) { in dce12_update_clocks()
784 clock_voltage_req.clocks_in_khz = max_pix_clk; in dce12_update_clocks()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_link.c2291 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10; in dc_link_validate_mode_timing() local
2301 if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk) in dc_link_validate_mode_timing()