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Searched refs:mmGC_EDC_CTRL (Results 1 – 5 of 5) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega10_powertune.c747 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC…
748 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC…
749 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC…
750 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC…
751 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC…
752 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC…
763 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC…
764 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC…
765 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC…
766 …{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC…
[all …]
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2966 #define mmGC_EDC_CTRL … macro
H A Dgc_9_2_1_offset.h3152 #define mmGC_EDC_CTRL … macro
H A Dgc_9_1_offset.h3196 #define mmGC_EDC_CTRL … macro
H A Dgc_10_1_0_offset.h5448 #define mmGC_EDC_CTRL … macro