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Searched refs:mmGC_USER_RB_BACKEND_DISABLE (Results 1 – 17 of 17) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vi.c552 {mmGC_USER_RB_BACKEND_DISABLE, true},
570 case mmGC_USER_RB_BACKEND_DISABLE: in vi_get_register_value()
H A Damdgpu_cik.c1046 {mmGC_USER_RB_BACKEND_DISABLE, true},
1065 case mmGC_USER_RB_BACKEND_DISABLE: in cik_get_register_value()
H A Damdgpu_si.c1047 case mmGC_USER_RB_BACKEND_DISABLE: in si_get_register_value()
H A Damdgpu_gfx_v6_0.c1336 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v6_0_get_rb_active_bitmap()
1513 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v6_0_setup_rb()
H A Damdgpu_gfx_v7_0.c1634 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1841 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
H A Damdgpu_gfx_v8_0.c3456 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v8_0_get_rb_active_bitmap()
3662 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v8_0_setup_rb()
H A Damdgpu_gfx_v10_0.c1527 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); in gfx_v10_0_get_rb_active_bitmap()
H A Damdgpu_gfx_v9_0.c2364 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); in gfx_v9_0_get_rb_active_bitmap()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h693 #define mmGC_USER_RB_BACKEND_DISABLE 0x26DF macro
H A Dgfx_7_0_d.h689 #define mmGC_USER_RB_BACKEND_DISABLE 0x26df macro
H A Dgfx_7_2_d.h702 #define mmGC_USER_RB_BACKEND_DISABLE 0x26df macro
H A Dgfx_8_0_d.h774 #define mmGC_USER_RB_BACKEND_DISABLE 0x26df macro
H A Dgfx_8_1_d.h774 #define mmGC_USER_RB_BACKEND_DISABLE 0x26df macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1056 #define mmGC_USER_RB_BACKEND_DISABLE macro
H A Dgc_9_2_1_offset.h992 #define mmGC_USER_RB_BACKEND_DISABLE macro
H A Dgc_9_1_offset.h1026 #define mmGC_USER_RB_BACKEND_DISABLE macro
H A Dgc_10_1_0_offset.h2982 #define mmGC_USER_RB_BACKEND_DISABLE macro