Home
last modified time | relevance | path

Searched refs:rb_bufsz (Results 1 – 25 of 35) sorted by relevance

12

/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_uvd_v1_0.c271 uint32_t rb_bufsz; in uvd_v1_0_start() local
382 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
383 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
384 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
H A Dradeon_ni_dma.c196 u32 rb_bufsz; in cayman_dma_resume() local
215 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
216 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
H A Dradeon_r600_dma.c129 u32 rb_bufsz; in r600_dma_resume() local
136 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
137 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
H A Dradeon_cik_sdma.c374 u32 rb_bufsz; in cik_sdma_gfx_resume() local
393 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
394 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
H A Dradeon_r600.c2752 u32 rb_bufsz; in r600_cp_resume() local
2762 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2814 u32 rb_bufsz; in r600_ring_init() local
2818 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2819 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3504 u32 rb_bufsz; in r600_ih_ring_init() local
3507 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3508 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3710 int rb_bufsz; in r600_irq_init() local
3744 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in r600_irq_init()
[all …]
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_ih.c49 u32 rb_bufsz; in amdgpu_ih_ring_init() local
53 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
54 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
H A Damdgpu_si_ih.c68 int rb_bufsz; in si_ih_irq_init() local
80 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
84 (rb_bufsz << 1) | in si_ih_irq_init()
H A Damdgpu_uvd_v4_2.c262 uint32_t rb_bufsz; in uvd_v4_2_start() local
372 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
373 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
374 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
H A Damdgpu_cik_ih.c114 int rb_bufsz; in cik_ih_irq_init() local
132 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
136 (rb_bufsz << 1)); in cik_ih_irq_init()
H A Damdgpu_cz_ih.c115 int rb_bufsz; in cz_ih_irq_init() local
134 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
137 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
H A Damdgpu_iceland_ih.c114 int rb_bufsz; in iceland_ih_irq_init() local
134 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
137 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
H A Damdgpu_tonga_ih.c111 int rb_bufsz; in tonga_ih_irq_init() local
130 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
H A Damdgpu_vcn_v2_5.c760 uint32_t rb_bufsz, tmp; in vcn_v2_5_start_dpg_mode() local
856 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
857 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
892 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
1036 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1037 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1133 uint32_t offset, size, tmp, i, rb_bufsz; in vcn_v2_5_sriov_start() local
1250 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1251 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
H A Damdgpu_uvd_v5_0.c300 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
397 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
H A Damdgpu_navi10_ih.c83 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl() local
91 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
H A Damdgpu_vcn_v2_0.c753 uint32_t rb_bufsz, tmp; in vcn_v2_0_start_dpg_mode() local
843 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
844 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
879 uint32_t rb_bufsz, tmp; in vcn_v2_0_start() local
1004 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1005 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
H A Damdgpu_si_dma.c139 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
150 rb_bufsz = order_base_2(ring->ring_size / 4); in si_dma_start()
151 rb_cntl = rb_bufsz << 1; in si_dma_start()
H A Damdgpu_vcn_v1_0.c788 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_spg_mode() local
907 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_spg_mode()
908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
962 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_dpg_mode() local
1065 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_dpg_mode()
1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
H A Damdgpu_sdma_v2_4.c420 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
444 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
446 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
H A Damdgpu_vega10_ih.c173 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl() local
181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
H A Damdgpu_cik_sdma.c441 u32 rb_bufsz; in cik_sdma_gfx_resume() local
467 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
468 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
H A Damdgpu_gfx_v6_0.c2098 u32 rb_bufsz; in gfx_v6_0_cp_gfx_resume() local
2114 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_gfx_resume()
2115 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_gfx_resume()
2195 u32 rb_bufsz; in gfx_v6_0_cp_compute_resume() local
2203 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2204 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
2223 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2224 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
H A Damdgpu_sdma_v3_0.c655 u32 rb_bufsz; in sdma_v3_0_gfx_resume() local
682 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v3_0_gfx_resume()
684 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
H A Damdgpu_uvd_v6_0.c707 uint32_t rb_bufsz, tmp; in uvd_v6_0_start() local
816 rb_bufsz = order_base_2(ring->ring_size); in uvd_v6_0_start()
817 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
H A Damdgpu_gfx_v10_0.c2774 u32 rb_bufsz; in gfx_v10_0_cp_gfx_resume() local
2790 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v10_0_cp_gfx_resume()
2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
2831 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v10_0_cp_gfx_resume()
2832 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
2833 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
2984 uint32_t rb_bufsz; in gfx_v10_0_gfx_mqd_init() local
3034 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; in gfx_v10_0_gfx_mqd_init()
3036 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_gfx_mqd_init()
[all …]

12