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Searched refs:reg_offset (Results 1 – 25 of 191) sorted by relevance

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/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_arct_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in arct_reg_base_init()
58 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in arct_reg_base_init()
59 adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); in arct_reg_base_init()
[all …]
H A Damdgpu_navi10_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi10_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); in navi10_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); in navi10_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); in navi10_reg_base_init()
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(VCN_BASE.instance[i])); in navi10_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); in navi10_reg_base_init()
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DCN_BASE.instance[i])); in navi10_reg_base_init()
50 adev->reg_offset[SDMA0_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi10_reg_base_init()
51 adev->reg_offset[SDMA1_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi10_reg_base_init()
53 adev->reg_offset[THM_HWIP][i] = (const uint32_t *)(&(THM_BASE.instance[i])); in navi10_reg_base_init()
[all …]
H A Damdgpu_navi12_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi12_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); in navi12_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); in navi12_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); in navi12_reg_base_init()
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i])); in navi12_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); in navi12_reg_base_init()
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i])); in navi12_reg_base_init()
50 adev->reg_offset[SDMA0_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi12_reg_base_init()
51 adev->reg_offset[SDMA1_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi12_reg_base_init()
53 adev->reg_offset[THM_HWIP][i] = (const uint32_t *)(&(THM_BASE.instance[i])); in navi12_reg_base_init()
[all …]
H A Damdgpu_navi14_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi14_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); in navi14_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); in navi14_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); in navi14_reg_base_init()
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i])); in navi14_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); in navi14_reg_base_init()
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i])); in navi14_reg_base_init()
50 adev->reg_offset[SDMA0_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi14_reg_base_init()
51 adev->reg_offset[SDMA1_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi14_reg_base_init()
53 adev->reg_offset[THM_HWIP][i] = (const uint32_t *)(&(THM_BASE.instance[i])); in navi14_reg_base_init()
[all …]
H A Damdgpu_vega10_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
48 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
49 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega10_reg_base_init()
50 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); in vega10_reg_base_init()
55 adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i])); in vega10_reg_base_init()
[all …]
H A Dsoc15_common.h33 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
34 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
38 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
41 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
44 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
47 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
50 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
64 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
102 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
120 uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
[all …]
H A Damdgpu_jpeg_v1_0.c45 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
46 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
64 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
70 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
82 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
103 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_set_patch_ring()
104 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_set_patch_ring()
362 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_reg_wait()
363 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_emit_reg_wait()
398 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_wreg()
[all …]
H A Damdgpu_vega20_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
48 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
49 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); in vega20_reg_base_init()
55 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in vega20_reg_base_init()
56 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega20_reg_base_init()
[all …]
H A Dmmsch_v1_0.h65 uint32_t reg_offset : 28; member
70 uint32_t reg_offset : 20; member
103 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
106 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
113 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
116 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
125 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
128 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
H A Dsoc15.h51 uint32_t reg_offset; member
61 uint32_t reg_offset; member
70 uint32_t reg_offset; member
79 …define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.…
/netbsd/sys/dev/isa/
H A Dnca_isa.c127 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, SCI_ICMD_RST); in nca_isa_test()
128 bus_space_write_1(iot, ioh, reg_offset + C80_ODR, 0); in nca_isa_test()
137 bus_space_write_1(iot, ioh, reg_offset+C80_ICR, 0); in nca_isa_test()
141 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, 0); in nca_isa_test()
146 bus_space_read_1(iot, ioh, reg_offset + C80_RPIR); in nca_isa_test()
154 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_BSR)); in nca_isa_test()
179 bus_size_t base_offset, reg_offset = 0; in nca_isa_find() local
207 reg_offset = 0; in nca_isa_find()
214 reg_offset = C400_5380_REG_OFFSET; in nca_isa_find()
218 reg_offset = 0; in nca_isa_find()
[all …]
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_cik_sdma.c257 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
266 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
268 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
311 uint32_t reg_offset, value; in cik_sdma_ctx_switch_enable() local
316 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
318 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
338 u32 me_cntl, reg_offset; in cik_sdma_enable() local
348 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_enable()
350 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable()
375 u32 reg_offset, wb_offset; in cik_sdma_gfx_resume() local
[all …]
H A Dradeon_ni_dma.c197 u32 reg_offset, wb_offset; in cayman_dma_resume() local
203 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
207 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
220 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
223 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
224 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
227 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
229 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
242 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); in cayman_dma_resume()
244 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume()
[all …]
/netbsd/external/gpl3/gdb/dist/gdb/
H A Dtic6x-linux-tdep.c96 unsigned int reg_offset; in tic6x_linux_rt_sigreturn_init() local
101 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); in tic6x_linux_rt_sigreturn_init()
102 gdb_assert (reg_offset != 0); in tic6x_linux_rt_sigreturn_init()
104 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); in tic6x_linux_rt_sigreturn_init()
109 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); in tic6x_linux_rt_sigreturn_init()
110 gdb_assert (reg_offset != 0); in tic6x_linux_rt_sigreturn_init()
112 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); in tic6x_linux_rt_sigreturn_init()
118 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); in tic6x_linux_rt_sigreturn_init()
119 gdb_assert (reg_offset != 0); in tic6x_linux_rt_sigreturn_init()
121 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); in tic6x_linux_rt_sigreturn_init()
/netbsd/external/gpl3/gdb.old/dist/gdb/
H A Dtic6x-linux-tdep.c96 unsigned int reg_offset; in tic6x_linux_rt_sigreturn_init() local
101 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); in tic6x_linux_rt_sigreturn_init()
102 gdb_assert (reg_offset != 0); in tic6x_linux_rt_sigreturn_init()
104 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); in tic6x_linux_rt_sigreturn_init()
109 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); in tic6x_linux_rt_sigreturn_init()
110 gdb_assert (reg_offset != 0); in tic6x_linux_rt_sigreturn_init()
112 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); in tic6x_linux_rt_sigreturn_init()
118 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); in tic6x_linux_rt_sigreturn_init()
119 gdb_assert (reg_offset != 0); in tic6x_linux_rt_sigreturn_init()
121 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); in tic6x_linux_rt_sigreturn_init()
/netbsd/external/gpl3/gdb/dist/sim/mips/
H A Ddv-tx3904tmr.c382 if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
396 if(reg_offset == 1) /* second byte */ in tx3904tmr_io_write_buffer()
400 else if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
408 if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
416 if(reg_offset == 1) /* second byte */ in tx3904tmr_io_write_buffer()
421 else if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
429 if(reg_offset == 1) /* second byte */ in tx3904tmr_io_write_buffer()
433 else if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
442 if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
462 MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte); in tx3904tmr_io_write_buffer()
[all …]
H A Ddv-tx3904sio.c328 int reg_offset = (address - controller->base_address) % 4; in tx3904sio_io_read_buffer() local
343 if(reg_offset == 0 && tx3904sio_fifo_nonempty(me, & controller->rx_fifo)) in tx3904sio_io_read_buffer()
354 memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1); in tx3904sio_io_read_buffer()
378 int reg_offset = 3 - (address - controller->base_address) % 4; in tx3904sio_io_write_buffer() local
386 SLCR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
399 SDICR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
422 SDISR_CLEAR_FLAG_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
435 SFCR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
444 SBGR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
450 if(reg_offset == 3) /* first byte */ in tx3904sio_io_write_buffer()
/netbsd/external/gpl3/gdb.old/dist/sim/mips/
H A Ddv-tx3904tmr.c382 if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
396 if(reg_offset == 1) /* second byte */ in tx3904tmr_io_write_buffer()
400 else if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
408 if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
416 if(reg_offset == 1) /* second byte */ in tx3904tmr_io_write_buffer()
421 else if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
429 if(reg_offset == 1) /* second byte */ in tx3904tmr_io_write_buffer()
433 else if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
442 if(reg_offset == 0) /* first byte */ in tx3904tmr_io_write_buffer()
462 MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte); in tx3904tmr_io_write_buffer()
[all …]
H A Ddv-tx3904sio.c328 int reg_offset = (address - controller->base_address) % 4; in tx3904sio_io_read_buffer() local
343 if(reg_offset == 0 && tx3904sio_fifo_nonempty(me, & controller->rx_fifo)) in tx3904sio_io_read_buffer()
354 memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1); in tx3904sio_io_read_buffer()
378 int reg_offset = 3 - (address - controller->base_address) % 4; in tx3904sio_io_write_buffer() local
386 SLCR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
399 SDICR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
422 SDISR_CLEAR_FLAG_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
435 SFCR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
444 SBGR_SET_BYTE(controller, reg_offset, write_byte); in tx3904sio_io_write_buffer()
450 if(reg_offset == 3) /* first byte */ in tx3904sio_io_write_buffer()
/netbsd/external/gpl3/gcc.old/dist/gcc/config/nds32/
H A Dnds32.h184 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \ argument
189 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
196 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
200 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \ argument
201 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
206 #define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \ argument
207 ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
215 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \ argument
216 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
219 #define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \ argument
[all …]
/netbsd/external/gpl3/gcc/dist/gcc/config/nds32/
H A Dnds32.h184 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \ argument
189 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
196 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
200 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \ argument
201 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
206 #define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \ argument
207 ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
215 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \ argument
216 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
219 #define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \ argument
[all …]
/netbsd/external/gpl3/gcc/dist/gcc/config/i386/
H A Dwinnt.c938 if (seh->reg_offset[regno] > 0 && seh->reg_offset[regno] <= alloc_offset) in i386_pe_seh_cold_init()
948 alloc_offset - seh->reg_offset[regno]); in i386_pe_seh_cold_init()
970 if (seh->reg_offset[regno] > alloc_offset) in i386_pe_seh_cold_init()
1016 seh->reg_offset[regno] = seh->sp_offset; in seh_emit_push()
1034 seh->reg_offset[regno] = cfa_offset; in seh_emit_save()
1075 HOST_WIDE_INT reg_offset = 0; in seh_cfa_adjust_cfa() local
1083 reg_offset = INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1088 reg_offset = -INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1102 seh->cfa_offset -= reg_offset; in seh_cfa_adjust_cfa()
1123 HOST_WIDE_INT reg_offset; in seh_cfa_offset() local
[all …]
H A Dwinnt.cc937 if (seh->reg_offset[regno] > 0 && seh->reg_offset[regno] <= alloc_offset) in i386_pe_seh_cold_init()
947 alloc_offset - seh->reg_offset[regno]); in i386_pe_seh_cold_init()
969 if (seh->reg_offset[regno] > alloc_offset) in i386_pe_seh_cold_init()
1015 seh->reg_offset[regno] = seh->sp_offset; in seh_emit_push()
1033 seh->reg_offset[regno] = cfa_offset; in seh_emit_save()
1074 HOST_WIDE_INT reg_offset = 0; in seh_cfa_adjust_cfa() local
1082 reg_offset = INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1087 reg_offset = -INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1101 seh->cfa_offset -= reg_offset; in seh_cfa_adjust_cfa()
1122 HOST_WIDE_INT reg_offset; in seh_cfa_offset() local
[all …]
/netbsd/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Dwinnt.c938 if (seh->reg_offset[regno] > 0 && seh->reg_offset[regno] <= alloc_offset) in i386_pe_seh_cold_init()
948 alloc_offset - seh->reg_offset[regno]); in i386_pe_seh_cold_init()
970 if (seh->reg_offset[regno] > alloc_offset) in i386_pe_seh_cold_init()
1016 seh->reg_offset[regno] = seh->sp_offset; in seh_emit_push()
1034 seh->reg_offset[regno] = cfa_offset; in seh_emit_save()
1075 HOST_WIDE_INT reg_offset = 0; in seh_cfa_adjust_cfa() local
1083 reg_offset = INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1088 reg_offset = -INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1102 seh->cfa_offset -= reg_offset; in seh_cfa_adjust_cfa()
1123 HOST_WIDE_INT reg_offset; in seh_cfa_offset() local
[all …]
/netbsd/external/gpl3/gcc.old/dist/libgcc/config/mips/
H A Dlinux-unwind.h51 _Unwind_Ptr new_cfa, reg_offset; in mips_fallback_frame_state() local
100 reg_offset = 4; in mips_fallback_frame_state()
102 reg_offset = 0; in mips_fallback_frame_state()
108 = (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa; in mips_fallback_frame_state()

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