1 /* $NetBSD: dwc2_core.h,v 1.9 2018/08/08 07:20:44 simonb Exp $ */
2
3 /*
4 * core.h - DesignWare HS OTG Controller common declarations
5 *
6 * Copyright (C) 2004-2013 Synopsys, Inc.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The names of the above-listed copyright holders may not be used
18 * to endorse or promote products derived from this software without
19 * specific prior written permission.
20 *
21 * ALTERNATIVELY, this software may be distributed under the terms of the
22 * GNU General Public License ("GPL") as published by the Free Software
23 * Foundation; either version 2 of the License, or (at your option) any
24 * later version.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef __DWC2_CORE_H__
40 #define __DWC2_CORE_H__
41
42 #include <sys/stdint.h>
43 #include <sys/pool.h>
44 #include <sys/queue.h>
45 #include <sys/device.h>
46
47 #include <machine/intr.h>
48 #include <sys/bus.h>
49
50 #include "dwc2_hw.h"
51
52 /* Maximum number of Endpoints/HostChannels */
53 #define MAX_EPS_CHANNELS 16
54
55 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56
57 /* dwc2-hsotg declarations */
58 static const char * const dwc2_hsotg_supply_names[] = {
59 "vusb_d", /* digital USB supply, 1.2V */
60 "vusb_a", /* analog USB supply, 1.1V */
61 };
62
63 /*
64 * EP0_MPS_LIMIT
65 *
66 * Unfortunately there seems to be a limit of the amount of data that can
67 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
68 * packets (which practically means 1 packet and 63 bytes of data) when the
69 * MPS is set to 64.
70 *
71 * This means if we are wanting to move >127 bytes of data, we need to
72 * split the transactions up, but just doing one packet at a time does
73 * not work (this may be an implicit DATA0 PID on first packet of the
74 * transaction) and doing 2 packets is outside the controller's limits.
75 *
76 * If we try to lower the MPS size for EP0, then no transfers work properly
77 * for EP0, and the system will fail basic enumeration. As no cause for this
78 * has currently been found, we cannot support any large IN transfers for
79 * EP0.
80 */
81 #define EP0_MPS_LIMIT 64
82
83 struct dwc2_hsotg;
84 struct dwc2_hsotg_req;
85
86 /**
87 * struct dwc2_hsotg_ep - driver endpoint definition.
88 * @ep: The gadget layer representation of the endpoint.
89 * @name: The driver generated name for the endpoint.
90 * @queue: Queue of requests for this endpoint.
91 * @parent: Reference back to the parent device structure.
92 * @req: The current request that the endpoint is processing. This is
93 * used to indicate an request has been loaded onto the endpoint
94 * and has yet to be completed (maybe due to data move, or simply
95 * awaiting an ack from the core all the data has been completed).
96 * @debugfs: File entry for debugfs file for this endpoint.
97 * @lock: State lock to protect contents of endpoint.
98 * @dir_in: Set to true if this endpoint is of the IN direction, which
99 * means that it is sending data to the Host.
100 * @index: The index for the endpoint registers.
101 * @mc: Multi Count - number of transactions per microframe
102 * @interval - Interval for periodic endpoints
103 * @name: The name array passed to the USB core.
104 * @halted: Set if the endpoint has been halted.
105 * @periodic: Set if this is a periodic ep, such as Interrupt
106 * @isochronous: Set if this is a isochronous ep
107 * @send_zlp: Set if we need to send a zero-length packet.
108 * @total_data: The total number of data bytes done.
109 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
110 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
111 * @last_load: The offset of data for the last start of request.
112 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
113 *
114 * This is the driver's state for each registered enpoint, allowing it
115 * to keep track of transactions that need doing. Each endpoint has a
116 * lock to protect the state, to try and avoid using an overall lock
117 * for the host controller as much as possible.
118 *
119 * For periodic IN endpoints, we have fifo_size and fifo_load to try
120 * and keep track of the amount of data in the periodic FIFO for each
121 * of these as we don't have a status register that tells us how much
122 * is in each of them. (note, this may actually be useless information
123 * as in shared-fifo mode periodic in acts like a single-frame packet
124 * buffer than a fifo)
125 */
126 struct dwc2_hsotg_ep {
127 struct usb_ep ep;
128 struct list_head queue;
129 struct dwc2_hsotg *parent;
130 struct dwc2_hsotg_req *req;
131 struct dentry *debugfs;
132
133 unsigned long total_data;
134 unsigned int size_loaded;
135 unsigned int last_load;
136 unsigned int fifo_load;
137 unsigned short fifo_size;
138 unsigned short fifo_index;
139
140 unsigned char dir_in;
141 unsigned char index;
142 unsigned char mc;
143 unsigned char interval;
144
145 unsigned int halted:1;
146 unsigned int periodic:1;
147 unsigned int isochronous:1;
148 unsigned int send_zlp:1;
149 unsigned int has_correct_parity:1;
150
151 char name[10];
152 };
153
154 /**
155 * struct dwc2_hsotg_req - data transfer request
156 * @req: The USB gadget request
157 * @queue: The list of requests for the endpoint this is queued for.
158 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
159 */
160 struct dwc2_hsotg_req {
161 struct usb_request req;
162 struct list_head queue;
163 void *saved_req_buf;
164 };
165
166 #define call_gadget(_hs, _entry) \
167 do { \
168 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
169 (_hs)->driver && (_hs)->driver->_entry) { \
170 spin_unlock(&_hs->lock); \
171 (_hs)->driver->_entry(&(_hs)->gadget); \
172 spin_lock(&_hs->lock); \
173 } \
174 } while (0)
175 #else
176 #define call_gadget(_hs, _entry) do {} while (0)
177 #endif
178
179 struct dwc2_hsotg;
180 struct dwc2_host_chan;
181
182 /* Device States */
183 enum dwc2_lx_state {
184 DWC2_L0, /* On state */
185 DWC2_L1, /* LPM sleep state */
186 DWC2_L2, /* USB suspend state */
187 DWC2_L3, /* Off state */
188 };
189
190 /*
191 * Gadget periodic tx fifo sizes as used by legacy driver
192 * EP0 is not included
193 */
194 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
195 768, 0, 0, 0, 0, 0, 0, 0}
196
197 /* Gadget ep0 states */
198 enum dwc2_ep0_state {
199 DWC2_EP0_SETUP,
200 DWC2_EP0_DATA_IN,
201 DWC2_EP0_DATA_OUT,
202 DWC2_EP0_STATUS_IN,
203 DWC2_EP0_STATUS_OUT,
204 };
205
206 /**
207 * struct dwc2_core_params - Parameters for configuring the core
208 *
209 * @otg_cap: Specifies the OTG capabilities.
210 * 0 - HNP and SRP capable
211 * 1 - SRP Only capable
212 * 2 - No HNP/SRP capable (always available)
213 * Defaults to best available option (0, 1, then 2)
214 * @otg_ver: OTG version supported
215 * 0 - 1.3 (default)
216 * 1 - 2.0
217 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
218 * the data FIFOs. The driver will automatically detect the
219 * value for this parameter if none is specified.
220 * 0 - Slave (always available)
221 * 1 - DMA (default, if available)
222 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
223 * address DMA mode or descriptor DMA mode for accessing
224 * the data FIFOs. The driver will automatically detect the
225 * value for this if none is specified.
226 * 0 - Address DMA
227 * 1 - Descriptor DMA (default, if available)
228 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
229 * address DMA mode or descriptor DMA mode for accessing
230 * the data FIFOs in Full Speed mode only. The driver
231 * will automatically detect the value for this if none is
232 * specified.
233 * 0 - Address DMA
234 * 1 - Descriptor DMA in FS (default, if available)
235 * @speed: Specifies the maximum speed of operation in host and
236 * device mode. The actual speed depends on the speed of
237 * the attached device and the value of phy_type.
238 * 0 - High Speed
239 * (default when phy_type is UTMI+ or ULPI)
240 * 1 - Full Speed
241 * (default when phy_type is Full Speed)
242 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
243 * 1 - Allow dynamic FIFO sizing (default, if available)
244 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
245 * are enabled
246 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
247 * dynamic FIFO sizing is enabled
248 * 16 to 32768
249 * Actual maximum value is autodetected and also
250 * the default.
251 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
252 * in host mode when dynamic FIFO sizing is enabled
253 * 16 to 32768
254 * Actual maximum value is autodetected and also
255 * the default.
256 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
257 * host mode when dynamic FIFO sizing is enabled
258 * 16 to 32768
259 * Actual maximum value is autodetected and also
260 * the default.
261 * @max_transfer_size: The maximum transfer size supported, in bytes
262 * 2047 to 65,535
263 * Actual maximum value is autodetected and also
264 * the default.
265 * @max_packet_count: The maximum number of packets in a transfer
266 * 15 to 511
267 * Actual maximum value is autodetected and also
268 * the default.
269 * @host_channels: The number of host channel registers to use
270 * 1 to 16
271 * Actual maximum value is autodetected and also
272 * the default.
273 * @phy_type: Specifies the type of PHY interface to use. By default,
274 * the driver will automatically detect the phy_type.
275 * 0 - Full Speed Phy
276 * 1 - UTMI+ Phy
277 * 2 - ULPI Phy
278 * Defaults to best available option (2, 1, then 0)
279 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
280 * is applicable for a phy_type of UTMI+ or ULPI. (For a
281 * ULPI phy_type, this parameter indicates the data width
282 * between the MAC and the ULPI Wrapper.) Also, this
283 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
284 * parameter was set to "8 and 16 bits", meaning that the
285 * core has been configured to work at either data path
286 * width.
287 * 8 or 16 (default 16 if available)
288 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
289 * data rate. This parameter is only applicable if phy_type
290 * is ULPI.
291 * 0 - single data rate ULPI interface with 8 bit wide
292 * data bus (default)
293 * 1 - double data rate ULPI interface with 4 bit wide
294 * data bus
295 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
296 * external supply to drive the VBus
297 * 0 - Internal supply (default)
298 * 1 - External supply
299 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
300 * speed PHY. This parameter is only applicable if phy_type
301 * is FS.
302 * 0 - No (default)
303 * 1 - Yes
304 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
305 * 0 - No (default)
306 * 1 - Yes
307 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
308 * when attached to a Full Speed or Low Speed device in
309 * host mode.
310 * 0 - Don't support low power mode (default)
311 * 1 - Support low power mode
312 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
313 * when connected to a Low Speed device in host
314 * mode. This parameter is applicable only if
315 * host_support_fs_ls_low_power is enabled.
316 * 0 - 48 MHz
317 * (default when phy_type is UTMI+ or ULPI)
318 * 1 - 6 MHz
319 * (default when phy_type is Full Speed)
320 * @ts_dline: Enable Term Select Dline pulsing
321 * 0 - No (default)
322 * 1 - Yes
323 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
324 * 0 - No (default for core < 2.92a)
325 * 1 - Yes (default for core >= 2.92a)
326 * @ahbcfg: This field allows the default value of the GAHBCFG
327 * register to be overridden
328 * -1 - GAHBCFG value will be set to 0x06
329 * (INCR4, default)
330 * all others - GAHBCFG value will be overridden with
331 * this value
332 * Not all bits can be controlled like this, the
333 * bits defined by GAHBCFG_CTRL_MASK are controlled
334 * by the driver and are ignored in this
335 * configuration value.
336 * @uframe_sched: True to enable the microframe scheduler
337 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
338 * Disable CONIDSTSCHNG controller interrupt in such
339 * case.
340 * 0 - No (default)
341 * 1 - Yes
342 * @hibernation: Specifies whether the controller support hibernation.
343 * If hibernation is enabled, the controller will enter
344 * hibernation in both peripheral and host mode when
345 * needed.
346 * 0 - No (default)
347 * 1 - Yes
348 *
349 * The following parameters may be specified when starting the module. These
350 * parameters define how the DWC_otg controller should be configured. A
351 * value of -1 (or any other out of range value) for any parameter means
352 * to read the value from hardware (if possible) or use the builtin
353 * default described above.
354 */
355 struct dwc2_core_params {
356 /*
357 * Don't add any non-int members here, this will break
358 * dwc2_set_all_params!
359 */
360 int otg_cap;
361 int otg_ver;
362 int dma_enable;
363 int dma_desc_enable;
364 int dma_desc_fs_enable;
365 int speed;
366 int enable_dynamic_fifo;
367 int en_multiple_tx_fifo;
368 int host_rx_fifo_size;
369 int host_nperio_tx_fifo_size;
370 int host_perio_tx_fifo_size;
371 int max_transfer_size;
372 int max_packet_count;
373 int host_channels;
374 int phy_type;
375 int phy_utmi_width;
376 int phy_ulpi_ddr;
377 int phy_ulpi_ext_vbus;
378 int i2c_enable;
379 int ulpi_fs_ls;
380 int host_support_fs_ls_low_power;
381 int host_ls_low_power_phy_clk;
382 int ts_dline;
383 int reload_ctl;
384 int ahbcfg;
385 int uframe_sched;
386 int external_id_pin_ctl;
387 int hibernation;
388 };
389
390 /**
391 * struct dwc2_hw_params - Autodetected parameters.
392 *
393 * These parameters are the various parameters read from hardware
394 * registers during initialization. They typically contain the best
395 * supported or maximum value that can be configured in the
396 * corresponding dwc2_core_params value.
397 *
398 * The values that are not in dwc2_core_params are documented below.
399 *
400 * @op_mode Mode of Operation
401 * 0 - HNP- and SRP-Capable OTG (Host & Device)
402 * 1 - SRP-Capable OTG (Host & Device)
403 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
404 * 3 - SRP-Capable Device
405 * 4 - Non-OTG Device
406 * 5 - SRP-Capable Host
407 * 6 - Non-OTG Host
408 * @arch Architecture
409 * 0 - Slave only
410 * 1 - External DMA
411 * 2 - Internal DMA
412 * @power_optimized Are power optimizations enabled?
413 * @num_dev_ep Number of device endpoints available
414 * @num_dev_perio_in_ep Number of device periodic IN endpoints
415 * available
416 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
417 * Depth
418 * 0 to 30
419 * @host_perio_tx_q_depth
420 * Host Mode Periodic Request Queue Depth
421 * 2, 4 or 8
422 * @nperio_tx_q_depth
423 * Non-Periodic Request Queue Depth
424 * 2, 4 or 8
425 * @hs_phy_type High-speed PHY interface type
426 * 0 - High-speed interface not supported
427 * 1 - UTMI+
428 * 2 - ULPI
429 * 3 - UTMI+ and ULPI
430 * @fs_phy_type Full-speed PHY interface type
431 * 0 - Full speed interface not supported
432 * 1 - Dedicated full speed interface
433 * 2 - FS pins shared with UTMI+ pins
434 * 3 - FS pins shared with ULPI pins
435 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
436 * @utmi_phy_data_width UTMI+ PHY data width
437 * 0 - 8 bits
438 * 1 - 16 bits
439 * 2 - 8 or 16 bits
440 * @snpsid: Value from SNPSID register
441 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
442 */
443 struct dwc2_hw_params {
444 unsigned op_mode:3;
445 unsigned arch:2;
446 unsigned dma_desc_enable:1;
447 unsigned dma_desc_fs_enable:1;
448 unsigned enable_dynamic_fifo:1;
449 unsigned en_multiple_tx_fifo:1;
450 unsigned host_rx_fifo_size:16;
451 unsigned host_nperio_tx_fifo_size:16;
452 unsigned dev_nperio_tx_fifo_size:16;
453 unsigned host_perio_tx_fifo_size:16;
454 unsigned nperio_tx_q_depth:3;
455 unsigned host_perio_tx_q_depth:3;
456 unsigned dev_token_q_depth:5;
457 unsigned max_transfer_size:26;
458 unsigned max_packet_count:11;
459 unsigned host_channels:5;
460 unsigned hs_phy_type:2;
461 unsigned fs_phy_type:2;
462 unsigned i2c_enable:1;
463 unsigned num_dev_ep:4;
464 unsigned num_dev_perio_in_ep:4;
465 unsigned total_fifo_size:16;
466 unsigned power_optimized:1;
467 unsigned utmi_phy_data_width:2;
468 u32 snpsid;
469 u32 dev_ep_dirs;
470 };
471
472 /* Size of control and EP0 buffers */
473 #define DWC2_CTRL_BUFF_SIZE 8
474
475 /**
476 * struct dwc2_gregs_backup - Holds global registers state before entering partial
477 * power down
478 * @gotgctl: Backup of GOTGCTL register
479 * @gintmsk: Backup of GINTMSK register
480 * @gahbcfg: Backup of GAHBCFG register
481 * @gusbcfg: Backup of GUSBCFG register
482 * @grxfsiz: Backup of GRXFSIZ register
483 * @gnptxfsiz: Backup of GNPTXFSIZ register
484 * @gi2cctl: Backup of GI2CCTL register
485 * @hptxfsiz: Backup of HPTXFSIZ register
486 * @gdfifocfg: Backup of GDFIFOCFG register
487 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
488 * @gpwrdn: Backup of GPWRDN register
489 */
490 struct dwc2_gregs_backup {
491 u32 gotgctl;
492 u32 gintmsk;
493 u32 gahbcfg;
494 u32 gusbcfg;
495 u32 grxfsiz;
496 u32 gnptxfsiz;
497 u32 gi2cctl;
498 u32 hptxfsiz;
499 u32 pcgcctl;
500 u32 gdfifocfg;
501 u32 dtxfsiz[MAX_EPS_CHANNELS];
502 u32 gpwrdn;
503 bool valid;
504 };
505
506 /**
507 * struct dwc2_dregs_backup - Holds device registers state before entering partial
508 * power down
509 * @dcfg: Backup of DCFG register
510 * @dctl: Backup of DCTL register
511 * @daintmsk: Backup of DAINTMSK register
512 * @diepmsk: Backup of DIEPMSK register
513 * @doepmsk: Backup of DOEPMSK register
514 * @diepctl: Backup of DIEPCTL register
515 * @dieptsiz: Backup of DIEPTSIZ register
516 * @diepdma: Backup of DIEPDMA register
517 * @doepctl: Backup of DOEPCTL register
518 * @doeptsiz: Backup of DOEPTSIZ register
519 * @doepdma: Backup of DOEPDMA register
520 */
521 struct dwc2_dregs_backup {
522 u32 dcfg;
523 u32 dctl;
524 u32 daintmsk;
525 u32 diepmsk;
526 u32 doepmsk;
527 u32 diepctl[MAX_EPS_CHANNELS];
528 u32 dieptsiz[MAX_EPS_CHANNELS];
529 u32 diepdma[MAX_EPS_CHANNELS];
530 u32 doepctl[MAX_EPS_CHANNELS];
531 u32 doeptsiz[MAX_EPS_CHANNELS];
532 u32 doepdma[MAX_EPS_CHANNELS];
533 bool valid;
534 };
535
536 /**
537 * struct dwc2_hregs_backup - Holds host registers state before entering partial
538 * power down
539 * @hcfg: Backup of HCFG register
540 * @haintmsk: Backup of HAINTMSK register
541 * @hcintmsk: Backup of HCINTMSK register
542 * @hptr0: Backup of HPTR0 register
543 * @hfir: Backup of HFIR register
544 */
545 struct dwc2_hregs_backup {
546 u32 hcfg;
547 u32 haintmsk;
548 u32 hcintmsk[MAX_EPS_CHANNELS];
549 u32 hprt0;
550 u32 hfir;
551 bool valid;
552 };
553
554 /**
555 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
556 * and periodic schedules
557 *
558 * These are common for both host and peripheral modes:
559 *
560 * @dev: The struct device pointer
561 * @regs: Pointer to controller regs
562 * @hw_params: Parameters that were autodetected from the
563 * hardware registers
564 * @core_params: Parameters that define how the core should be configured
565 * @op_state: The operational State, during transitions (a_host=>
566 * a_peripheral and b_device=>b_host) this may not match
567 * the core, but allows the software to determine
568 * transitions
569 * @dr_mode: Requested mode of operation, one of following:
570 * - USB_DR_MODE_PERIPHERAL
571 * - USB_DR_MODE_HOST
572 * - USB_DR_MODE_OTG
573 * @hcd_enabled Host mode sub-driver initialization indicator.
574 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
575 * @ll_hw_enabled Status of low-level hardware resources.
576 * @phy: The otg phy transceiver structure for phy control.
577 * @uphy: The otg phy transceiver structure for old USB phy control.
578 * @plat: The platform specific configuration data. This can be removed once
579 * all SoCs support usb transceiver.
580 * @supplies: Definition of USB power supplies
581 * @phyif: PHY interface width
582 * @lock: Spinlock that protects all the driver data structures
583 * @priv: Stores a pointer to the struct usb_hcd
584 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
585 * transfer are in process of being queued
586 * @srp_success: Stores status of SRP request in the case of a FS PHY
587 * with an I2C interface
588 * @wq_otg: Workqueue object used for handling of some interrupts
589 * @wf_otg: Work object for handling Connector ID Status Change
590 * interrupt
591 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
592 * @lx_state: Lx state of connected device
593 * @gregs_backup: Backup of global registers during suspend
594 * @dregs_backup: Backup of device registers during suspend
595 * @hregs_backup: Backup of host registers during suspend
596 *
597 * These are for host mode:
598 *
599 * @flags: Flags for handling root port state changes
600 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
601 * Transfers associated with these QHs are not currently
602 * assigned to a host channel.
603 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
604 * Transfers associated with these QHs are currently
605 * assigned to a host channel.
606 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
607 * non-periodic schedule
608 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
609 * list of QHs for periodic transfers that are _not_
610 * scheduled for the next frame. Each QH in the list has an
611 * interval counter that determines when it needs to be
612 * scheduled for execution. This scheduling mechanism
613 * allows only a simple calculation for periodic bandwidth
614 * used (i.e. must assume that all periodic transfers may
615 * need to execute in the same frame). However, it greatly
616 * simplifies scheduling and should be sufficient for the
617 * vast majority of OTG hosts, which need to connect to a
618 * small number of peripherals at one time. Items move from
619 * this list to periodic_sched_ready when the QH interval
620 * counter is 0 at SOF.
621 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
622 * the next frame, but have not yet been assigned to host
623 * channels. Items move from this list to
624 * periodic_sched_assigned as host channels become
625 * available during the current frame.
626 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
627 * frame that are assigned to host channels. Items move
628 * from this list to periodic_sched_queued as the
629 * transactions for the QH are queued to the DWC_otg
630 * controller.
631 * @periodic_sched_queued: List of periodic QHs that have been queued for
632 * execution. Items move from this list to either
633 * periodic_sched_inactive or periodic_sched_ready when the
634 * channel associated with the transfer is released. If the
635 * interval for the QH is 1, the item moves to
636 * periodic_sched_ready because it must be rescheduled for
637 * the next frame. Otherwise, the item moves to
638 * periodic_sched_inactive.
639 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
640 * This value is in microseconds per (micro)frame. The
641 * assumption is that all periodic transfers may occur in
642 * the same (micro)frame.
643 * @frame_usecs: Internal variable used by the microframe scheduler
644 * @frame_number: Frame number read from the core at SOF. The value ranges
645 * from 0 to HFNUM_MAX_FRNUM.
646 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
647 * SOF enable/disable.
648 * @free_hc_list: Free host channels in the controller. This is a list of
649 * struct dwc2_host_chan items.
650 * @periodic_channels: Number of host channels assigned to periodic transfers.
651 * Currently assuming that there is a dedicated host
652 * channel for each periodic transaction and at least one
653 * host channel is available for non-periodic transactions.
654 * @non_periodic_channels: Number of host channels assigned to non-periodic
655 * transfers
656 * @available_host_channels Number of host channels available for the microframe
657 * scheduler to use
658 * @hc_ptr_array: Array of pointers to the host channel descriptors.
659 * Allows accessing a host channel descriptor given the
660 * host channel number. This is useful in interrupt
661 * handlers.
662 * @status_buf: Buffer used for data received during the status phase of
663 * a control transfer.
664 * @status_buf_dma: DMA address for status_buf
665 * @start_work: Delayed work for handling host A-cable connection
666 * @reset_work: Delayed work for handling a port reset
667 * @otg_port: OTG port number
668 * @frame_list: Frame list
669 * @frame_list_dma: Frame list DMA address
670 * @frame_list_sz: Frame list size
671 * @desc_gen_cache: Kmem cache for generic descriptors
672 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
673 *
674 * These are for peripheral mode:
675 *
676 * @driver: USB gadget driver
677 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
678 * @num_of_eps: Number of available EPs (excluding EP0)
679 * @debug_root: Root directrory for debugfs.
680 * @debug_file: Main status file for debugfs.
681 * @debug_testmode: Testmode status file for debugfs.
682 * @debug_fifo: FIFO status file for debugfs.
683 * @ep0_reply: Request used for ep0 reply.
684 * @ep0_buff: Buffer for EP0 reply data, if needed.
685 * @ctrl_buff: Buffer for EP0 control requests.
686 * @ctrl_req: Request for EP0 control packets.
687 * @ep0_state: EP0 control transfers state
688 * @test_mode: USB test mode requested by the host
689 * @eps: The endpoints being supplied to the gadget framework
690 * @g_using_dma: Indicate if dma usage is enabled
691 * @g_rx_fifo_sz: Contains rx fifo size value
692 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
693 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
694 */
695 struct dwc2_hsotg {
696 device_t dev;
697 struct dwc2_softc *hsotg_sc;
698 /** Params detected from hardware */
699 struct dwc2_hw_params hw_params;
700 /** Params to actually use */
701 struct dwc2_core_params *core_params;
702 enum usb_otg_state op_state;
703 enum usb_dr_mode dr_mode;
704 unsigned int hcd_enabled:1;
705 unsigned int gadget_enabled:1;
706 unsigned int ll_hw_enabled:1;
707
708 spinlock_t lock;
709 void *priv;
710 struct usb_phy *uphy;
711 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
712 struct phy *phy;
713 struct usb_phy *uphy;
714 struct dwc2_hsotg_plat *plat;
715 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
716 u32 phyif;
717
718 int irq;
719 struct clk *clk;
720 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
721
722 unsigned int queuing_high_bandwidth:1;
723 unsigned int srp_success:1;
724
725 struct workqueue_struct *wq_otg;
726 struct work_struct wf_otg;
727 struct callout wkp_timer;
728 enum dwc2_lx_state lx_state;
729 struct dwc2_gregs_backup gr_backup;
730 struct dwc2_dregs_backup dr_backup;
731 struct dwc2_hregs_backup hr_backup;
732
733 struct dentry *debug_root;
734 struct debugfs_regset32 *regset;
735
736 /* DWC OTG HW Release versions */
737 #define DWC2_CORE_REV_2_71a 0x4f54271a
738 #define DWC2_CORE_REV_2_90a 0x4f54290a
739 #define DWC2_CORE_REV_2_92a 0x4f54292a
740 #define DWC2_CORE_REV_2_94a 0x4f54294a
741 #define DWC2_CORE_REV_3_00a 0x4f54300a
742
743 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
744 union dwc2_hcd_internal_flags {
745 u32 d32;
746 struct {
747 unsigned port_connect_status_change:1;
748 unsigned port_connect_status:1;
749 unsigned port_reset_change:1;
750 unsigned port_enable_change:1;
751 unsigned port_suspend_change:1;
752 unsigned port_over_current_change:1;
753 unsigned port_l1_change:1;
754 unsigned reserved:25;
755 } b;
756 } flags;
757
758 struct list_head non_periodic_sched_inactive;
759 struct list_head non_periodic_sched_waiting;
760 struct list_head non_periodic_sched_active;
761 struct list_head *non_periodic_qh_ptr;
762 struct list_head periodic_sched_inactive;
763 struct list_head periodic_sched_ready;
764 struct list_head periodic_sched_assigned;
765 struct list_head periodic_sched_queued;
766 u16 periodic_usecs;
767 u16 frame_usecs[8];
768 u16 frame_number;
769 u16 periodic_qh_count;
770 bool bus_suspended;
771 bool new_connection;
772
773 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
774 #define FRAME_NUM_ARRAY_SIZE 1000
775 u16 last_frame_num;
776 u16 *frame_num_array;
777 u16 *last_frame_num_array;
778 int frame_num_idx;
779 int dumped_frame_num_array;
780 #endif
781
782 struct list_head free_hc_list;
783 int periodic_channels;
784 int non_periodic_channels;
785 int available_host_channels;
786 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
787 usb_dma_t status_buf_usbdma;
788 u8 *status_buf;
789 dma_addr_t status_buf_dma;
790 #define DWC2_HCD_STATUS_BUF_SIZE 64
791
792 struct delayed_work start_work;
793 struct delayed_work reset_work;
794 u8 otg_port;
795 usb_dma_t frame_list_usbdma;
796 u32 *frame_list;
797 dma_addr_t frame_list_dma;
798 u32 frame_list_sz;
799 struct kmem_cache *desc_gen_cache;
800 struct kmem_cache *desc_hsisoc_cache;
801
802 #ifdef DEBUG
803 u32 frrem_samples;
804 u64 frrem_accum;
805
806 u32 hfnum_7_samples_a;
807 u64 hfnum_7_frrem_accum_a;
808 u32 hfnum_0_samples_a;
809 u64 hfnum_0_frrem_accum_a;
810 u32 hfnum_other_samples_a;
811 u64 hfnum_other_frrem_accum_a;
812
813 u32 hfnum_7_samples_b;
814 u64 hfnum_7_frrem_accum_b;
815 u32 hfnum_0_samples_b;
816 u64 hfnum_0_frrem_accum_b;
817 u32 hfnum_other_samples_b;
818 u64 hfnum_other_frrem_accum_b;
819 #endif
820 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
821
822 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
823 /* Gadget structures */
824 struct usb_gadget_driver *driver;
825 int fifo_mem;
826 unsigned int dedicated_fifos:1;
827 unsigned char num_of_eps;
828 u32 fifo_map;
829
830 struct usb_request *ep0_reply;
831 struct usb_request *ctrl_req;
832 void *ep0_buff;
833 void *ctrl_buff;
834 enum dwc2_ep0_state ep0_state;
835 u8 test_mode;
836
837 struct usb_gadget gadget;
838 unsigned int enabled:1;
839 unsigned int connected:1;
840 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
841 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
842 u32 g_using_dma;
843 u32 g_rx_fifo_sz;
844 u32 g_np_g_tx_fifo_sz;
845 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
846 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
847 };
848
849 /* Reasons for halting a host channel */
850 enum dwc2_halt_status {
851 DWC2_HC_XFER_NO_HALT_STATUS,
852 DWC2_HC_XFER_COMPLETE,
853 DWC2_HC_XFER_URB_COMPLETE,
854 DWC2_HC_XFER_ACK,
855 DWC2_HC_XFER_NAK,
856 DWC2_HC_XFER_NYET,
857 DWC2_HC_XFER_STALL,
858 DWC2_HC_XFER_XACT_ERR,
859 DWC2_HC_XFER_FRAME_OVERRUN,
860 DWC2_HC_XFER_BABBLE_ERR,
861 DWC2_HC_XFER_DATA_TOGGLE_ERR,
862 DWC2_HC_XFER_AHB_ERR,
863 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
864 DWC2_HC_XFER_URB_DEQUEUE,
865 };
866
867 /*
868 * The following functions support initialization of the core driver component
869 * and the DWC_otg controller
870 */
871 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
872 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
873 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
874 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
875 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
876
877 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
878
879 /*
880 * Host core Functions.
881 * The following functions support managing the DWC_otg controller in host
882 * mode.
883 */
884 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
885 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
886 enum dwc2_halt_status halt_status);
887 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
888 struct dwc2_host_chan *chan);
889 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
890 struct dwc2_host_chan *chan);
891 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
892 struct dwc2_host_chan *chan);
893 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
894 struct dwc2_host_chan *chan);
895 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
896 struct dwc2_host_chan *chan);
897 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
898 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
899
900 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
901 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
902
903 /*
904 * Common core Functions.
905 * The following functions support managing the DWC_otg controller in either
906 * device or host mode.
907 */
908 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
909 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
910 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
911
912 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
913 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
914 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
915
916 /* This function should be called on every hardware interrupt. */
917 extern irqreturn_t dwc2_handle_common_intr(void *dev);
918
919 /* OTG Core Parameters */
920
921 /*
922 * Specifies the OTG capabilities. The driver will automatically
923 * detect the value for this parameter if none is specified.
924 * 0 - HNP and SRP capable (default)
925 * 1 - SRP Only capable
926 * 2 - No HNP/SRP capable
927 */
928 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
929 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
930 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
931 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
932
933 /*
934 * Specifies whether to use slave or DMA mode for accessing the data
935 * FIFOs. The driver will automatically detect the value for this
936 * parameter if none is specified.
937 * 0 - Slave
938 * 1 - DMA (default, if available)
939 */
940 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
941
942 /*
943 * When DMA mode is enabled specifies whether to use
944 * address DMA or DMA Descritor mode for accessing the data
945 * FIFOs in device mode. The driver will automatically detect
946 * the value for this parameter if none is specified.
947 * 0 - address DMA
948 * 1 - DMA Descriptor(default, if available)
949 */
950 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
951
952 /*
953 * When DMA mode is enabled specifies whether to use
954 * address DMA or DMA Descritor mode with full speed devices
955 * for accessing the data FIFOs in host mode.
956 * 0 - address DMA
957 * 1 - FS DMA Descriptor(default, if available)
958 */
959 extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg,
960 int val);
961
962 /*
963 * Specifies the maximum speed of operation in host and device mode.
964 * The actual speed depends on the speed of the attached device and
965 * the value of phy_type. The actual speed depends on the speed of the
966 * attached device.
967 * 0 - High Speed (default)
968 * 1 - Full Speed
969 */
970 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
971 #define DWC2_SPEED_PARAM_HIGH 0
972 #define DWC2_SPEED_PARAM_FULL 1
973
974 /*
975 * Specifies whether low power mode is supported when attached
976 * to a Full Speed or Low Speed device in host mode.
977 *
978 * 0 - Don't support low power mode (default)
979 * 1 - Support low power mode
980 */
981 extern void dwc2_set_param_host_support_fs_ls_low_power(
982 struct dwc2_hsotg *hsotg, int val);
983
984 /*
985 * Specifies the PHY clock rate in low power mode when connected to a
986 * Low Speed device in host mode. This parameter is applicable only if
987 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
988 * then defaults to 6 MHZ otherwise 48 MHZ.
989 *
990 * 0 - 48 MHz
991 * 1 - 6 MHz
992 */
993 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
994 int val);
995 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
996 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
997
998 /*
999 * 0 - Use cC FIFO size parameters
1000 * 1 - Allow dynamic FIFO sizing (default)
1001 */
1002 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
1003 int val);
1004
1005 /*
1006 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
1007 * FIFO sizing is enabled.
1008 * 16 to 32768 (default 1024)
1009 */
1010 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
1011
1012 /*
1013 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
1014 * when Dynamic FIFO sizing is enabled in the core.
1015 * 16 to 32768 (default 256)
1016 */
1017 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1018 int val);
1019
1020 /*
1021 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
1022 * FIFO sizing is enabled.
1023 * 16 to 32768 (default 256)
1024 */
1025 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1026 int val);
1027
1028 /*
1029 * The maximum transfer size supported in bytes.
1030 * 2047 to 65,535 (default 65,535)
1031 */
1032 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
1033
1034 /*
1035 * The maximum number of packets in a transfer.
1036 * 15 to 511 (default 511)
1037 */
1038 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
1039
1040 /*
1041 * The number of host channel registers to use.
1042 * 1 to 16 (default 11)
1043 * Note: The FPGA configuration supports a maximum of 11 host channels.
1044 */
1045 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
1046
1047 /*
1048 * Specifies the type of PHY interface to use. By default, the driver
1049 * will automatically detect the phy_type.
1050 *
1051 * 0 - Full Speed PHY
1052 * 1 - UTMI+ (default)
1053 * 2 - ULPI
1054 */
1055 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
1056 #define DWC2_PHY_TYPE_PARAM_FS 0
1057 #define DWC2_PHY_TYPE_PARAM_UTMI 1
1058 #define DWC2_PHY_TYPE_PARAM_ULPI 2
1059
1060 /*
1061 * Specifies the UTMI+ Data Width. This parameter is
1062 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
1063 * PHY_TYPE, this parameter indicates the data width between
1064 * the MAC and the ULPI Wrapper.) Also, this parameter is
1065 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
1066 * to "8 and 16 bits", meaning that the core has been
1067 * configured to work at either data path width.
1068 *
1069 * 8 or 16 bits (default 16)
1070 */
1071 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
1072
1073 /*
1074 * Specifies whether the ULPI operates at double or single
1075 * data rate. This parameter is only applicable if PHY_TYPE is
1076 * ULPI.
1077 *
1078 * 0 - single data rate ULPI interface with 8 bit wide data
1079 * bus (default)
1080 * 1 - double data rate ULPI interface with 4 bit wide data
1081 * bus
1082 */
1083 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
1084
1085 /*
1086 * Specifies whether to use the internal or external supply to
1087 * drive the vbus with a ULPI phy.
1088 */
1089 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
1090 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0
1091 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
1092
1093 /*
1094 * Specifies whether to use the I2Cinterface for full speed PHY. This
1095 * parameter is only applicable if PHY_TYPE is FS.
1096 * 0 - No (default)
1097 * 1 - Yes
1098 */
1099 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
1100
1101 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
1102
1103 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
1104
1105 /*
1106 * Specifies whether dedicated transmit FIFOs are
1107 * enabled for non periodic IN endpoints in device mode
1108 * 0 - No
1109 * 1 - Yes
1110 */
1111 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
1112 int val);
1113
1114 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
1115
1116 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
1117
1118 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
1119
1120 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1121 const struct dwc2_core_params *params);
1122
1123 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value);
1124
1125 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1126
1127 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1128 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1129
1130 /*
1131 * The following functions check the controller's OTG operation mode
1132 * capability (GHWCFG2.OTG_MODE).
1133 *
1134 * These functions can be used before the internal hsotg->hw_params
1135 * are read in and cached so they always read directly from the
1136 * GHWCFG2 register.
1137 */
1138 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1139 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1140 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1141 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1142
1143 /*
1144 * Returns the mode of operation, host or device
1145 */
dwc2_is_host_mode(struct dwc2_hsotg * hsotg)1146 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1147 {
1148 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1149 }
1150
dwc2_is_device_mode(struct dwc2_hsotg * hsotg)1151 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1152 {
1153 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1154 }
1155
1156 /*
1157 * Dump core registers and SPRAM
1158 */
1159 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1160 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1161 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1162
1163 /*
1164 * Return OTG version - either 1.3 or 2.0
1165 */
1166 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1167
1168 /* Gadget defines */
1169 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1170 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1171 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1172 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1173 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1174 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1175 bool reset);
1176 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1177 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1178 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1179 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1180 #else
dwc2_hsotg_remove(struct dwc2_hsotg * dwc2)1181 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1182 { return 0; }
dwc2_hsotg_suspend(struct dwc2_hsotg * dwc2)1183 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1184 { return 0; }
dwc2_hsotg_resume(struct dwc2_hsotg * dwc2)1185 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1186 { return 0; }
dwc2_gadget_init(struct dwc2_hsotg * hsotg,int irq)1187 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1188 { return 0; }
dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg * dwc2,bool reset)1189 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1190 bool reset) {}
dwc2_hsotg_core_connect(struct dwc2_hsotg * hsotg)1191 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_disconnect(struct dwc2_hsotg * dwc2)1192 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
dwc2_hsotg_set_test_mode(struct dwc2_hsotg * hsotg,int testmode)1193 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1194 int testmode)
1195 { return 0; }
1196 #define dwc2_is_device_connected(hsotg) (0)
1197 #endif
1198
1199 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1200 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1201 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1202 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1203 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1204 #else
dwc2_hcd_get_frame_number(struct dwc2_hsotg * hsotg)1205 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1206 { return 0; }
dwc2_hcd_connect(struct dwc2_hsotg * hsotg)1207 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_disconnect(struct dwc2_hsotg * hsotg,bool force)1208 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
dwc2_hcd_start(struct dwc2_hsotg * hsotg)1209 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_remove(struct dwc2_hsotg * hsotg)1210 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_init(struct dwc2_hsotg * hsotg)1211 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1212 { return 0; }
1213 #endif
1214
1215 #endif /* __DWC2_CORE_H__ */
1216