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Searched refs:v16f64 (Results 1 – 9 of 9) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h163 v16f64 = 105, // 16 x f64 enumerator
421 SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 || in is1024BitVector()
643 case v16f64: in getVectorElementType()
719 case v16f64: in getVectorMinNumElements()
972 case v16f64: return TypeSize::Fixed(1024); in getSizeInBits()
1242 if (NumElements == 16) return MVT::v16f64; in getVectorVT()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td777 def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
782 def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
818 defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
838 defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>;
H A DSIInstructions.td1242 def : BitConvert <v16i64, v16f64, VReg_1024>;
1243 def : BitConvert <v16f64, v16i64, VReg_1024>;
1246 def : BitConvert <v16f64, v32f32, VReg_1024>;
1247 def : BitConvert <v32f32, v16f64, VReg_1024>;
1249 def : BitConvert <v32i32, v16f64, VReg_1024>;
1250 def : BitConvert <v16f64, v32i32, VReg_1024>;
H A DAMDGPUISelLowering.cpp117 setOperationAction(ISD::LOAD, MVT::v16f64, Promote); in AMDGPUTargetLowering()
118 AddPromotedToType(ISD::LOAD, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
178 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f32, Expand); in AMDGPUTargetLowering()
184 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f16, Expand); in AMDGPUTargetLowering()
237 setOperationAction(ISD::STORE, MVT::v16f64, Promote); in AMDGPUTargetLowering()
238 AddPromotedToType(ISD::STORE, MVT::v16f64, MVT::v32i32); in AMDGPUTargetLowering()
272 setTruncStoreAction(MVT::v16f64, MVT::v16f32, Expand); in AMDGPUTargetLowering()
273 setTruncStoreAction(MVT::v16f64, MVT::v16f16, Expand); in AMDGPUTargetLowering()
350 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f64, Custom); in AMDGPUTargetLowering()
H A DSIISelLowering.cpp117 addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024)); in SITargetLowering()
248 MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32 }) { in SITargetLowering()
320 for (MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) { in SITargetLowering()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.td136 def v16f64 : ValueType<1024, 105>; // 16 x f64 vector value
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DValueTypes.cpp382 case MVT::v16f64: in getTypeForEVT()
/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenTarget.cpp169 case MVT::v16f64: return "MVT::v16f64"; in getEnumName()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIntrinsics.td328 def llvm_v16f64_ty : LLVMType<v16f64>; // 16 x double