1 /* $NetBSD: dm_pp_interface.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef _DM_PP_INTERFACE_ 26 #define _DM_PP_INTERFACE_ 27 28 #include "dm_services_types.h" 29 30 #define PP_MAX_CLOCK_LEVELS 16 31 32 enum amd_pp_display_config_type{ 33 AMD_PP_DisplayConfigType_None = 0, 34 AMD_PP_DisplayConfigType_DP54 , 35 AMD_PP_DisplayConfigType_DP432 , 36 AMD_PP_DisplayConfigType_DP324 , 37 AMD_PP_DisplayConfigType_DP27, 38 AMD_PP_DisplayConfigType_DP243, 39 AMD_PP_DisplayConfigType_DP216, 40 AMD_PP_DisplayConfigType_DP162, 41 AMD_PP_DisplayConfigType_HDMI6G , 42 AMD_PP_DisplayConfigType_HDMI297 , 43 AMD_PP_DisplayConfigType_HDMI162, 44 AMD_PP_DisplayConfigType_LVDS, 45 AMD_PP_DisplayConfigType_DVI, 46 AMD_PP_DisplayConfigType_WIRELESS, 47 AMD_PP_DisplayConfigType_VGA 48 }; 49 50 struct single_display_configuration 51 { 52 uint32_t controller_index; 53 uint32_t controller_id; 54 uint32_t signal_type; 55 uint32_t display_state; 56 /* phy id for the primary internal transmitter */ 57 uint8_t primary_transmitter_phyi_d; 58 /* bitmap with the active lanes */ 59 uint8_t primary_transmitter_active_lanemap; 60 /* phy id for the secondary internal transmitter (for dual-link dvi) */ 61 uint8_t secondary_transmitter_phy_id; 62 /* bitmap with the active lanes */ 63 uint8_t secondary_transmitter_active_lanemap; 64 /* misc phy settings for SMU. */ 65 uint32_t config_flags; 66 uint32_t display_type; 67 uint32_t view_resolution_cx; 68 uint32_t view_resolution_cy; 69 enum amd_pp_display_config_type displayconfigtype; 70 uint32_t vertical_refresh; /* for active display */ 71 }; 72 73 #define MAX_NUM_DISPLAY 32 74 75 struct amd_pp_display_configuration { 76 bool nb_pstate_switch_disable;/* controls NB PState switch */ 77 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ 78 bool cpu_pstate_disable; 79 uint32_t cpu_pstate_separation_time; 80 81 uint32_t num_display; /* total number of display*/ 82 uint32_t num_path_including_non_display; 83 uint32_t crossfire_display_index; 84 uint32_t min_mem_set_clock; 85 uint32_t min_core_set_clock; 86 /* unit 10KHz x bit*/ 87 uint32_t min_bus_bandwidth; 88 /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ 89 uint32_t min_core_set_clock_in_sr; 90 91 struct single_display_configuration displays[MAX_NUM_DISPLAY]; 92 93 uint32_t vrefresh; /* for active display*/ 94 95 uint32_t min_vblank_time; /* for active display*/ 96 bool multi_monitor_in_sync; 97 /* Controller Index of primary display - used in MCLK SMC switching hang 98 * SW Workaround*/ 99 uint32_t crtc_index; 100 /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ 101 uint32_t line_time_in_us; 102 bool invalid_vblank_time; 103 104 uint32_t display_clk; 105 /* 106 * for given display configuration if multimonitormnsync == false then 107 * Memory clock DPMS with this latency or below is allowed, DPMS with 108 * higher latency not allowed. 109 */ 110 uint32_t dce_tolerable_mclk_in_active_latency; 111 uint32_t min_dcef_set_clk; 112 uint32_t min_dcef_deep_sleep_set_clk; 113 }; 114 115 struct amd_pp_simple_clock_info { 116 uint32_t engine_max_clock; 117 uint32_t memory_max_clock; 118 uint32_t level; 119 }; 120 121 enum PP_DAL_POWERLEVEL { 122 PP_DAL_POWERLEVEL_INVALID = 0, 123 PP_DAL_POWERLEVEL_ULTRALOW, 124 PP_DAL_POWERLEVEL_LOW, 125 PP_DAL_POWERLEVEL_NOMINAL, 126 PP_DAL_POWERLEVEL_PERFORMANCE, 127 128 PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, 129 PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, 130 PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, 131 PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, 132 PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, 133 PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, 134 PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, 135 PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, 136 }; 137 138 struct amd_pp_clock_info { 139 uint32_t min_engine_clock; 140 uint32_t max_engine_clock; 141 uint32_t min_memory_clock; 142 uint32_t max_memory_clock; 143 uint32_t min_bus_bandwidth; 144 uint32_t max_bus_bandwidth; 145 uint32_t max_engine_clock_in_sr; 146 uint32_t min_engine_clock_in_sr; 147 enum PP_DAL_POWERLEVEL max_clocks_state; 148 }; 149 150 enum amd_pp_clock_type { 151 amd_pp_disp_clock = 1, 152 amd_pp_sys_clock, 153 amd_pp_mem_clock, 154 amd_pp_dcef_clock, 155 amd_pp_soc_clock, 156 amd_pp_pixel_clock, 157 amd_pp_phy_clock, 158 amd_pp_dcf_clock, 159 amd_pp_dpp_clock, 160 amd_pp_f_clock = amd_pp_dcef_clock, 161 }; 162 163 #define MAX_NUM_CLOCKS 16 164 165 struct amd_pp_clocks { 166 uint32_t count; 167 uint32_t clock[MAX_NUM_CLOCKS]; 168 uint32_t latency[MAX_NUM_CLOCKS]; 169 }; 170 171 struct pp_clock_with_latency { 172 uint32_t clocks_in_khz; 173 uint32_t latency_in_us; 174 }; 175 176 struct pp_clock_levels_with_latency { 177 uint32_t num_levels; 178 struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS]; 179 }; 180 181 struct pp_clock_with_voltage { 182 uint32_t clocks_in_khz; 183 uint32_t voltage_in_mv; 184 }; 185 186 struct pp_clock_levels_with_voltage { 187 uint32_t num_levels; 188 struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS]; 189 }; 190 191 struct pp_display_clock_request { 192 enum amd_pp_clock_type clock_type; 193 uint32_t clock_freq_in_khz; 194 }; 195 196 #endif /* _DM_PP_INTERFACE_ */ 197