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Searched refs:ANY_EXTEND (Results 1 – 25 of 52) sorted by relevance

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/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h766 ANY_EXTEND, enumerator
1494 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND || in isExtOpcode()
H A DSelectionDAG.h906 case ISD::ANY_EXTEND:
908 return ISD::ANY_EXTEND;
922 case ISD::ANY_EXTEND:
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp421 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in lowerBITCAST()
673 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2))), in lowerINTRINSIC_W_CHAIN()
816 DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Op.getOperand(3))); in lowerINTRINSIC_VOID()
844 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(3))); in lowerINTRINSIC_VOID()
998 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp()
1100 SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src); in ReplaceNodeResults()
1122 SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src); in ReplaceNodeResults()
1254 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), in ReplaceNodeResults()
1272 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), in ReplaceNodeResults()
1273 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3)), in ReplaceNodeResults()
[all …]
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp366 case ISD::ANY_EXTEND: in PromoteIntRes_AtomicCmpSwap()
418 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
435 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
482 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
505 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res); in PromoteIntRes_BSWAP()
526 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res); in PromoteIntRes_BITREVERSE()
538 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), in PromoteIntRes_BUILD_PAIR()
2246 return ISD::ANY_EXTEND; in getExtendForIntVecReduction()
2264 case ISD::ANY_EXTEND: in PromoteIntOpVectorReduction()
3197 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); in ExpandIntRes_ANY_EXTEND()
[all …]
H A DSelectionDAGBuilder.h340 ISD::NodeType ExtendType = ISD::ANY_EXTEND);
773 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
H A DLegalizeDAG.cpp2822 case ISD::ANY_EXTEND: in ExpandNode()
2916 Op = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, in ExpandNode()
3377 SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]); in ExpandNode()
3419 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) && in ExpandNode()
3425 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi); in ExpandNode()
3551 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); in ExpandNode()
4511 Tmp1 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4613 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4659 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4694 Tmp1 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
[all …]
H A DLegalizeVectorTypes.cpp78 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
432 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
642 case ISD::ANY_EXTEND: in ScalarizeVectorOperand()
1073 case ISD::ANY_EXTEND: in SplitVectorResult()
1740 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecRes_INSERT_VECTOR_ELT()
2861 case ISD::ANY_EXTEND: in SplitVectorOperand()
3202 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecOp_EXTRACT_VECTOR_ELT()
4049 case ISD::ANY_EXTEND: in WidenVectorResult()
4569 if (Opcode == ISD::ANY_EXTEND) in WidenVecRes_Convert()
5806 case ISD::ANY_EXTEND: in WidenVectorOperand()
[all …]
H A DFunctionLoweringInfo.cpp65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in getPreferredExtendForValue()
H A DDAGCombiner.cpp1318 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1875 case ISD::ANY_EXTEND: in combine()
8041 case ISD::ANY_EXTEND: in calculateByteProvider()
8150 case ISD::ANY_EXTEND: in stripTruncAndExt()
9219 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
11744 Opcode == ISD::ANY_EXTEND) && in tryToFoldExtendSelectLoad()
11787 Opcode == ISD::ANY_EXTEND || in tryToFoldExtendOfConstant()
11817 if (FoldOpc == ISD::ANY_EXTEND) in tryToFoldExtendOfConstant()
13011 if (N0.getOpcode() == ISD::ANY_EXTEND || in visitANY_EXTEND()
13766 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
[all …]
H A DLegalizeTypesGeneric.cpp226 OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0)); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeTypes.cpp1010 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); in JoinIntegers()
H A DSelectionDAGDumper.cpp346 case ISD::ANY_EXTEND: return "any_extend"; in getOperationName()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp65 SrcOrValue = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, SrcOrValue); in EmitMOPS()
H A DAArch64ISelLowering.cpp1142 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); in AArch64TargetLowering()
1738 setOperationAction(ISD::ANY_EXTEND, VT, Custom); in addTypeForStreamingSVE()
1852 setOperationAction(ISD::ANY_EXTEND, VT, Custom); in addTypeForFixedLengthSVE()
4427 N->getOpcode() == ISD::ANY_EXTEND || in isSignExtended()
4433 N->getOpcode() == ISD::ANY_EXTEND || in isZeroExtended()
6013 case ISD::ANY_EXTEND: in LowerOperation()
12750 Vec1 = DAG.getNode(ISD::ANY_EXTEND, DL, WideVT, Vec1); in LowerINSERT_SUBVECTOR()
19224 ExtOpCode != ISD::ANY_EXTEND) in foldTruncStoreOfExt()
20432 if (Op->getOpcode() == ISD::ANY_EXTEND && in getTestBitOperand()
21441 case ISD::ANY_EXTEND: in PerformDAGCombine()
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/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVEISelLowering.h122 return ISD::ANY_EXTEND; in getExtendForAtomicOps()
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp852 case ISD::ANY_EXTEND: in expandRxSBG()
972 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && in tryRISBGZero()
1081 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && in tryRxSBG()
1920 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); in expandSelectBoolean()
H A DSystemZISelLowering.h604 return ISD::ANY_EXTEND; in getExtendForAtomicOps()
H A DSystemZISelLowering.cpp1407 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
3313 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi); in lowerThreadPointer()
3533 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In); in lowerBITCAST()
4111 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op); in lowerCTPOP()
5211 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1); in joinDwords()
5213 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in joinDwords()
5215 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in joinDwords()
5216 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1); in joinDwords()
6228 if (N0.hasOneUse() && N0.getOpcode() == ISD::ANY_EXTEND) in combineSIGN_EXTEND_INREG()
6257 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT, in combineSIGN_EXTEND()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp235 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
278 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
421 setOperationAction(ISD::ANY_EXTEND, VecTy, Custom); in initializeHVXLowering()
1655 SDValue ToInt32 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, ToInt16); in LowerHvxSplatVector()
2901 case ISD::ANY_EXTEND: in CreateTLWrapper()
3210 case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG); in LowerHvxOperation()
3265 case ISD::ANY_EXTEND: in ExpandHvxResizeIntoSteps()
3366 case ISD::ANY_EXTEND: in LowerHvxOperationWrapper()
3432 case ISD::ANY_EXTEND: in ReplaceHvxNodeResults()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1110 case ISD::ANY_EXTEND: in PreprocessISelDAG()
1119 assert(N->getOpcode() == ISD::ANY_EXTEND && in PreprocessISelDAG()
1123 NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG()
1969 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in foldMaskedShiftToScaledMask()
1996 SDValue NewX = DAG.getNode(ISD::ANY_EXTEND, DL, VT, X); in foldMaskedShiftToScaledMask()
2085 if (X.getOpcode() == ISD::ANY_EXTEND) { in foldMaskAndShiftToScale()
2389 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || in matchAddressRecursively()
3714 NBits = CurDAG->getNode(ISD::ANY_EXTEND, DL, NVT, NBits); in matchBitExtract()
3772 Control = CurDAG->getNode(ISD::ANY_EXTEND, DL, XVT, Control); in matchBitExtract()
4123 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in tryShrinkShlLogicImm()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp287 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
644 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1079 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1457 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src); in getBitTestCondition()
1462 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo); in getBitTestCondition()
3393 Carry.getOpcode() == ISD::ANY_EXTEND || in combineCarryThroughADD()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2853 isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerScalarInsert()
3764 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0); in LowerOperation()
3770 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in LowerOperation()
3838 case ISD::ANY_EXTEND: in LowerOperation()
5648 Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Scalar); in LowerINTRINSIC_WO_CHAIN()
7637 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp()
7824 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in ReplaceNodeResults()
7848 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in ReplaceNodeResults()
7873 unsigned ExtOpc = ISD::ANY_EXTEND; in ReplaceNodeResults()
8084 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in ReplaceNodeResults()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2694 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
3230 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
5105 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS); in ReplaceNodeResults()
5106 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS); in ReplaceNodeResults()
6374 Addr = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Addr); in packImage16bitOpsToDwords()
8611 return DAG.getNode(ISD::ANY_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
11079 MulLHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i64, MulLHS); in tryFoldToMad64_32()
11080 MulRHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i64, MulRHS); in tryFoldToMad64_32()
11159 Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY) in performAddCombine()
11167 case ISD::ANY_EXTEND: { in performAddCombine()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1669 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
2398 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1); in LowerSelect()
2399 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2); in LowerSelect()
2573 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
2882 RetVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, RetVal); in LowerReturn()
4793 if (Val.getOpcode() == ISD::ANY_EXTEND) { in PerformANDCombine()
/openbsd/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp844 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1243 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), in LowerSIGN_EXTEND()

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