1 /* $OpenBSD: ar9003reg.h,v 1.9 2017/05/19 11:42:48 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * MAC registers. 22 */ 23 #define AR_ISR_S2_S 0x00d0 24 #define AR_ISR_S3_S 0x00d4 25 #define AR_ISR_S4_S 0x00d8 26 #define AR_ISR_S5_S 0x00dc 27 #define AR_GPIO_IN_OUT 0x4048 28 #define AR_GPIO_IN 0x404c 29 #define AR9300_GPIO_IN_VAL 0x0001FFFF 30 #define AR_GPIO_OE_OUT 0x4050 31 #define AR_GPIO_INTR_POL 0x4058 32 #define AR_GPIO_INPUT_EN_VAL 0x405c 33 #define AR_GPIO_INPUT_MUX1 0x4060 34 #define AR_GPIO_INPUT_MUX2 0x4064 35 #define AR_GPIO_OUTPUT_MUX(i) (0x4068 + (i) * 4) 36 #define AR_INPUT_STATE 0x4074 37 #define AR_EEPROM_STATUS_DATA 0x4084 38 #define AR_OBS 0x4088 39 #define AR_GPIO_PDPU 0x4090 40 #define AR_PCIE_MSI 0x40a4 41 #define AR_ENT_OTP 0x40d8 42 43 /* Bits for AR_ENT_OTP. */ 44 #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 45 #define AR_ENT_OTP_MPSD 0x00800000 46 47 /* 48 * PHY registers. 49 */ 50 #define AR_PHY_TIMING1 0x09800 51 #define AR_PHY_TIMING2 0x09804 52 #define AR_PHY_TIMING3 0x09808 53 #define AR_PHY_TIMING4 0x0980c 54 #define AR_PHY_TIMING5 0x09810 55 #define AR_PHY_TIMING6 0x09814 56 #define AR_PHY_TIMING11 0x09818 57 #define AR_PHY_SPUR_REG 0x0981c 58 #define AR_PHY_FIND_SIG_LOW 0x09820 59 #define AR_PHY_SFCORR 0x09824 60 #define AR_PHY_SFCORR_LOW 0x09828 61 #define AR_PHY_SFCORR_EXT 0x0982c 62 #define AR_PHY_EXT_CCA(i) (0x09830 + (i) * 0x1000) 63 #define AR_PHY_RADAR_0 0x09834 64 #define AR_PHY_RADAR_1 0x09838 65 #define AR_PHY_RADAR_EXT 0x0983c 66 #define AR_PHY_MULTICHAIN_CTRL 0x09880 67 #define AR_PHY_PERCHAIN_CSD 0x09884 68 #define AR_PHY_TX_CRC 0x098a0 69 #define AR_PHY_TST_DAC_CONST 0x098a4 70 #define AR_PHY_SPUR_REPORT_0 0x098a8 71 #define AR_PHY_TX_IQCAL_CONTROL_3 0x098b0 72 #define AR_PHY_IQ_ADC_MEAS_0_B(i) (0x098c0 + (i) * 0x1000) 73 #define AR_PHY_IQ_ADC_MEAS_1_B(i) (0x098c4 + (i) * 0x1000) 74 #define AR_PHY_IQ_ADC_MEAS_2_B(i) (0x098c8 + (i) * 0x1000) 75 #define AR_PHY_IQ_ADC_MEAS_3_B(i) (0x098cc + (i) * 0x1000) 76 #define AR_PHY_TX_PHASE_RAMP_0 0x098d0 77 #define AR_PHY_ADC_DC_GAIN_CORR(i) (0x098d4 + (i) * 0x1000) 78 #define AR_PHY_RX_IQCAL_CORR_B(i) (0x098dc + (i) * 0x1000) 79 #define AR_PHY_PAPRD_AM2AM 0x098e4 80 #define AR_PHY_PAPRD_AM2PM 0x098e8 81 #define AR_PHY_PAPRD_HT40 0x098ec 82 #define AR_PHY_PAPRD_CTRL0_B(i) (0x098f0 + (i) * 0x1000) 83 #define AR_PHY_PAPRD_CTRL1_B(i) (0x098f4 + (i) * 0x1000) 84 #define AR_PHY_PA_GAIN123_B(i) (0x098f8 + (i) * 0x1000) 85 #define AR_PHY_PAPRD_PRE_POST_SCALE_B0(i) \ 86 (0x09900 + (i) * 4) 87 #define AR_PHY_PAPRD_MEM_TAB_B(i, j) (0x09920 + (i) * 0x1000 + (j) * 4) 88 #define AR_PHY_CHAN_INFO_TAB(i, j) (0x09b00 + (i) * 0x1000 + (j) * 4) 89 #define AR_PHY_TIMING_3A 0x09c00 90 #define AR_PHY_LDPC_CNTL1 0x09c04 91 #define AR_PHY_LDPC_CNTL2 0x09c08 92 #define AR_PHY_PILOT_SPUR_MASK 0x09c0c 93 #define AR_PHY_CHAN_SPUR_MASK 0x09c10 94 #define AR_PHY_SGI_DELTA 0x09c14 95 #define AR_PHY_ML_CNTL_1 0x09c18 96 #define AR_PHY_ML_CNTL_2 0x09c1c 97 #define AR_PHY_TST_ADC 0x09c20 98 #define AR_PHY_SETTLING 0x09e00 99 #define AR_PHY_RXGAIN(i) (0x09e04 + (i) * 0x1000) 100 #define AR_PHY_GAINS_MINOFF0 0x09e08 101 #define AR_PHY_DESIRED_SZ 0x09e0c 102 #define AR_PHY_FIND_SIG 0x09e10 103 #define AR_PHY_AGC 0x09e14 104 #define AR_PHY_EXT_ATTEN_CTL(i) (0x09e18 + (i) * 0x1000) 105 #define AR_PHY_CCA(i) (0x09e1c + (i) * 0x1000) 106 #define AR_PHY_CCA_CTRL(i) (0x09e20 + (i) * 0x1000) 107 #define AR_PHY_RESTART 0x09e24 108 #define AR_PHY_MC_GAIN_CTRL 0x09e28 109 #define AR_PHY_EXTCHN_PWRTHR1 0x09e2c 110 #define AR_PHY_EXT_CHN_WIN 0x09e30 111 #define AR_PHY_20_40_DET_THR 0x09e34 112 #define AR_PHY_RIFS_SRCH 0x09e38 113 #define AR_PHY_PEAK_DET_CTRL_1 0x09e3c 114 #define AR_PHY_PEAK_DET_CTRL_2 0x09e40 115 #define AR_PHY_RX_GAIN_BOUNDS_1 0x09e44 116 #define AR_PHY_RX_GAIN_BOUNDS_2 0x09e48 117 #define AR_PHY_RSSI(i) (0x09f80 + (i) * 0x1000) 118 #define AR_PHY_SPUR_CCK_REP0 0x09f84 119 #define AR_PHY_CCK_DETECT 0x09fc0 120 #define AR_PHY_DAG_CTRLCCK 0x09fc4 121 #define AR_PHY_IQCORR_CTRL_CCK 0x09fc8 122 #define AR_PHY_CCK_SPUR_MIT 0x09fcc 123 #define AR_PHY_RX_OCGAIN 0x0a000 124 #define AR_PHY_D2_CHIP_ID 0x0a200 125 #define AR_PHY_GEN_CTRL 0x0a204 126 #define AR_PHY_MODE 0x0a208 127 #define AR_PHY_ACTIVE 0x0a20c 128 #define AR_PHY_SPUR_MASK_A 0x0a220 129 #define AR_PHY_SPUR_MASK_B 0x0a224 130 #define AR_PHY_SPECTRAL_SCAN 0x0a228 131 #define AR_PHY_RADAR_BW_FILTER 0x0a22c 132 #define AR_PHY_SEARCH_START_DELAY 0x0a230 133 #define AR_PHY_MAX_RX_LEN 0x0a234 134 #define AR_PHY_FRAME_CTL 0x0a238 135 #define AR_PHY_RFBUS_REQ 0x0a23c 136 #define AR_PHY_RFBUS_GRANT 0x0a240 137 #define AR_PHY_RIFS 0x0a244 138 #define AR_PHY_RX_CLR_DELAY 0x0a250 139 #define AR_PHY_RX_DELAY 0x0a254 140 #define AR_PHY_XPA_TIMING_CTL 0x0a264 141 #define AR_PHY_MISC_PA_CTL 0x0a280 142 #define AR_PHY_SWITCH_CHAIN(i) (0x0a284 + (i) * 0x1000) 143 #define AR_PHY_SWITCH_COM 0x0a288 144 #define AR_PHY_SWITCH_COM_2 0x0a28c 145 #define AR_PHY_RX_CHAINMASK 0x0a2a0 146 #define AR_PHY_CAL_CHAINMASK 0x0a2c0 147 #define AR_PHY_AGC_CONTROL 0x0a2c4 148 #define AR_PHY_CALMODE 0x0a2c8 149 #define AR_PHY_FCAL_1 0x0a2cc 150 #define AR_PHY_FCAL_2_0 0x0a2d0 151 #define AR_PHY_DFT_TONE_CTL_0 0x0a2d4 152 #define AR_PHY_CL_CAL_CTL 0x0a2d8 153 #define AR_PHY_CL_TAB_0 0x0a300 154 #define AR_PHY_SYNTH_CONTROL 0x0a340 155 #define AR_PHY_ADDAC_CLK_SEL 0x0a344 156 #define AR_PHY_PLL_CTL 0x0a348 157 #define AR_PHY_ANALOG_SWAP 0x0a34c 158 #define AR_PHY_ADDAC_PARA_CTL 0x0a350 159 #define AR_PHY_XPA_CFG 0x0a358 160 #define AR_PHY_TEST 0x0a360 161 #define AR_PHY_TEST_CTL_STATUS 0x0a364 162 #define AR_PHY_TSTDAC 0x0a368 163 #define AR_PHY_CHAN_STATUS 0x0a36c 164 #define AR_PHY_CHAN_INFO_MEMORY 0x0a370 165 #define AR_PHY_CHNINFO_NOISEPWR 0x0a374 166 #define AR_PHY_CHNINFO_GAINDIFF 0x0a378 167 #define AR_PHY_CHNINFO_FINETIM 0x0a37c 168 #define AR_PHY_CHAN_INFO_GAIN_0 0x0a380 169 #define AR_PHY_SCRAMBLER_SEED 0x0a390 170 #define AR_PHY_CCK_TX_CTRL 0x0a394 171 #define AR_PHY_HEAVYCLIP_CTL 0x0a3a4 172 #define AR_PHY_HEAVYCLIP_20 0x0a3a8 173 #define AR_PHY_HEAVYCLIP_40 0x0a3ac 174 #define AR_PHY_ILLEGAL_TXRATE 0x0a3b0 175 #define AR_PHY_PWRTX_RATE1 0x0a3c0 176 #define AR_PHY_PWRTX_RATE2 0x0a3c4 177 #define AR_PHY_PWRTX_RATE3 0x0a3c8 178 #define AR_PHY_PWRTX_RATE4 0x0a3cc 179 #define AR_PHY_PWRTX_RATE5 0x0a3d0 180 #define AR_PHY_PWRTX_RATE6 0x0a3d4 181 #define AR_PHY_PWRTX_RATE7 0x0a3d8 182 #define AR_PHY_PWRTX_RATE8 0x0a3dc 183 #define AR_PHY_PWRTX_RATE10 0x0a3e4 184 #define AR_PHY_PWRTX_RATE11 0x0a3e8 185 #define AR_PHY_PWRTX_RATE12 0x0a3ec 186 #define AR_PHY_PWRTX_MAX 0x0a3f0 187 #define AR_PHY_POWER_TX_SUB 0x0a3f4 188 #define AR_PHY_TPC_1 0x0a3f8 189 #define AR_PHY_TPC_4_B(i) (0x0a404 + (i) * 0x1000) 190 #define AR_PHY_TPC_5_B(i) (0x0a408 + (i) * 0x1000) 191 #define AR_PHY_TPC_6_B(i) (0x0a40c + (i) * 0x1000) 192 #define AR_PHY_TPC_11_B(i) (0x0a420 + (i) * 0x1000) 193 #define AR_PHY_TPC_12 0x0a424 194 #define AR_PHY_TPC_18 0x0a43c 195 #define AR_PHY_TPC_19 0x0a440 196 #define AR_PHY_BB_THERM_ADC_1 0x0a448 197 #define AR_PHY_BB_THERM_ADC_4 0x0a454 198 #define AR_PHY_TX_FORCED_GAIN 0x0a458 199 #define AR_PHY_PDADC_TAB(i) (0x0a480 + (i) * 0x1000) 200 #define AR_PHY_TXGAIN_TABLE(i) (0x0a500 + (i) * 4) 201 #define AR_PHY_TX_IQCAL_CONTROL_1 0x0a648 202 #define AR_PHY_TX_IQCAL_START 0x0a640 203 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i) \ 204 (0x0a650 + (i) * 0x1000) 205 #define AR_PHY_TX_IQCAL_STATUS_B(i) (0x0a68c + (i) * 0x1000) 206 #define AR_PHY_PAPRD_TRAINER_CNTL1 0x0a690 207 #define AR_PHY_PAPRD_TRAINER_CNTL2 0x0a694 208 #define AR_PHY_PAPRD_TRAINER_CNTL3 0x0a698 209 #define AR_PHY_PAPRD_TRAINER_CNTL4 0x0a69c 210 #define AR_PHY_PAPRD_TRAINER_STAT1 0x0a6a0 211 #define AR_PHY_PAPRD_TRAINER_STAT2 0x0a6a4 212 #define AR_PHY_PAPRD_TRAINER_STAT3 0x0a6a8 213 #define AR_PHY_PANIC_WD_STATUS 0x0a7c0 214 #define AR_PHY_PANIC_WD_CTL_1 0x0a7c4 215 #define AR_PHY_PANIC_WD_CTL_2 0x0a7c8 216 #define AR_PHY_BT_CTL 0x0a7cc 217 #define AR_PHY_ONLY_WARMRESET 0x0a7d0 218 #define AR_PHY_ONLY_CTL 0x0a7d4 219 #define AR_PHY_ECO_CTRL 0x0a7dc 220 221 /* 222 * Analog registers. 223 */ 224 #define AR_IS_ANALOG_REG(reg) ((reg) >= 0x16000 && (reg) <= 0x17000) 225 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c 226 #define AR_PHY_65NM_CH0_SYNTH7 0x16098 227 #define AR_PHY_65NM_CH0_BIAS1 0x160c0 228 #define AR_PHY_65NM_CH0_BIAS2 0x160c4 229 #define AR_PHY_65NM_CH0_BIAS4 0x160cc 230 #define AR_PHY_65NM_CH0_RXTX1 0x16100 231 #define AR_PHY_65NM_CH0_RXTX2 0x16104 232 #define AR_PHY_65NM_CH0_RXTX4 0x1610c 233 #define AR9485_PHY_65NM_CH0_TOP2 0x16284 234 #define AR_PHY_65NM_CH0_TOP 0x16288 235 #define AR_PHY_65NM_CH0_THERM 0x16290 236 #define AR9485_PHY_CH0_XTAL 0x16290 237 #define AR_PHY_65NM_CH1_RXTX1 0x16500 238 #define AR_PHY_65NM_CH1_RXTX2 0x16504 239 #define AR_PHY_65NM_CH2_RXTX1 0x16900 240 #define AR_PHY_65NM_CH2_RXTX2 0x16904 241 #define AR_PHY_PMU1 0x16c40 242 #define AR_PHY_PMU2 0x16c44 243 244 245 /* Bits for AR_PHY_TIMING2. */ 246 #define AR_PHY_TIMING2_FORCE_PPM_VAL_M 0x00000fff 247 #define AR_PHY_TIMING2_FORCE_PPM_VAL_S 0 248 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 249 250 /* Bits for AR_PHY_TIMING3. */ 251 #define AR_PHY_TIMING3_DSC_EXP_M 0x0001e000 252 #define AR_PHY_TIMING3_DSC_EXP_S 13 253 #define AR_PHY_TIMING3_DSC_MAN_M 0xfffe0000 254 #define AR_PHY_TIMING3_DSC_MAN_S 17 255 256 /* Bits for AR_PHY_TIMING4. */ 257 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_M 0x0000f000 258 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 259 #define AR_PHY_TIMING4_DO_CAL 0x00010000 260 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000 261 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000 262 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000 263 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000 264 265 /* Bits for AR_PHY_TIMING5. */ 266 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 267 #define AR_PHY_TIMING5_CYCPWR_THR1_M 0x000000fe 268 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 269 #define AR_PHY_TIMING5_RSSI_THR1A_ENA 0x00008000 270 #define AR_PHY_TIMING5_CYCPWR_THR1A_M 0x007f0000 271 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 272 #define AR_PHY_TIMING5_RSSI_THR1A_M 0x007f0000 273 #define AR_PHY_TIMING5_RSSI_THR1A_S 16 274 275 /* Bits for AR_PHY_TIMING11. */ 276 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M 0x000fffff 277 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 278 #define AR_PHY_TIMING11_SPUR_FREQ_SD_M 0x3ff00000 279 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 280 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000 281 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000 282 283 /* Bits for AR_PHY_SPUR_REG. */ 284 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M 0x000000ff 285 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 286 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100 287 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x00020000 288 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_M 0x03fc0000 289 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 290 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x04000000 291 292 /* Bits for AR_PHY_FIND_SIG_LOW. */ 293 #define AR_PHY_FIND_SIG_LOW_RELSTEP_M 0x0000001f 294 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 295 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_M 0x00000fc0 296 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 297 #define AR_PHY_FIND_SIG_LOW_FIRPWR_M 0x0007f000 298 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 299 300 /* Bits for AR_PHY_SFCORR. */ 301 #define AR_PHY_SFCORR_M2COUNT_THR_M 0x0000001f 302 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 303 #define AR_PHY_SFCORR_M1_THRESH_M 0x00fe0000 304 #define AR_PHY_SFCORR_M1_THRESH_S 17 305 #define AR_PHY_SFCORR_M2_THRESH_M 0x7f000000 306 #define AR_PHY_SFCORR_M2_THRESH_S 24 307 308 /* Bits for AR_PHY_SFCORR_LOW. */ 309 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 310 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M 0x00003f00 311 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 312 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M 0x001fc000 313 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 314 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M 0x0fe00000 315 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 316 317 /* Bits for AR_PHY_SFCORR_EXT. */ 318 #define AR_PHY_SFCORR_EXT_M1_THRESH_M 0x0000007f 319 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 320 #define AR_PHY_SFCORR_EXT_M2_THRESH_M 0x00003f80 321 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 322 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M 0x001fc000 323 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 324 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M 0x0fe00000 325 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 326 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000 327 328 /* Bits for AR_PHY_RADAR_0. */ 329 #define AR_PHY_RADAR_0_ENA 0x00000001 330 #define AR_PHY_RADAR_0_INBAND_M 0x0000003e 331 #define AR_PHY_RADAR_0_INBAND_S 1 332 #define AR_PHY_RADAR_0_PRSSI_M 0x00000fc0 333 #define AR_PHY_RADAR_0_PRSSI_S 6 334 #define AR_PHY_RADAR_0_HEIGHT_M 0x0003f000 335 #define AR_PHY_RADAR_0_HEIGHT_S 12 336 #define AR_PHY_RADAR_0_RRSSI_M 0x00fc0000 337 #define AR_PHY_RADAR_0_RRSSI_S 18 338 #define AR_PHY_RADAR_0_FIRPWR_M 0x7f000000 339 #define AR_PHY_RADAR_0_FIRPWR_S 24 340 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 341 342 /* Bits for AR_PHY_RADAR_1. */ 343 #define AR_PHY_RADAR_1_MAXLEN_M 0x000000ff 344 #define AR_PHY_RADAR_1_MAXLEN_S 0 345 #define AR_PHY_RADAR_1_RELSTEP_THRESH_M 0x00001f00 346 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 347 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 348 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 349 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 350 #define AR_PHY_RADAR_1_RELPWR_THRESH_M 0x003f0000 351 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 352 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 353 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 354 355 /* Bits for AR_PHY_RADAR_EXT. */ 356 #define AR_PHY_RADAR_EXT_ENA 0x00004000 357 #define AR_PHY_RADAR_DC_PWR_THRESH_M 0x007f8000 358 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15 359 #define AR_PHY_RADAR_LB_DC_CAP_M 0x7f800000 360 #define AR_PHY_RADAR_LB_DC_CAP_S 23 361 362 /* Bits for AR_PHY_TX_IQCAL_CONTROL_3. */ 363 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 364 365 /* Bits for AR_PHY_RX_IQCAL_CORR_B(0). */ 366 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_M 0x0000007f 367 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 368 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_M 0x00003f80 369 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 370 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 371 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_M 0x003f8000 372 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 373 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_M 0x1fc00000 374 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 375 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 376 377 /* Bits for AR_PHY_PAPRD_AM2AM. */ 378 #define AR_PHY_PAPRD_AM2AM_MASK_M 0x01ffffff 379 #define AR_PHY_PAPRD_AM2AM_MASK_S 0 380 381 /* Bits for AR_PHY_PAPRD_AM2PM. */ 382 #define AR_PHY_PAPRD_AM2PM_MASK_M 0x01ffffff 383 #define AR_PHY_PAPRD_AM2PM_MASK_S 0 384 385 /* Bits for AR_PHY_PAPRD_HT40. */ 386 #define AR_PHY_PAPRD_HT40_MASK_M 0x01ffffff 387 #define AR_PHY_PAPRD_HT40_MASK_S 0 388 389 /* Bits for AR_PHY_PAPRD_CTRL0_B(i). */ 390 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001 391 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE 0x00000002 392 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_M 0xf8000000 393 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27 394 395 /* Bits for AR_PHY_PAPRD_CTRL1_B(i). */ 396 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001 397 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA 0x00000002 398 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA 0x00000004 399 #define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_M 0x000001f8 400 #define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_S 3 401 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_M 0x0001fe00 402 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_S 9 403 #define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_M 0x0ffe0000 404 #define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_S 17 405 406 /* Bits for AR_PHY_PA_GAIN123_B(i). */ 407 #define AR_PHY_PA_GAIN123_PA_GAIN1_M 0x000003ff 408 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0 409 410 /* Bits for AR_PHY_PAPRD_PRE_POST_SCALE_B0(i). */ 411 #define AR_PHY_PAPRD_PRE_POST_SCALING_M 0x0003ffff 412 #define AR_PHY_PAPRD_PRE_POST_SCALING_S 0 413 414 /* Bits for AR_PHY_PAPRD_MEM_TAB_B(i). */ 415 #define AR_PHY_PAPRD_ANGLE_M 0x000007ff 416 #define AR_PHY_PAPRD_ANGLE_S 0 417 #define AR_PHY_PAPRD_PA_IN_M 0x003ff800 418 #define AR_PHY_PAPRD_PA_IN_S 11 419 420 /* Bits for AR_PHY_PILOT_SPUR_MASK. */ 421 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_M 0x0000001f 422 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 423 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_M 0x00000fe0 424 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 425 426 /* Bits for AR_PHY_CHAN_SPUR_MASK. */ 427 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_M 0x0000001f 428 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 429 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_M 0x00000fe0 430 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 431 432 /* Bits for AR_PHY_SGI_DELTA. */ 433 #define AR_PHY_SGI_DSC_EXP_M 0x0000000f 434 #define AR_PHY_SGI_DSC_EXP_S 0 435 #define AR_PHY_SGI_DSC_MAN_M 0x0007fff0 436 #define AR_PHY_SGI_DSC_MAN_S 4 437 438 /* Bits for AR_PHY_SETTLING. */ 439 #define AR_PHY_SETTLING_SWITCH_M 0x00003f80 440 #define AR_PHY_SETTLING_SWITCH_S 7 441 442 /* Bits for AR_PHY_RXGAIN(i). */ 443 #define AR_PHY_RXGAIN_TXRX_ATTEN_M 0x0003f000 444 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 445 #define AR_PHY_RXGAIN_TXRX_RF_MAX_M 0x007c0000 446 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 447 448 /* Bits for AR_PHY_DESIRED_SZ. */ 449 #define AR_PHY_DESIRED_SZ_ADC_M 0x000000ff 450 #define AR_PHY_DESIRED_SZ_ADC_S 0 451 #define AR_PHY_DESIRED_SZ_PGA_M 0x0000ff00 452 #define AR_PHY_DESIRED_SZ_PGA_S 8 453 #define AR_PHY_DESIRED_SZ_TOT_DES_M 0x0ff00000 454 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 455 456 /* Bits for AR_PHY_FIND_SIG. */ 457 #define AR_PHY_FIND_SIG_RELSTEP_M 0x0000001f 458 #define AR_PHY_FIND_SIG_RELSTEP_S 0 459 #define AR_PHY_FIND_SIG_RELPWR_M 0x000007c0 460 #define AR_PHY_FIND_SIG_RELPWR_S 6 461 #define AR_PHY_FIND_SIG_FIRSTEP_M 0x0003f000 462 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 463 #define AR_PHY_FIND_SIG_FIRPWR_M 0x03fc0000 464 #define AR_PHY_FIND_SIG_FIRPWR_S 18 465 466 /* Bits for AR_PHY_AGC. */ 467 #define AR_PHY_AGC_COARSE_PWR_CONST_M 0x0000007f 468 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0 469 #define AR_PHY_AGC_COARSE_LOW_M 0x00007f80 470 #define AR_PHY_AGC_COARSE_LOW_S 7 471 #define AR_PHY_AGC_COARSE_HIGH_M 0x003f8000 472 #define AR_PHY_AGC_COARSE_HIGH_S 15 473 474 /* Bits for AR_PHY_EXT_ATTEN_CTL(i). */ 475 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_M 0x0000001f 476 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 477 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_M 0x0000003f 478 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 479 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_M 0x00000fc0 480 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 481 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_M 0x00003c00 482 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 483 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_M 0x0001f000 484 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 485 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_M 0x003e0000 486 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 487 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_M 0x00fc0000 488 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 489 490 /* Bits for AR_PHY_CCA(i). */ 491 #define AR_PHY_MAXCCA_PWR_M 0x000001ff 492 #define AR_PHY_MAXCCA_PWR_S 0 493 #define AR_PHY_MINCCA_PWR_M 0x1ff00000 494 #define AR_PHY_MINCCA_PWR_S 20 495 496 /* Bits for AR_PHY_EXT_CCA(i). */ 497 #define AR_PHY_EXT_MAXCCA_PWR_M 0x000001ff 498 #define AR_PHY_EXT_MAXCCA_PWR_S 0 499 #define AR_PHY_EXT_MINCCA_PWR_M 0x01ff0000 500 #define AR_PHY_EXT_MINCCA_PWR_S 16 501 502 /* Bits for AR_PHY_RESTART. */ 503 #define AR_PHY_RESTART_ENA 0x00000001 504 #define AR_PHY_RESTART_DIV_GC_M 0x001c0000 505 #define AR_PHY_RESTART_DIV_GC_S 18 506 507 /* Bits for AR_PHY_MC_GAIN_CTRL. */ 508 #define AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV 0x01000000 509 #define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_M 0x7e000000 510 #define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_S 25 511 512 /* Bits for AR_PHY_CCK_DETECT. */ 513 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M 0x0000003f 514 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 515 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M 0x00001fc0 516 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 517 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x00002000 518 519 /* Bits for AR_PHY_DAG_CTRLCCK. */ 520 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 521 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_M 0x0001fc00 522 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 523 524 /* Bits for AR_PHY_CCK_SPUR_MIT. */ 525 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 526 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_M 0x000001fe 527 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 528 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_M 0x1ffffe00 529 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 530 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_M 0x60000000 531 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 532 533 /* Bits for AR_PHY_GEN_CTRL. */ 534 #define AR_PHY_GC_TURBO_MODE 0x00000001 535 #define AR_PHY_GC_TURBO_SHORT 0x00000002 536 #define AR_PHY_GC_DYN2040_EN 0x00000004 537 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 538 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 539 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 540 #define AR_PHY_GC_HT_EN 0x00000040 541 #define AR_PHY_GC_SHORT_GI_40 0x00000080 542 #define AR_PHY_GC_WALSH 0x00000100 543 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 544 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 545 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 546 547 /* Bits for AR_PHY_MODE. */ 548 #define AR_PHY_MODE_OFDM 0x00000000 549 #define AR_PHY_MODE_CCK 0x00000001 550 #define AR_PHY_MODE_DYNAMIC 0x00000004 551 #define AR_PHY_MODE_HALF 0x00000020 552 #define AR_PHY_MODE_QUARTER 0x00000040 553 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 554 #define AR_PHY_MODE_SVD_HALF 0x00000200 555 556 /* Bits for AR_PHY_ACTIVE. */ 557 #define AR_PHY_ACTIVE_DIS 0x00000000 558 #define AR_PHY_ACTIVE_EN 0x00000001 559 560 /* Bits for AR_PHY_SPUR_MASK_A. */ 561 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_M 0x000003ff 562 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 563 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_M 0x0001fc00 564 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 565 566 /* Bits for AR_PHY_SPECTRAL_SCAN. */ 567 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 568 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 569 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_M 0x000000f0 570 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 571 #define AR_PHY_SPECTRAL_SCAN_PERIOD_M 0x0000ff00 572 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 573 #define AR_PHY_SPECTRAL_SCAN_COUNT_M 0x00ff0000 574 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 575 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 576 577 /* Bits for AR_PHY_RFBUS_REQ. */ 578 #define AR_PHY_RFBUS_REQ_EN 0x00000001 579 580 /* Bits for AR_PHY_RFBUS_GRANT. */ 581 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 582 583 /* Bits for AR_PHY_RIFS. */ 584 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 585 586 /* Bits for AR_PHY_RX_DELAY. */ 587 #define AR_PHY_RX_DELAY_DELAY_M 0x00003fff 588 #define AR_PHY_RX_DELAY_DELAY_S 0 589 590 /* Bits for AR_PHY_XPA_TIMING_CTL. */ 591 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_M 0x000000ff 592 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 593 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_M 0x0000ff00 594 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 595 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_M 0x00ff0000 596 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 597 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_M 0xff000000 598 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 599 600 /* Bits for AR_PHY_SWITCH_CHAIN. */ 601 #define AR_SWITCH_TABLE_ALL_M 0x00000fff 602 #define AR_SWITCH_TABLE_ALL_S 0 603 604 /* Bits for AR_PHY_SWITCH_COM. */ 605 #define AR_SWITCH_TABLE_COM_ALL_M 0x0000ffff 606 #define AR_SWITCH_TABLE_COM_ALL_S 0 607 608 /* Bits for AR_SWITCH_TABLE_COM_2. */ 609 #define AR_SWITCH_TABLE_COM_2_ALL_M 0x00ffffff 610 #define AR_SWITCH_TABLE_COM_2_ALL_S 0 611 612 /* Bits for AR_PHY_AGC_CONTROL. */ 613 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 614 #define AR_PHY_AGC_CONTROL_NF 0x00000002 615 #define AR_PHY_AGC_CONTROL_YCOK_MAX_M 0x000003c0 616 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 617 #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 618 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 619 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 620 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 621 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 622 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 623 624 /* Bits for AR_PHY_CALMODE. */ 625 #define AR_PHY_CALMODE_IQ 0x00000000 626 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 627 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 628 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 629 630 /* Bits for AR_PHY_FCAL_2_0. */ 631 #define AR_PHY_FCAL20_CAP_STATUS_0_M 0x01f00000 632 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20 633 634 /* Bits for AR_PHY_SYNTH_CONTROL. */ 635 #define AR9380_BMODE 0x20000000 636 637 /* Bits for AR_PHY_ANALOG_SWAP. */ 638 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 639 640 /* Bits for AR_PHY_ADDAC_PARA_CTL. */ 641 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 642 643 /* Bits for AR_PHY_TEST. */ 644 #define AR_PHY_TEST_RFSILENT_BB 0x00002000 645 #define AR_PHY_TEST_BBB_OBS_SEL_M 0x00780000 646 #define AR_PHY_TEST_BBB_OBS_SEL_S 19 647 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 0x00800000 648 #define AR_PHY_TEST_CHAIN_SEL_M 0xc0000000 649 #define AR_PHY_TEST_CHAIN_SEL_S 30 650 651 /* Bits for AR_PHY_TEST_CTL_STATUS. */ 652 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x00000001 653 #define AR_PHY_TEST_CTL_TX_OBS_SEL_M 0x0000001c 654 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 655 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_M 0x00000060 656 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 657 #define AR_PHY_TEST_CTL_TSTADC_EN 0x00000100 658 #define AR_PHY_TEST_CTL_RX_OBS_SEL_M 0x00003c00 659 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 660 661 /* Bits for AR_PHY_CHAN_INFO_MEMORY. */ 662 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x00000001 663 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 664 665 /* Bits for AR_PHY_CHAN_INFO_GAIN_0. */ 666 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0x00000fff 667 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 668 669 /* Bits for AR_PHY_CCK_TX_CTRL. */ 670 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 671 672 /* Bits for AR_PHY_PWRTX_RATE5. */ 673 #define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_M 0x0000003f 674 #define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_S 0 675 676 /* Bits for AR_PHY_PWRTX_MAX. */ 677 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 678 679 /* Bits for AR_PHY_TPC_1. */ 680 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001 681 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_M 0x0000003e 682 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1 683 684 /* Bits for AR_PHY_TPC_5_B(i). */ 685 #define AR_PHY_TPC_5_PD_GAIN_OVERLAP_M 0x0000000f 686 #define AR_PHY_TPC_5_PD_GAIN_OVERLAP_S 0 687 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_M 0x000003f0 688 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_S 4 689 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_M 0x0000fc00 690 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_S 10 691 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_M 0x003f0000 692 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_S 16 693 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_M 0x0fc00000 694 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_S 22 695 696 /* Bits for AR_PHY_TPC_6_B(i). */ 697 #define AR_PHY_TPC_6_ERROR_EST_MODE_M 0x03000000 698 #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 699 700 /* Bits for AR_PHY_TPC_11_B(i). */ 701 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_M 0x00ff0000 702 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16 703 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_M 0xff000000 704 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_S 24 705 706 /* Bits for AR_PHY_TPC_12. */ 707 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_M 0x3e000000 708 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25 709 710 /* Bits for AR_PHY_TPC_18. */ 711 #define AR_PHY_TPC_18_THERM_CAL_M 0x000000ff 712 #define AR_PHY_TPC_18_THERM_CAL_S 0 713 #define AR_PHY_TPC_18_VOLT_CAL_M 0x0000ff00 714 #define AR_PHY_TPC_18_VOLT_CAL_S 8 715 716 /* Bits for AR_PHY_TPC_19. */ 717 #define AR_PHY_TPC_19_ALPHA_THERM_M 0x000000ff 718 #define AR_PHY_TPC_19_ALPHA_THERM_S 0 719 #define AR_PHY_TPC_19_ALPHA_VOLT_M 0x001f0000 720 #define AR_PHY_TPC_19_ALPHA_VOLT_S 16 721 722 /* Bits for AR_PHY_BB_THERM_ADC_1. */ 723 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_M 0x000000ff 724 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0 725 726 /* Bits for AR_PHY_BB_THERM_ADC_4. */ 727 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_M 0x000000ff 728 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S 0 729 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_M 0x0000ff00 730 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_S 8 731 732 /* Bits for AR_PHY_TX_FORCED_GAIN. */ 733 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001 734 #define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_M 0x0000000e 735 #define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_S 1 736 #define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_M 0x00000030 737 #define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_S 4 738 #define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_M 0x000003c0 739 #define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_S 6 740 #define AR_PHY_TX_FORCED_GAIN_PADRVGNA_M 0x00003c00 741 #define AR_PHY_TX_FORCED_GAIN_PADRVGNA_S 10 742 #define AR_PHY_TX_FORCED_GAIN_PADRVGNB_M 0x0003c000 743 #define AR_PHY_TX_FORCED_GAIN_PADRVGNB_S 14 744 #define AR_PHY_TX_FORCED_GAIN_PADRVGNC_M 0x003c0000 745 #define AR_PHY_TX_FORCED_GAIN_PADRVGNC_S 18 746 #define AR_PHY_TX_FORCED_GAIN_PADRVGND_M 0x00c00000 747 #define AR_PHY_TX_FORCED_GAIN_PADRVGND_S 22 748 #define AR_PHY_TX_FORCED_GAIN_ENABLE_PAL 0x01000000 749 750 /* Bits for AR_PHY_TXGAIN_TABLE(i). */ 751 #define AR_PHY_TXGAIN_TXBB1DBGAIN_M 0x00000007 752 #define AR_PHY_TXGAIN_TXBB1DBGAIN_S 0 753 #define AR_PHY_TXGAIN_TXBB6DBGAIN_M 0x00000018 754 #define AR_PHY_TXGAIN_TXBB6DBGAIN_S 3 755 #define AR_PHY_TXGAIN_TXMXRGAIN_M 0x000001e0 756 #define AR_PHY_TXGAIN_TXMXRGAIN_S 5 757 #define AR_PHY_TXGAIN_PADRVGNA_M 0x00001e00 758 #define AR_PHY_TXGAIN_PADRVGNA_S 9 759 #define AR_PHY_TXGAIN_PADRVGNB_M 0x0001e000 760 #define AR_PHY_TXGAIN_PADRVGNB_S 13 761 #define AR_PHY_TXGAIN_PADRVGNC_M 0x001e0000 762 #define AR_PHY_TXGAIN_PADRVGNC_S 17 763 #define AR_PHY_TXGAIN_PADRVGND_M 0x00600000 764 #define AR_PHY_TXGAIN_PADRVGND_S 21 765 #define AR_PHY_TXGAIN_INDEX_M 0xff000000 766 #define AR_PHY_TXGAIN_INDEX_S 24 767 768 /* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */ 769 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M 0x01fc0000 770 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 771 772 /* Bits for AR_PHY_TX_IQCAL_START. */ 773 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 774 775 /* Bits for AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i). */ 776 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_M 0x00003fff 777 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0 778 779 /* Bits for AR_PHY_TX_IQCAL_STATUS_B(i). */ 780 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 781 782 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL1. */ 783 #define AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE 0x00000001 784 #define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_M 0x0000007e 785 #define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_S 1 786 #define AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE 0x00000100 787 #define AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE 0x00000200 788 #define AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE 0x00000400 789 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE 0x00000800 790 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_M 0x0003f000 791 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_S 12 792 793 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL3. */ 794 #define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_M 0x0000003f 795 #define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_S 0 796 #define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_M 0x00000fc0 797 #define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_S 6 798 #define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_M 0x0001f000 799 #define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_S 12 800 #define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_M 0x000e0000 801 #define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_S 17 802 #define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_M 0x00f00000 803 #define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_S 20 804 #define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_M 0x0f000000 805 #define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_S 24 806 #define AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE 0x20000000 807 808 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL4. */ 809 #define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_M 0x00000fff 810 #define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_S 0 811 #define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_M 0x0000f000 812 #define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_S 12 813 #define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_M 0x03ff0000 814 #define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_S 16 815 816 /* Bits for AR_PHY_PAPRD_TRAINER_STAT1. */ 817 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE 0x00000001 818 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_INCOMPLETE 0x00000002 819 #define AR_PHY_PAPRD_TRAINER_STAT1_CORR_ERR 0x00000004 820 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_ACTIVE 0x00000008 821 #define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_M 0x000001f0 822 #define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_S 4 823 #define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_M 0x0001fe00 824 #define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_S 9 825 826 /* Bits for AR_PHY_PAPRD_TRAINER_STAT2. */ 827 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_M 0x0000ffff 828 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_S 0 829 #define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_M 0x001f0000 830 #define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_S 16 831 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_M 0x00600000 832 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_S 21 833 834 /* Bits for AR_PHY_PAPRD_TRAINER_STAT3. */ 835 #define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_M 0x000fffff 836 #define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_S 0 837 838 /* Bits for AR_PHY_65NM_CH0_SYNTH4. */ 839 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 840 841 /* Bits for AR_PHY_65NM_CH0_SYNTH7. */ 842 #define AR9380_FRACMODE 0x40000000 843 #define AR9380_LOAD_SYNTH 0x80000000 844 845 /* Bits for AR_PHY_65NM_CH0_BIAS1. */ 846 #define AR_PHY_65NM_CH0_BIAS1_0_M 0x000001c0 847 #define AR_PHY_65NM_CH0_BIAS1_0_S 6 848 #define AR_PHY_65NM_CH0_BIAS1_1_M 0x00000e00 849 #define AR_PHY_65NM_CH0_BIAS1_1_S 9 850 #define AR_PHY_65NM_CH0_BIAS1_2_M 0x00007000 851 #define AR_PHY_65NM_CH0_BIAS1_2_S 12 852 #define AR_PHY_65NM_CH0_BIAS1_3_M 0x00038000 853 #define AR_PHY_65NM_CH0_BIAS1_3_S 15 854 #define AR_PHY_65NM_CH0_BIAS1_4_M 0x001c0000 855 #define AR_PHY_65NM_CH0_BIAS1_4_S 18 856 #define AR_PHY_65NM_CH0_BIAS1_5_M 0x00e00000 857 #define AR_PHY_65NM_CH0_BIAS1_5_S 21 858 859 /* Bits for AR_PHY_65NM_CH0_BIAS2. */ 860 #define AR_PHY_65NM_CH0_BIAS2_0_M 0x000000e0 861 #define AR_PHY_65NM_CH0_BIAS2_0_S 5 862 #define AR_PHY_65NM_CH0_BIAS2_1_M 0x00000700 863 #define AR_PHY_65NM_CH0_BIAS2_1_S 8 864 #define AR_PHY_65NM_CH0_BIAS2_2_M 0x00003800 865 #define AR_PHY_65NM_CH0_BIAS2_2_S 11 866 #define AR_PHY_65NM_CH0_BIAS2_3_M 0x0001c000 867 #define AR_PHY_65NM_CH0_BIAS2_3_S 14 868 #define AR_PHY_65NM_CH0_BIAS2_4_M 0x000e0000 869 #define AR_PHY_65NM_CH0_BIAS2_4_S 17 870 #define AR_PHY_65NM_CH0_BIAS2_5_M 0x00700000 871 #define AR_PHY_65NM_CH0_BIAS2_5_S 20 872 #define AR_PHY_65NM_CH0_BIAS2_6_M 0x03800000 873 #define AR_PHY_65NM_CH0_BIAS2_6_S 23 874 #define AR_PHY_65NM_CH0_BIAS2_7_M 0x1c000000 875 #define AR_PHY_65NM_CH0_BIAS2_7_S 26 876 #define AR_PHY_65NM_CH0_BIAS2_8_M 0xe0000000 877 #define AR_PHY_65NM_CH0_BIAS2_8_S 29 878 879 /* Bits for AR_PHY_65NM_CH0_BIAS4. */ 880 #define AR_PHY_65NM_CH0_BIAS4_0_M 0x03800000 881 #define AR_PHY_65NM_CH0_BIAS4_0_S 23 882 #define AR_PHY_65NM_CH0_BIAS4_1_M 0x1c000000 883 #define AR_PHY_65NM_CH0_BIAS4_1_S 26 884 #define AR_PHY_65NM_CH0_BIAS4_2_M 0xe0000000 885 #define AR_PHY_65NM_CH0_BIAS4_2_S 29 886 887 /* Bits for AR_PHY_65NM_CH0_RXTX4. */ 888 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 889 890 /* Bits for AR9485_PHY_65NM_CH0_TOP2. */ 891 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M 0x0000f000 892 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_S 12 893 894 /* Bits for AR_PHY_65NM_CH0_TOP. */ 895 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_M 0x00000300 896 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S 8 897 898 /* Bits for AR_PHY_65NM_CH0_THERM. */ 899 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_M 0x00000003 900 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0 901 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004 902 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_M 0x0000ff00 903 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 904 #define AR_PHY_65NM_CH0_THERM_START 0x20000000 905 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 906 907 /* Bits for AR9485_PHY_CH0_XTAL. */ 908 #define AR9485_PHY_CH0_XTAL_CAPINDAC_M 0x7f000000 909 #define AR9485_PHY_CH0_XTAL_CAPINDAC_S 24 910 #define AR9485_PHY_CH0_XTAL_CAPOUTDAC_M 0x00fe0000 911 #define AR9485_PHY_CH0_XTAL_CAPOUTDAC_S 17 912 913 /* Bits for AR_PHY_PMU1. */ 914 #define AR_PHY_PMU1_PWD 0x00000001 915 916 /* Bits for AR_PHY_PMU2. */ 917 #define AR_PHY_PMU2_PGM 0x00200000 918 919 /* 920 * OTP registers. 921 */ 922 #define AR_OTP_BASE(i) (0x14000 + (i) * 4) 923 #define AR_OTP_STATUS 0x15f18 924 #define AR_OTP_READ_DATA 0x15f1c 925 926 /* Bits for AR_OTP_STATUS. */ 927 #define AR_OTP_STATUS_TYPE_M 0x00000007 928 #define AR_OTP_STATUS_TYPE_S 0 929 #define AR_OTP_STATUS_SM_BUSY 0x1 930 #define AR_OTP_STATUS_ACCESS_BUSY 0x2 931 #define AR_OTP_STATUS_VALID 0x4 932 933 934 #define AR9003_MAX_CHAINS 3 935 936 #define AR9003_TX_QDEPTH 8 937 #define AR9003_RX_LP_QDEPTH 128 938 #define AR9003_RX_HP_QDEPTH 16 939 940 #define AR9003_NTXSTATUS 64 941 942 /* Maximum number of DMA segments per Tx descriptor. */ 943 #define AR9003_MAX_SCATTER 4 944 945 /* 946 * Tx DMA descriptor. 947 */ 948 struct ar_tx_desc { 949 uint32_t ds_info; 950 uint32_t ds_link; 951 struct { 952 uint32_t ds_data; 953 uint32_t ds_ctl; 954 } __packed ds_segs[AR9003_MAX_SCATTER]; 955 uint32_t ds_ctl10; 956 uint32_t ds_ctl11; 957 uint32_t ds_ctl12; 958 uint32_t ds_ctl13; 959 uint32_t ds_ctl14; 960 uint32_t ds_ctl15; 961 uint32_t ds_ctl16; 962 uint32_t ds_ctl17; 963 uint32_t ds_ctl18; 964 uint32_t ds_ctl19; 965 uint32_t ds_ctl20; 966 uint32_t ds_ctl21; 967 uint32_t ds_ctl22; 968 /* 969 * Padding to make Tx descriptors 128 bytes such that they will 970 * not cross a 4KB boundary. 971 */ 972 uint32_t pad[9]; 973 } __packed __attribute__((aligned(4))); 974 975 /* Bits for ds_info. */ 976 #define AR_TXI_DESC_NDWORDS_M 0x000000ff 977 #define AR_TXI_DESC_NDWORDS_S 0 978 #define AR_TXI_QCU_NUM_M 0x00000f00 979 #define AR_TXI_QCU_NUM_S 8 980 #define AR_TXI_CTRL_STAT 0x00004000 981 #define AR_TXI_DESC_TX 0x00008000 982 #define AR_TXI_DESC_ID_M 0xffff0000 983 #define AR_TXI_DESC_ID_S 16 984 #define AR_VENDOR_ATHEROS 0x168c /* NB: PCI_VENDOR_ATHEROS */ 985 986 /* Bits for ds_ctl. */ 987 #define AR_TXC_BUF_LEN_M 0x0fff0000 988 #define AR_TXC_BUF_LEN_S 16 989 990 /* Bits for ds_ctl10. */ 991 #define AR_TXC10_PTR_CHK_SUM_M 0x0000ffff 992 #define AR_TXC10_PTR_CHK_SUM_S 0 993 994 /* Bits for ds_ctl11. */ 995 #define AR_TXC11_FRAME_LEN_M 0x00000fff 996 #define AR_TXC11_FRAME_LEN_S 0 997 #define AR_TXC11_XMIT_POWER_M 0x003f0000 998 #define AR_TXC11_XMIT_POWER_S 16 999 #define AR_TXC11_RTS_ENABLE 0x00400000 1000 #define AR_TXC11_CLR_DEST_MASK 0x01000000 1001 #define AR_TXC11_DEST_IDX_VALID 0x40000000 1002 #define AR_TXC11_CTS_ENABLE 0x80000000 1003 1004 /* Bits for ds_ctl12. */ 1005 #define AR_TXC12_PAPRD_CHAIN_MASK_M 0x00000e00 1006 #define AR_TXC12_PAPRD_CHAIN_MASK_S 9 1007 #define AR_TXC12_DEST_IDX_M 0x000fe000 1008 #define AR_TXC12_DEST_IDX_S 13 1009 #define AR_TXC12_FRAME_TYPE_M 0x00f00000 1010 #define AR_TXC12_FRAME_TYPE_S 20 1011 #define AR_FRAME_TYPE_NORMAL 0 1012 #define AR_FRAME_TYPE_ATIM 1 1013 #define AR_FRAME_TYPE_PSPOLL 2 1014 #define AR_FRAME_TYPE_BEACON 3 1015 #define AR_FRAME_TYPE_PROBE_RESP 4 1016 #define AR_TXC12_NO_ACK 0x01000000 1017 1018 /* Bits for ds_ctl13. */ 1019 #define AR_TXC13_BURST_DUR_M 0x00007fff 1020 #define AR_TXC13_BURST_DUR_S 0 1021 #define AR_TXC13_DUR_UPDATE_ENA 0x00008000 1022 #define AR_TXC13_XMIT_DATA_TRIES0_M 0x000f0000 1023 #define AR_TXC13_XMIT_DATA_TRIES0_S 16 1024 #define AR_TXC13_XMIT_DATA_TRIES1_M 0x00f00000 1025 #define AR_TXC13_XMIT_DATA_TRIES1_S 20 1026 #define AR_TXC13_XMIT_DATA_TRIES2_M 0x0f000000 1027 #define AR_TXC13_XMIT_DATA_TRIES2_S 24 1028 #define AR_TXC13_XMIT_DATA_TRIES3_M 0xf0000000 1029 #define AR_TXC13_XMIT_DATA_TRIES3_S 28 1030 1031 /* Bits for ds_ctl14. */ 1032 #define AR_TXC14_XMIT_RATE0_M 0x000000ff 1033 #define AR_TXC14_XMIT_RATE0_S 0 1034 #define AR_TXC14_XMIT_RATE1_M 0x0000ff00 1035 #define AR_TXC14_XMIT_RATE1_S 8 1036 #define AR_TXC14_XMIT_RATE2_M 0x00ff0000 1037 #define AR_TXC14_XMIT_RATE2_S 16 1038 #define AR_TXC14_XMIT_RATE3_M 0xff000000 1039 #define AR_TXC14_XMIT_RATE3_S 24 1040 1041 /* Bits for ds_ctl15. */ 1042 #define AR_TXC15_PACKET_DUR0_M 0x00007fff 1043 #define AR_TXC15_PACKET_DUR0_S 0 1044 #define AR_TXC15_RTSCTS_QUAL0 0x00008000 1045 #define AR_TXC15_PACKET_DUR1_M 0x7fff0000 1046 #define AR_TXC15_PACKET_DUR1_S 16 1047 #define AR_TXC15_RTSCTS_QUAL1 0x80000000 1048 /* Shortcut. */ 1049 #define AR_TXC15_RTSCTS_QUAL01 \ 1050 (AR_TXC15_RTSCTS_QUAL0 | AR_TXC15_RTSCTS_QUAL1) 1051 1052 /* Bits for ds_ctl16. */ 1053 #define AR_TXC16_PACKET_DUR2_M 0x00007fff 1054 #define AR_TXC16_PACKET_DUR2_S 0 1055 #define AR_TXC16_RTSCTS_QUAL2 0x00008000 1056 #define AR_TXC16_PACKET_DUR3_M 0x7fff0000 1057 #define AR_TXC16_PACKET_DUR3_S 16 1058 #define AR_TXC16_RTSCTS_QUAL3 0x80000000 1059 /* Shortcut. */ 1060 #define AR_TXC16_RTSCTS_QUAL23 \ 1061 (AR_TXC16_RTSCTS_QUAL2 | AR_TXC16_RTSCTS_QUAL3) 1062 1063 /* Bits for ds_ctl17. */ 1064 #define AR_TXC17_ENCR_TYPE_M 0x0c000000 1065 #define AR_TXC17_ENCR_TYPE_S 26 1066 #define AR_ENCR_TYPE_CLEAR 0 1067 #define AR_ENCR_TYPE_WEP 1 1068 #define AR_ENCR_TYPE_AES 2 1069 #define AR_ENCR_TYPE_TKIP 3 1070 1071 /* Bits for ds_ctl18. */ 1072 #define AR_TXC18_2040_0 0x00000001 1073 #define AR_TXC18_GI0 0x00000002 1074 #define AR_TXC18_CHAIN_SEL0_M 0x0000001c 1075 #define AR_TXC18_CHAIN_SEL0_S 2 1076 #define AR_TXC18_2040_1 0x00000020 1077 #define AR_TXC18_GI1 0x00000040 1078 #define AR_TXC18_CHAIN_SEL1_M 0x00000380 1079 #define AR_TXC18_CHAIN_SEL1_S 7 1080 #define AR_TXC18_2040_2 0x00000400 1081 #define AR_TXC18_GI2 0x00000800 1082 #define AR_TXC18_CHAIN_SEL2_M 0x00007000 1083 #define AR_TXC18_CHAIN_SEL2_S 12 1084 #define AR_TXC18_2040_3 0x00008000 1085 #define AR_TXC18_GI3 0x00010000 1086 #define AR_TXC18_CHAIN_SEL3_M 0x000e0000 1087 #define AR_TXC18_CHAIN_SEL3_S 17 1088 #define AR_TXC18_RTSCTS_RATE_M 0x0ff00000 1089 #define AR_TXC18_RTSCTS_RATE_S 20 1090 /* Shortcuts. */ 1091 #define AR_TXC18_2040_0123 \ 1092 (AR_TXC18_2040_0 | AR_TXC18_2040_1 | AR_TXC18_2040_2 | AR_TXC18_2040_3) 1093 #define AR_TXC18_GI0123 \ 1094 (AR_TXC18_GI0 | AR_TXC18_GI1 | AR_TXC18_GI2 | AR_TXC18_GI3) 1095 1096 /* Bits for ds_ctl19. */ 1097 #define AR_TXC19_NOT_SOUNDING 0x20000000 1098 1099 1100 /* 1101 * Tx status DMA descriptor. 1102 */ 1103 struct ar_tx_status { 1104 uint32_t ds_info; 1105 uint32_t ds_status1; 1106 uint32_t ds_status2; 1107 uint32_t ds_status3; 1108 uint32_t ds_status4; 1109 uint32_t ds_status5; 1110 uint32_t ds_status6; 1111 uint32_t ds_status7; 1112 uint32_t ds_status8; 1113 } __packed __attribute__((aligned(4))); 1114 1115 /* Bits for ds_status3. */ 1116 #define AR_TXS3_EXCESSIVE_RETRIES 0x00000002 1117 #define AR_TXS3_FIFO_UNDERRUN 0x00000004 1118 #define AR_TXS3_RTS_FAIL_CNT_M 0x000000f0 1119 #define AR_TXS3_RTS_FAIL_CNT_S 4 1120 #define AR_TXS3_DATA_FAIL_CNT_M 0x00000f00 1121 #define AR_TXS3_DATA_FAIL_CNT_S 8 1122 #define AR_TXS3_TX_DELIM_UNDERRUN 0x00010000 1123 #define AR_TXS3_TX_DATA_UNDERRUN 0x00020000 1124 /* Shortcut. */ 1125 #define AR_TXS3_UNDERRUN \ 1126 (AR_TXS3_FIFO_UNDERRUN | \ 1127 AR_TXS3_TX_DELIM_UNDERRUN | \ 1128 AR_TXS3_TX_DATA_UNDERRUN) 1129 1130 /* Bits for ds_status8. */ 1131 #define AR_TXS8_DONE 0x00000001 1132 #define AR_TXS8_FINAL_IDX_M 0x00600000 1133 #define AR_TXS8_FINAL_IDX_S 21 1134 1135 /* 1136 * Rx status DMA descriptor. 1137 */ 1138 struct ar_rx_status { 1139 uint32_t ds_info; 1140 uint32_t ds_status1; 1141 uint32_t ds_status2; 1142 uint32_t ds_status3; 1143 uint32_t ds_status4; 1144 uint32_t ds_status5; 1145 uint32_t ds_status6; 1146 uint32_t ds_status7; 1147 uint32_t ds_status8; 1148 uint32_t ds_status9; 1149 uint32_t ds_status10; 1150 uint32_t ds_status11; 1151 } __packed __attribute__((aligned(4))); 1152 1153 /* Bits for ds_info. */ 1154 #define AR_RXI_CTRL_STAT 0x00004000 1155 #define AR_RXI_DESC_TX 0x00008000 1156 #define AR_RXI_DESC_ID_M 0xffff0000 1157 #define AR_RXI_DESC_ID_S 16 1158 1159 /* Bits for ds_status1. */ 1160 #define AR_RXS1_RATE_M 0x000003fc 1161 #define AR_RXS1_RATE_S 2 1162 1163 /* Bits for ds_status2. */ 1164 #define AR_RXS2_DATA_LEN_M 0x00000fff 1165 #define AR_RXS2_DATA_LEN_S 0 1166 1167 /* Bits for ds_status4. */ 1168 #define AR_RXS4_GI 0x00000001 1169 #define AR_RXS4_ANTENNA_M 0xffffff00 1170 #define AR_RXS4_ANTENNA_S 8 1171 1172 /* Bits for ds_status5. */ 1173 #define AR_RXS5_RSSI_COMBINED_M 0xff000000 1174 #define AR_RXS5_RSSI_COMBINED_S 24 1175 1176 /* Bits for ds_status11. */ 1177 #define AR_RXS11_DONE 0x00000001 1178 #define AR_RXS11_FRAME_OK 0x00000002 1179 #define AR_RXS11_CRC_ERR 0x00000004 1180 #define AR_RXS11_DECRYPT_CRC_ERR 0x00000008 1181 #define AR_RXS11_PHY_ERR 0x00000010 1182 #define AR_RXS11_PHY_ERR_CODE_M 0x0000ff00 1183 #define AR_RXS11_PHY_ERR_CODE_S 8 1184 #define AR_RXS11_MICHAEL_ERR 0x00000020 1185 1186 /* 1187 * AR9003 family common ROM structures. 1188 */ 1189 #define AR_EEP_COMPRESS_NONE 0 1190 #define AR_EEP_COMPRESS_LZMA 1 1191 #define AR_EEP_COMPRESS_PAIRS 2 1192 #define AR_EEP_COMPRESS_BLOCK 3 1193 1194 struct ar_cal_target_power_leg { 1195 uint8_t tPow2x[4]; 1196 } __packed; 1197 1198 struct ar_cal_target_power_ht { 1199 uint8_t tPow2x[14]; 1200 } __packed; 1201