1 /* $OpenBSD: if_auereg.h,v 1.18 2015/06/18 10:02:49 mpi Exp $ */ 2 /* $NetBSD: if_auereg.h,v 1.16 2001/10/10 02:14:17 augustss Exp $ */ 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/usb/if_auereg.h,v 1.2 2000/01/08 06:52:36 wpaul Exp $ 35 */ 36 37 /* 38 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 39 * chip. The Pegasus uses a total of four USB endpoints: the control 40 * endpoint (0), a bulk read endpoint for receiving packets (1), 41 * a bulk write endpoint for sending packets (2) and an interrupt 42 * endpoint for passing RX and TX status (3). Endpoint 0 is used 43 * to read and write the ethernet module's registers. All registers 44 * are 8 bits wide. 45 * 46 * Packet transfer is done in 64 byte chunks. The last chunk in a 47 * transfer is denoted by having a length less that 64 bytes. For 48 * the RX case, the data includes an optional RX status word. 49 */ 50 51 #define AUE_UR_READREG 0xF0 52 #define AUE_UR_WRITEREG 0xF1 53 54 /* 55 * Note that while the ADMtek technically has four 56 * endpoints, the control endpoint (endpoint 0) is 57 * regarded as special by the USB code and drivers 58 * don't have direct access to it. (We access it 59 * using usbd_do_request() when reading/writing 60 * registers.) Consequently, our endpoint indexes 61 * don't match those in the ADMtek Pegasus manual: 62 * we consider the RX data endpoint to be index 0 63 * and work up from there. 64 */ 65 #define AUE_ENDPT_RX 0x0 66 #define AUE_ENDPT_TX 0x1 67 #define AUE_ENDPT_INTR 0x2 68 #define AUE_ENDPT_MAX 0x3 69 70 #define AUE_CTL0 0x00 71 #define AUE_CTL1 0x01 72 #define AUE_CTL2 0x02 73 #define AUE_MAR0 0x08 74 #define AUE_MAR1 0x09 75 #define AUE_MAR2 0x0A 76 #define AUE_MAR3 0x0B 77 #define AUE_MAR4 0x0C 78 #define AUE_MAR5 0x0D 79 #define AUE_MAR6 0x0E 80 #define AUE_MAR7 0x0F 81 #define AUE_MAR AUE_MAR0 82 #define AUE_PAR0 0x10 83 #define AUE_PAR1 0x11 84 #define AUE_PAR2 0x12 85 #define AUE_PAR3 0x13 86 #define AUE_PAR4 0x14 87 #define AUE_PAR5 0x15 88 #define AUE_PAR AUE_PAR0 89 #define AUE_PAUSE0 0x18 90 #define AUE_PAUSE1 0x19 91 #define AUE_PAUSE AUE_PAUSE0 92 #define AUE_RX_FLOWCTL_CNT 0x1A 93 #define AUE_RX_FLOWCTL_FIFO 0x1B 94 #define AUE_REG_1D 0x1D 95 #define AUE_EE_REG 0x20 96 #define AUE_EE_DATA0 0x21 97 #define AUE_EE_DATA1 0x22 98 #define AUE_EE_DATA AUE_EE_DATA0 99 #define AUE_EE_CTL 0x23 100 #define AUE_PHY_ADDR 0x25 101 #define AUE_PHY_DATA0 0x26 102 #define AUE_PHY_DATA1 0x27 103 #define AUE_PHY_DATA AUE_PHY_DATA0 104 #define AUE_PHY_CTL 0x28 105 #define AUE_USB_STS 0x2A 106 #define AUE_TXSTAT0 0x2B 107 #define AUE_TXSTAT1 0x2C 108 #define AUE_TXSTAT AUE_TXSTAT0 109 #define AUE_RXSTAT 0x2D 110 #define AUE_PKTLOST0 0x2E 111 #define AUE_PKTLOST1 0x2F 112 #define AUE_PKTLOST AUE_PKTLOST0 113 114 #define AUE_REG_7B 0x7B 115 #define AUE_GPIO0 0x7E 116 #define AUE_GPIO1 0x7F 117 #define AUE_REG_81 0x81 118 119 #define AUE_CTL0_INCLUDE_RXCRC 0x01 120 #define AUE_CTL0_ALLMULTI 0x02 121 #define AUE_CTL0_STOP_BACKOFF 0x04 122 #define AUE_CTL0_RXSTAT_APPEND 0x08 123 #define AUE_CTL0_WAKEON_ENB 0x10 124 #define AUE_CTL0_RXPAUSE_ENB 0x20 125 #define AUE_CTL0_RX_ENB 0x40 126 #define AUE_CTL0_TX_ENB 0x80 127 128 #define AUE_CTL1_HOMELAN 0x04 129 #define AUE_CTL1_RESETMAC 0x08 130 #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ 131 #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ 132 #define AUE_CTL1_DELAYHOME 0x40 133 134 #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ 135 #define AUE_CTL2_RX_BADFRAMES 0x02 136 #define AUE_CTL2_RX_PROMISC 0x04 137 #define AUE_CTL2_LOOPBACK 0x08 138 #define AUE_CTL2_EEPROMWR_ENB 0x10 139 #define AUE_CTL2_EEPROM_LOAD 0x20 140 141 #define AUE_EECTL_WRITE 0x01 142 #define AUE_EECTL_READ 0x02 143 #define AUE_EECTL_DONE 0x04 144 145 #define AUE_PHYCTL_PHYREG 0x1F 146 #define AUE_PHYCTL_WRITE 0x20 147 #define AUE_PHYCTL_READ 0x40 148 #define AUE_PHYCTL_DONE 0x80 149 150 #define AUE_USBSTS_SUSPEND 0x01 151 #define AUE_USBSTS_RESUME 0x02 152 153 #define AUE_TXSTAT0_JABTIMO 0x04 154 #define AUE_TXSTAT0_CARLOSS 0x08 155 #define AUE_TXSTAT0_NOCARRIER 0x10 156 #define AUE_TXSTAT0_LATECOLL 0x20 157 #define AUE_TXSTAT0_EXCESSCOLL 0x40 158 #define AUE_TXSTAT0_UNDERRUN 0x80 159 160 #define AUE_TXSTAT1_PKTCNT 0x0F 161 #define AUE_TXSTAT1_FIFO_EMPTY 0x40 162 #define AUE_TXSTAT1_FIFO_FULL 0x80 163 164 #define AUE_RXSTAT_OVERRUN 0x01 165 #define AUE_RXSTAT_PAUSE 0x02 166 167 #define AUE_GPIO_IN0 0x01 168 #define AUE_GPIO_OUT0 0x02 169 #define AUE_GPIO_SEL0 0x04 170 #define AUE_GPIO_IN1 0x08 171 #define AUE_GPIO_OUT1 0x10 172 #define AUE_GPIO_SEL1 0x20 173 174 struct aue_intrpkt { 175 u_int8_t aue_txstat0; 176 u_int8_t aue_txstat1; 177 u_int8_t aue_rxstat; 178 u_int8_t aue_rxlostpkt0; 179 u_int8_t aue_rxlostpkt1; 180 u_int8_t aue_wakeupstat; 181 u_int8_t aue_rsvd; 182 u_int8_t _pad; 183 }; 184 #define AUE_INTR_PKTLEN 8 185 186 struct aue_rxpkt { 187 uWord aue_pktlen; 188 uByte aue_rxstat; 189 }; 190 191 #define AUE_RXSTAT_MCAST 0x01 192 #define AUE_RXSTAT_GIANT 0x02 193 #define AUE_RXSTAT_RUNT 0x04 194 #define AUE_RXSTAT_CRCERR 0x08 195 #define AUE_RXSTAT_DRIBBLE 0x10 196 #define AUE_RXSTAT_MASK 0x1E 197 198 199 /*************** The rest belongs in if_auevar.h *************/ 200 201 #define AUE_TX_LIST_CNT 1 202 #define AUE_RX_LIST_CNT 1 203 204 struct aue_softc; 205 206 struct aue_chain { 207 struct aue_softc *aue_sc; 208 struct usbd_xfer *aue_xfer; 209 char *aue_buf; 210 struct mbuf *aue_mbuf; 211 int aue_idx; 212 }; 213 214 struct aue_cdata { 215 struct aue_chain aue_tx_chain[AUE_TX_LIST_CNT]; 216 struct aue_chain aue_rx_chain[AUE_RX_LIST_CNT]; 217 struct aue_intrpkt aue_ibuf; 218 int aue_tx_prod; 219 int aue_tx_cons; 220 int aue_tx_cnt; 221 int aue_rx_prod; 222 }; 223 224 struct aue_softc { 225 struct device aue_dev; 226 227 struct arpcom arpcom; 228 struct mii_data aue_mii; 229 #define GET_IFP(sc) (&(sc)->arpcom.ac_if) 230 #define GET_MII(sc) (&(sc)->aue_mii) 231 232 struct timeout aue_stat_ch; 233 234 struct usbd_device *aue_udev; 235 struct usbd_interface *aue_iface; 236 u_int16_t aue_vendor; 237 u_int16_t aue_product; 238 int aue_ed[AUE_ENDPT_MAX]; 239 struct usbd_pipe *aue_ep[AUE_ENDPT_MAX]; 240 u_int8_t aue_link; 241 struct aue_cdata aue_cdata; 242 243 u_int16_t aue_flags; 244 245 int aue_refcnt; 246 u_int aue_rx_errs; 247 u_int aue_intr_errs; 248 struct timeval aue_rx_notice; 249 250 struct usb_task aue_tick_task; 251 struct usb_task aue_stop_task; 252 253 struct rwlock aue_mii_lock; 254 }; 255 256 #define AUE_TIMEOUT 1000 257 #define AUE_BUFSZ 1536 258 #define AUE_MIN_FRAMELEN 60 259 #define AUE_TX_TIMEOUT 10000 /* ms */ 260 #define AUE_INTR_INTERVAL 100 /* ms */ 261