Searched refs:AndIdx (Results 1 – 2 of 2) sorted by relevance
| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 83 static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, in isDefBetween() argument
85 LiveQueryResult AndLRQ = LR.Query(AndIdx); in isDefBetween()
93 SlotIndex AndIdx = LIS->getInstructionIndex(And).getRegSlot(); in isDefBetween() local
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
212 SlotIndex AndIdx = LIS->ReplaceMachineInstrInMaps(*And, *Andn2); in optimizeVcndVcmpPair() local
229 for (auto I = DefSegment; I != SelLI->end() && I->start <= AndIdx; ++I) { in optimizeVcndVcmpPair()
232 SlotIndex End = I->end < AndIdx.getRegSlot() || I->end.isBlock() ? in optimizeVcndVcmpPair()
233 I->end : AndIdx.getRegSlot(); in optimizeVcndVcmpPair()
237 if (!SelLI->getSegmentContaining(AndIdx.getRegSlot())) in optimizeVcndVcmpPair()
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| /openbsd/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 3146 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT() local
3147 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
3204 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT() local
3205 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
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