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Searched refs:BANK_WIDTH (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v6_0.c84 #define BANK_WIDTH(x) ((x) << 14) macro
409 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
417 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
425 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
452 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
460 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
480 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
[all …]
H A Dgfx_v8_0.c2195 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2199 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2203 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2207 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2211 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2215 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2219 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2223 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2227 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2387 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
[all …]
H A Dgfx_v7_0.c1122 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1126 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1130 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1134 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1138 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1142 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1146 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1150 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1154 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1305 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
[all …]
H A Dcikd.h194 # define BANK_WIDTH(x) ((x) << 0) macro
H A Dsid.h1203 # define BANK_WIDTH(x) ((x) << 14) macro
H A Ddce_v6_0.c1941 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
H A Ddce_v8_0.c1910 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
H A Ddce_v10_0.c1985 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
H A Ddce_v11_0.c2035 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
/openbsd/sys/dev/pci/drm/radeon/
H A Dsi.c2520 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2556 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
[all …]
H A Dcik.c2436 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2440 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2444 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2448 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2452 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2456 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2460 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2464 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2468 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2579 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
[all …]
H A Dsid.h1206 # define BANK_WIDTH(x) ((x) << 14) macro
H A Dcikd.h1260 # define BANK_WIDTH(x) ((x) << 0) macro
/openbsd/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c188 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_gfx8_tiling_info_from_flags()
/openbsd/sys/dev/pci/drm/amd/include/
H A Dnavi10_enum.h1744 typedef enum BANK_WIDTH { enum
1749 } BANK_WIDTH; typedef