1 /* Definitions of target machine for GNU compiler. TMS320C[34]x 2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003 Free Software Foundation, Inc. 4 5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz) 6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl). 7 8 This file is part of GNU CC. 9 10 GNU CC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2, or (at your option) 13 any later version. 14 15 GNU CC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GNU CC; see the file COPYING. If not, write to 22 the Free Software Foundation, 59 Temple Place - Suite 330, 23 Boston, MA 02111-1307, USA. */ 24 25 /* RUN-TIME TARGET SPECIFICATION. */ 26 27 #include "hwint.h" 28 29 #define C4x 1 30 31 #define TARGET_CPU_CPP_BUILTINS() \ 32 do \ 33 { \ 34 if (!TARGET_SMALL) \ 35 builtin_define ("_BIGMODEL"); \ 36 if (!TARGET_MEMPARM) \ 37 builtin_define ("_REGPARM"); \ 38 if (flag_inline_functions \ 39 || flag_inline_trees) \ 40 builtin_define ("_INLINE"); \ 41 if (TARGET_C3X) \ 42 { \ 43 builtin_define ("_TMS320C3x"); \ 44 builtin_define ("_C3x"); \ 45 if (TARGET_C30) \ 46 { \ 47 builtin_define ("_TMS320C30"); \ 48 builtin_define ("_C30"); \ 49 } \ 50 else if (TARGET_C31) \ 51 { \ 52 builtin_define ("_TMS320C31"); \ 53 builtin_define ("_C31"); \ 54 } \ 55 else if (TARGET_C32) \ 56 { \ 57 builtin_define ("_TMS320C32"); \ 58 builtin_define ("_C32"); \ 59 } \ 60 else if (TARGET_C33) \ 61 { \ 62 builtin_define ("_TMS320C33"); \ 63 builtin_define ("_C33"); \ 64 } \ 65 } \ 66 else \ 67 { \ 68 builtin_define ("_TMS320C4x"); \ 69 builtin_define ("_C4x"); \ 70 if (TARGET_C40) \ 71 { \ 72 builtin_define ("_TMS320C40"); \ 73 builtin_define ("_C40"); \ 74 } \ 75 else if (TARGET_C44) \ 76 { \ 77 builtin_define ("_TMS320C44"); \ 78 builtin_define ("_C44"); \ 79 } \ 80 } \ 81 } \ 82 while (0) 83 84 /* Name of the c4x assembler. */ 85 86 #define ASM_PROG "c4x-as" 87 88 /* Name of the c4x linker. */ 89 90 #define LD_PROG "c4x-ld" 91 92 /* Define assembler options. */ 93 94 #define ASM_SPEC "\ 95 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\ 96 %{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \ 97 %{mcpu=30} \ 98 %{mcpu=31} \ 99 %{mcpu=32} \ 100 %{mcpu=33} \ 101 %{mcpu=40} \ 102 %{mcpu=44} \ 103 %{m30} \ 104 %{m31} \ 105 %{m32} \ 106 %{m33} \ 107 %{m40} \ 108 %{m44} \ 109 %{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \ 110 %{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}" 111 112 /* Define linker options. */ 113 114 #define LINK_SPEC "\ 115 %{m30:--architecture c3x} \ 116 %{m31:--architecture c3x} \ 117 %{m32:--architecture c3x} \ 118 %{m33:--architecture c3x} \ 119 %{mcpu=30:--architecture c3x} \ 120 %{mcpu=31:--architecture c3x} \ 121 %{mcpu=32:--architecture c3x} \ 122 %{mcpu=33:--architecture c3x}" 123 124 /* Specify the end file to link with. */ 125 126 #define ENDFILE_SPEC "" 127 128 /* Target compilation option flags. */ 129 130 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */ 131 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */ 132 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */ 133 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */ 134 #define C3X_FLAG 0x0000010 /* Emit C3x code. */ 135 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */ 136 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */ 137 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */ 138 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */ 139 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */ 140 #define BK_FLAG 0x0000400 /* Use BK as general register. */ 141 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */ 142 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */ 143 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */ 144 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */ 145 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */ 146 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */ 147 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */ 148 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */ 149 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */ 150 151 #define C30_FLAG 0x0100000 /* Emit C30 code. */ 152 #define C31_FLAG 0x0200000 /* Emit C31 code. */ 153 #define C32_FLAG 0x0400000 /* Emit C32 code. */ 154 #define C33_FLAG 0x0800000 /* Emit C33 code. */ 155 #define C40_FLAG 0x1000000 /* Emit C40 code. */ 156 #define C44_FLAG 0x2000000 /* Emit C44 code. */ 157 158 /* Run-time compilation parameters selecting different hardware subsets. 159 160 Macro to define tables used to set the flags. 161 This is a list in braces of triplets in braces, 162 each pair being { "NAME", VALUE, "DESCRIPTION" } 163 where VALUE is the bits to set or minus the bits to clear. 164 An empty string NAME is used to identify the default VALUE. */ 165 166 #define TARGET_SWITCHES \ 167 { { "small", SMALL_MEMORY_FLAG, \ 168 N_("Small memory model") }, \ 169 { "big", -SMALL_MEMORY_FLAG, \ 170 N_("Big memory model") }, \ 171 { "mpyi", MPYI_FLAG, \ 172 N_("Use MPYI instruction for C3x") }, \ 173 { "no-mpyi", -MPYI_FLAG, \ 174 N_("Do not use MPYI instruction for C3x") }, \ 175 { "fast-fix", FAST_FIX_FLAG, \ 176 N_("Use fast but approximate float to integer conversion") }, \ 177 { "no-fast-fix", -FAST_FIX_FLAG, \ 178 N_("Use slow but accurate float to integer conversion") }, \ 179 { "rpts", RPTS_FLAG, \ 180 N_("Enable use of RTPS instruction") }, \ 181 { "no-rpts", -RPTS_FLAG, \ 182 N_("Disable use of RTPS instruction") }, \ 183 { "rptb", RPTB_FLAG, \ 184 N_("Enable use of RTPB instruction") }, \ 185 { "no-rptb", -RPTB_FLAG, \ 186 N_("Disable use of RTPB instruction") }, \ 187 { "30", C30_FLAG, \ 188 N_("Generate code for C30 CPU")}, \ 189 { "31", C31_FLAG, \ 190 N_("Generate code for C31 CPU")}, \ 191 { "32", C32_FLAG, \ 192 N_("Generate code for C32 CPU")}, \ 193 { "33", C33_FLAG, \ 194 N_("Generate code for C33 CPU")}, \ 195 { "40", C40_FLAG, \ 196 N_("Generate code for C40 CPU")}, \ 197 { "44", C44_FLAG, \ 198 N_("Generate code for C44 CPU")}, \ 199 { "ti", TI_FLAG, \ 200 N_("Emit code compatible with TI tools")}, \ 201 { "no-ti", -TI_FLAG, \ 202 N_("Emit code to use GAS extensions")}, \ 203 { "paranoid", PARANOID_FLAG, \ 204 N_("Save DP across ISR in small memory model") }, \ 205 { "no-paranoid", -PARANOID_FLAG, \ 206 N_("Don't save DP across ISR in small memory model") }, \ 207 { "isr-dp-reload", PARANOID_FLAG, \ 208 N_("Save DP across ISR in small memory model") }, \ 209 { "no-isr-dp-reload", -PARANOID_FLAG, \ 210 N_("Don't save DP across ISR in small memory model") }, \ 211 { "memparm", MEMPARM_FLAG, \ 212 N_("Pass arguments on the stack") }, \ 213 { "regparm", -MEMPARM_FLAG, \ 214 N_("Pass arguments in registers") }, \ 215 { "devel", DEVEL_FLAG, \ 216 N_("Enable new features under development") }, \ 217 { "no-devel", -DEVEL_FLAG, \ 218 N_("Disable new features under development") }, \ 219 { "bk", BK_FLAG, \ 220 N_("Use the BK register as a general purpose register") }, \ 221 { "no-bk", -BK_FLAG, \ 222 N_("Do not allocate BK register") }, \ 223 { "db", DB_FLAG, \ 224 N_("Enable use of DB instruction") }, \ 225 { "no-db", -DB_FLAG, \ 226 N_("Disable use of DB instruction") }, \ 227 { "debug", DEBUG_FLAG, \ 228 N_("Enable debugging") }, \ 229 { "no-debug", -DEBUG_FLAG, \ 230 N_("Disable debugging") }, \ 231 { "hoist", HOIST_FLAG, \ 232 N_("Force constants into registers to improve hoisting") }, \ 233 { "no-hoist", -HOIST_FLAG, \ 234 N_("Don't force constants into registers") }, \ 235 { "force", FORCE_FLAG, \ 236 N_("Force RTL generation to emit valid 3 operand insns") }, \ 237 { "no-force", -FORCE_FLAG, \ 238 N_("Allow RTL generation to emit invalid 3 operand insns") }, \ 239 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \ 240 N_("Allow unsigned iteration counts for RPTB/DB") }, \ 241 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \ 242 N_("Disallow unsigned iteration counts for RPTB/DB") }, \ 243 { "preserve-float", PRESERVE_FLOAT_FLAG, \ 244 N_("Preserve all 40 bits of FP reg across call") }, \ 245 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \ 246 N_("Only preserve 32 bits of FP reg across call") }, \ 247 { "parallel-insns", PARALLEL_INSN_FLAG, \ 248 N_("Enable parallel instructions") }, \ 249 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \ 250 N_("Disable parallel instructions") }, \ 251 { "parallel-mpy", PARALLEL_MPY_FLAG, \ 252 N_("Enable MPY||ADD and MPY||SUB instructions") }, \ 253 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \ 254 N_("Disable MPY||ADD and MPY||SUB instructions") }, \ 255 { "aliases", ALIASES_FLAG, \ 256 N_("Assume that pointers may be aliased") }, \ 257 { "no-aliases", -ALIASES_FLAG, \ 258 N_("Assume that pointers not aliased") }, \ 259 { "", TARGET_DEFAULT, ""} } 260 261 /* Default target switches. */ 262 263 /* Play safe, not the fastest code. */ 264 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \ 265 | PARALLEL_MPY_FLAG | RPTB_FLAG 266 267 /* Caveats: 268 Max iteration count for RPTB/RPTS is 2^31 + 1. 269 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30. 270 RPTS blocks interrupts. */ 271 272 273 extern int target_flags; 274 275 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */ 276 #define TARGET_SMALL_REG_CLASS 0 277 278 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG) 279 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG)) 280 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG) 281 #define TARGET_RPTS (target_flags & RPTS_FLAG) 282 #define TARGET_TI (target_flags & TI_FLAG) 283 #define TARGET_PARANOID (target_flags & PARANOID_FLAG) 284 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG) 285 #define TARGET_DEVEL (target_flags & DEVEL_FLAG) 286 #define TARGET_RPTB (target_flags & RPTB_FLAG \ 287 && optimize >= 2) 288 #define TARGET_BK (target_flags & BK_FLAG) 289 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG)) 290 #define TARGET_DEBUG (target_flags & DEBUG_FLAG) 291 #define TARGET_HOIST (target_flags & HOIST_FLAG) 292 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG) 293 #define TARGET_FORCE (target_flags & FORCE_FLAG) 294 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG) 295 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \ 296 && optimize >= 2) 297 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \ 298 && (target_flags & PARALLEL_MPY_FLAG)) 299 #define TARGET_ALIASES (target_flags & ALIASES_FLAG) 300 301 #define TARGET_C3X (target_flags & C3X_FLAG) 302 #define TARGET_C30 (target_flags & C30_FLAG) 303 #define TARGET_C31 (target_flags & C31_FLAG) 304 #define TARGET_C32 (target_flags & C32_FLAG) 305 #define TARGET_C33 (target_flags & C33_FLAG) 306 #define TARGET_C40 (target_flags & C40_FLAG) 307 #define TARGET_C44 (target_flags & C44_FLAG) 308 309 /* Define some options to control code generation. */ 310 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL)) 311 /* Nonzero to convert direct memory references into HIGH/LO_SUM pairs 312 during RTL generation. */ 313 #define TARGET_EXPOSE_LDP 0 314 /* Nonzero to force loading of direct memory references into a register. */ 315 #define TARGET_LOAD_DIRECT_MEMS 0 316 317 /* -mrpts allows the use of the RPTS instruction irregardless. 318 -mrpts=max-cycles will use RPTS if the number of cycles is constant 319 and less than max-cycles. */ 320 321 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles) 322 323 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED) 324 325 /* -mcpu=XX with XX = target DSP version number. */ 326 327 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string; 328 329 #define TARGET_OPTIONS \ 330 { {"rpts=", &c4x_rpts_cycles_string, \ 331 N_("Specify maximum number of iterations for RPTS") }, \ 332 {"cpu=", &c4x_cpu_version_string, \ 333 N_("Select CPU to generate code for") } } 334 335 /* Sometimes certain combinations of command options do not make sense 336 on a particular target machine. You can define a macro 337 `OVERRIDE_OPTIONS' to take account of this. This macro, if 338 defined, is executed once just after all the command options have 339 been parsed. */ 340 341 #define OVERRIDE_OPTIONS c4x_override_options () 342 343 /* Define this to change the optimizations performed by default. */ 344 345 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE) 346 347 /* Run Time Target Specification. */ 348 349 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)"); 350 351 /* Storage Layout. */ 352 353 #define BITS_BIG_ENDIAN 0 354 #define BYTES_BIG_ENDIAN 0 355 #define WORDS_BIG_ENDIAN 0 356 357 /* Technically, we are little endian, but we put the floats out as 358 whole longs and this makes GCC put them out in the right order. */ 359 360 #define FLOAT_WORDS_BIG_ENDIAN 1 361 362 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x 363 all integral and floating point data types are stored in memory as 364 32-bits (floating point types can be stored as 40-bits in the 365 extended precision registers), so sizeof(char) = sizeof(short) = 366 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */ 367 368 #define BITS_PER_UNIT 32 369 #define UNITS_PER_WORD 1 370 #define PARM_BOUNDARY 32 371 #define STACK_BOUNDARY 32 372 #define FUNCTION_BOUNDARY 32 373 #define BIGGEST_ALIGNMENT 32 374 #define EMPTY_FIELD_BOUNDARY 32 375 #define STRICT_ALIGNMENT 0 376 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT 377 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */ 378 379 /* If a structure has a floating point field then force structure 380 to have BLKMODE, unless it is the only field. */ 381 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ 382 (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode) 383 384 /* Number of bits in the high and low parts of a two stage 385 load of an immediate constant. */ 386 #define BITS_PER_HIGH 16 387 #define BITS_PER_LO_SUM 16 388 389 /* Define register numbers. */ 390 391 /* Extended-precision registers. */ 392 393 #define R0_REGNO 0 394 #define R1_REGNO 1 395 #define R2_REGNO 2 396 #define R3_REGNO 3 397 #define R4_REGNO 4 398 #define R5_REGNO 5 399 #define R6_REGNO 6 400 #define R7_REGNO 7 401 402 /* Auxiliary (address) registers. */ 403 404 #define AR0_REGNO 8 405 #define AR1_REGNO 9 406 #define AR2_REGNO 10 407 #define AR3_REGNO 11 408 #define AR4_REGNO 12 409 #define AR5_REGNO 13 410 #define AR6_REGNO 14 411 #define AR7_REGNO 15 412 413 /* Data page register. */ 414 415 #define DP_REGNO 16 416 417 /* Index registers. */ 418 419 #define IR0_REGNO 17 420 #define IR1_REGNO 18 421 422 /* Block size register. */ 423 424 #define BK_REGNO 19 425 426 /* Stack pointer. */ 427 428 #define SP_REGNO 20 429 430 /* Status register. */ 431 432 #define ST_REGNO 21 433 434 /* Misc. interrupt registers. */ 435 436 #define DIE_REGNO 22 /* C4x only. */ 437 #define IE_REGNO 22 /* C3x only. */ 438 #define IIE_REGNO 23 /* C4x only. */ 439 #define IF_REGNO 23 /* C3x only. */ 440 #define IIF_REGNO 24 /* C4x only. */ 441 #define IOF_REGNO 24 /* C3x only. */ 442 443 /* Repeat block registers. */ 444 445 #define RS_REGNO 25 446 #define RE_REGNO 26 447 #define RC_REGNO 27 448 449 /* Additional extended-precision registers. */ 450 451 #define R8_REGNO 28 /* C4x only. */ 452 #define R9_REGNO 29 /* C4x only. */ 453 #define R10_REGNO 30 /* C4x only. */ 454 #define R11_REGNO 31 /* C4x only. */ 455 456 #define FIRST_PSEUDO_REGISTER 32 457 458 /* Extended precision registers (low set). */ 459 460 #define IS_R0R1_REGNO(r) \ 461 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO)) 462 #define IS_R2R3_REGNO(r) \ 463 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO)) 464 #define IS_EXT_LOW_REGNO(r) \ 465 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO)) 466 467 /* Extended precision registers (high set). */ 468 469 #define IS_EXT_HIGH_REGNO(r) \ 470 (! TARGET_C3X \ 471 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO))) 472 473 /* Address registers. */ 474 475 #define IS_AUX_REGNO(r) \ 476 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO)) 477 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r) 478 #define IS_DP_REGNO(r) ((r) == DP_REGNO) 479 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO)) 480 #define IS_SP_REGNO(r) ((r) == SP_REGNO) 481 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO) 482 483 /* Misc registers. */ 484 485 #define IS_ST_REGNO(r) ((r) == ST_REGNO) 486 #define IS_RC_REGNO(r) ((r) == RC_REGNO) 487 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO)) 488 489 /* Composite register sets. */ 490 491 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r)) 492 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r)) 493 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \ 494 || IS_REPEAT_REGNO(r) \ 495 || IS_SP_REGNO(r) \ 496 || IS_BK_REGNO(r)) 497 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r)) 498 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r)) 499 #define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \ 500 || ((r) == R8_REGNO)) 501 #define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO)) 502 503 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER) 504 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r)) 505 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r)) 506 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r)) 507 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r)) 508 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r)) 509 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r)) 510 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r)) 511 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \ 512 || IS_PSEUDO_REGNO(r)) 513 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r)) 514 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r)) 515 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r)) 516 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r)) 517 518 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op))) 519 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op))) 520 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op))) 521 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op))) 522 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op))) 523 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op))) 524 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op))) 525 526 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op))) 527 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op))) 528 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op))) 529 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op))) 530 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op))) 531 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op))) 532 533 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op))) 534 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op))) 535 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op))) 536 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op))) 537 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op))) 538 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op))) 539 540 /* 1 for registers that have pervasive standard uses 541 and are not available for the register allocator. */ 542 543 #define FIXED_REGISTERS \ 544 { \ 545 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \ 546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 547 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \ 548 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \ 549 } 550 551 /* 1 for registers not available across function calls. 552 These must include the FIXED_REGISTERS and also any 553 registers that can be used without being saved. 554 The latter must include the registers where values are returned 555 and the register where structure-value addresses are passed. 556 Aside from that, you can include as many other registers as you like. 557 558 Note that the extended precision registers are only saved in some 559 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes 560 get clobbered for a given regno. */ 561 562 #define CALL_USED_REGISTERS \ 563 { \ 564 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \ 565 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \ 566 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \ 567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \ 568 } 569 570 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 571 572 #define CONDITIONAL_REGISTER_USAGE \ 573 { \ 574 if (! TARGET_BK) \ 575 { \ 576 fixed_regs[BK_REGNO] = 1; \ 577 call_used_regs[BK_REGNO] = 1; \ 578 c4x_regclass_map[BK_REGNO] = NO_REGS; \ 579 } \ 580 if (TARGET_C3X) \ 581 { \ 582 int i; \ 583 \ 584 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \ 585 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \ 586 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \ 587 \ 588 for (i = R8_REGNO; i <= R11_REGNO; i++) \ 589 { \ 590 fixed_regs[i] = call_used_regs[i] = 1; \ 591 c4x_regclass_map[i] = NO_REGS; \ 592 } \ 593 } \ 594 if (TARGET_PRESERVE_FLOAT) \ 595 { \ 596 c4x_caller_save_map[R6_REGNO] = HFmode; \ 597 c4x_caller_save_map[R7_REGNO] = HFmode; \ 598 } \ 599 } 600 601 /* Order of Allocation of Registers. */ 602 603 /* List the order in which to allocate registers. Each register must be 604 listed once, even those in FIXED_REGISTERS. 605 606 First allocate registers that don't need preservation across calls, 607 except index and address registers. Then allocate data registers 608 that require preservation across calls (even though this invokes an 609 extra overhead of having to save/restore these registers). Next 610 allocate the address and index registers, since using these 611 registers for arithmetic can cause pipeline stalls. Finally 612 allocated the fixed registers which won't be allocated anyhow. */ 613 614 #define REG_ALLOC_ORDER \ 615 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \ 616 R9_REGNO, R10_REGNO, R11_REGNO, \ 617 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \ 618 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \ 619 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \ 620 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \ 621 IR0_REGNO, IR1_REGNO, \ 622 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO} 623 624 /* A C expression that is nonzero if hard register number REGNO2 can be 625 considered for use as a rename register for REGNO1 */ 626 627 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 628 c4x_hard_regno_rename_ok((REGNO1), (REGNO2)) 629 630 /* Determine which register classes are very likely used by spill registers. 631 local-alloc.c won't allocate pseudos that have these classes as their 632 preferred class unless they are "preferred or nothing". */ 633 634 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS) 635 636 /* CCmode is wrongly defined in machmode.def. It should have a size 637 of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single 638 extended precision register. Similarly, HCmode fits within two 639 extended precision registers. */ 640 641 #define HARD_REGNO_NREGS(REGNO, MODE) \ 642 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \ 643 ((MODE) == HFmode) ? 1 : \ 644 ((MODE) == HCmode) ? 2 : \ 645 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 646 647 648 /* A C expression that is nonzero if the hard register REGNO is preserved 649 across a call in mode MODE. This does not have to include the call used 650 registers. */ 651 652 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 653 ((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \ 654 || (IS_INT_CALL_SAVED_REGNO (REGNO) \ 655 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode))) 656 657 /* Specify the modes required to caller save a given hard regno. */ 658 659 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO]) 660 661 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE) 662 663 /* A C expression that is nonzero if it is desirable to choose 664 register allocation so as to avoid move instructions between a 665 value of mode MODE1 and a value of mode MODE2. 666 667 Value is 1 if it is a good idea to tie two pseudo registers 668 when one has mode MODE1 and one has mode MODE2. 669 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 670 for any hard reg, then this must be 0 for correct output. */ 671 672 #define MODES_TIEABLE_P(MODE1, MODE2) 0 673 674 675 /* Define the classes of registers for register constraints in the 676 machine description. Also define ranges of constants. 677 678 One of the classes must always be named ALL_REGS and include all hard regs. 679 If there is more than one class, another class must be named NO_REGS 680 and contain no registers. 681 682 The name GENERAL_REGS must be the name of a class (or an alias for 683 another name such as ALL_REGS). This is the class of registers 684 that is allowed by "g" or "r" in a register constraint. 685 Also, registers outside this class are allocated only when 686 instructions express preferences for them. 687 688 The classes must be numbered in nondecreasing order; that is, 689 a larger-numbered class must never be contained completely 690 in a smaller-numbered class. 691 692 For any two classes, it is very desirable that there be another 693 class that represents their union. */ 694 695 enum reg_class 696 { 697 NO_REGS, 698 R0R1_REGS, /* 't'. */ 699 R2R3_REGS, /* 'u'. */ 700 EXT_LOW_REGS, /* 'q'. */ 701 EXT_REGS, /* 'f'. */ 702 ADDR_REGS, /* 'a'. */ 703 INDEX_REGS, /* 'x'. */ 704 BK_REG, /* 'k'. */ 705 SP_REG, /* 'b'. */ 706 RC_REG, /* 'v'. */ 707 COUNTER_REGS, /* */ 708 INT_REGS, /* 'c'. */ 709 GENERAL_REGS, /* 'r'. */ 710 DP_REG, /* 'z'. */ 711 ST_REG, /* 'y'. */ 712 ALL_REGS, 713 LIM_REG_CLASSES 714 }; 715 716 #define N_REG_CLASSES (int) LIM_REG_CLASSES 717 718 #define REG_CLASS_NAMES \ 719 { \ 720 "NO_REGS", \ 721 "R0R1_REGS", \ 722 "R2R3_REGS", \ 723 "EXT_LOW_REGS", \ 724 "EXT_REGS", \ 725 "ADDR_REGS", \ 726 "INDEX_REGS", \ 727 "BK_REG", \ 728 "SP_REG", \ 729 "RC_REG", \ 730 "COUNTER_REGS", \ 731 "INT_REGS", \ 732 "GENERAL_REGS", \ 733 "DP_REG", \ 734 "ST_REG", \ 735 "ALL_REGS" \ 736 } 737 738 /* Define which registers fit in which classes. 739 This is an initializer for a vector of HARD_REG_SET 740 of length N_REG_CLASSES. RC is not included in GENERAL_REGS 741 since the register allocator will often choose a general register 742 in preference to RC for the decrement_and_branch_on_count pattern. */ 743 744 #define REG_CLASS_CONTENTS \ 745 { \ 746 {0x00000000}, /* No registers. */ \ 747 {0x00000003}, /* 't' R0-R1 . */ \ 748 {0x0000000c}, /* 'u' R2-R3 . */ \ 749 {0x000000ff}, /* 'q' R0-R7 . */ \ 750 {0xf00000ff}, /* 'f' R0-R11 */ \ 751 {0x0000ff00}, /* 'a' AR0-AR7. */ \ 752 {0x00060000}, /* 'x' IR0-IR1. */ \ 753 {0x00080000}, /* 'k' BK. */ \ 754 {0x00100000}, /* 'b' SP. */ \ 755 {0x08000000}, /* 'v' RC. */ \ 756 {0x0800ff00}, /* RC,AR0-AR7. */ \ 757 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \ 758 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\ 759 {0x00010000}, /* 'z' DP. */ \ 760 {0x00200000}, /* 'y' ST. */ \ 761 {0xffffffff}, /* All registers. */ \ 762 } 763 764 /* The same information, inverted: 765 Return the class number of the smallest class containing 766 reg number REGNO. This could be a conditional expression 767 or could index an array. */ 768 769 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO]) 770 771 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers 772 explicitly used in the rtl is kept as short as possible. 773 774 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY 775 is defined since the MPY|ADD insns require the classes R0R1_REGS and 776 R2R3_REGS which are used by the function return registers (R0,R1) and 777 the register arguments (R2,R3), respectively. I'm reluctant to define 778 this macro since it stomps on many potential optimisations. Ideally 779 it should have a register class argument so that not all the register 780 classes gets penalised for the sake of a naughty few... For long 781 double arithmetic we need two additional registers that we can use as 782 spill registers. */ 783 784 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY) 785 786 #define BASE_REG_CLASS ADDR_REGS 787 #define INDEX_REG_CLASS INDEX_REGS 788 789 /* 790 Register constraints for the C4x 791 792 a - address reg (ar0-ar7) 793 b - stack reg (sp) 794 c - other gp int-only reg 795 d - data/int reg (equiv. to f) 796 f - data/float reg 797 h - data/long double reg (equiv. to f) 798 k - block count (bk) 799 q - r0-r7 800 t - r0-r1 801 u - r2-r3 802 v - repeat count (rc) 803 x - index register (ir0-ir1) 804 y - status register (st) 805 z - dp reg (dp) 806 807 Memory/constant constraints for the C4x 808 809 G - short float 16-bit 810 I - signed 16-bit constant (sign extended) 811 J - signed 8-bit constant (sign extended) (C4x only) 812 K - signed 5-bit constant (sign extended) (C4x only for stik) 813 L - unsigned 16-bit constant 814 M - unsigned 8-bit constant (C4x only) 815 N - ones complement of unsigned 16-bit constant 816 Q - indirect arx + 9-bit signed displacement 817 (a *-arx(n) or *+arx(n) is used to account for the sign bit) 818 R - indirect arx + 5-bit unsigned displacement (C4x only) 819 S - indirect arx + 0, 1, or irn displacement 820 T - direct symbol ref 821 > - indirect with autoincrement 822 < - indirect with autodecrement 823 } - indirect with post-modify 824 { - indirect with pre-modify 825 */ 826 827 #define REG_CLASS_FROM_LETTER(CC) \ 828 ( ((CC) == 'a') ? ADDR_REGS \ 829 : ((CC) == 'b') ? SP_REG \ 830 : ((CC) == 'c') ? INT_REGS \ 831 : ((CC) == 'd') ? EXT_REGS \ 832 : ((CC) == 'f') ? EXT_REGS \ 833 : ((CC) == 'h') ? EXT_REGS \ 834 : ((CC) == 'k') ? BK_REG \ 835 : ((CC) == 'q') ? EXT_LOW_REGS \ 836 : ((CC) == 't') ? R0R1_REGS \ 837 : ((CC) == 'u') ? R2R3_REGS \ 838 : ((CC) == 'v') ? RC_REG \ 839 : ((CC) == 'x') ? INDEX_REGS \ 840 : ((CC) == 'y') ? ST_REG \ 841 : ((CC) == 'z') ? DP_REG \ 842 : NO_REGS ) 843 844 /* These assume that REGNO is a hard or pseudo reg number. 845 They give nonzero only if REGNO is a hard reg of the suitable class 846 or a pseudo reg currently allocated to a suitable hard reg. 847 Since they use reg_renumber, they are safe only once reg_renumber 848 has been allocated, which happens in local-alloc.c. */ 849 850 #define REGNO_OK_FOR_BASE_P(REGNO) \ 851 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO])) 852 853 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 854 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO])) 855 856 /* If we have to generate framepointer + constant prefer an ADDR_REGS 857 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */ 858 859 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 860 (GET_CODE (X) == PLUS \ 861 && GET_MODE (X) == Pmode \ 862 && GET_CODE (XEXP ((X), 0)) == REG \ 863 && GET_MODE (XEXP ((X), 0)) == Pmode \ 864 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \ 865 && GET_CODE (XEXP ((X), 1)) == CONST_INT \ 866 ? ADDR_REGS : (CLASS)) 867 868 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS) 869 870 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0 871 872 #define CLASS_MAX_NREGS(CLASS, MODE) \ 873 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \ 874 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 875 876 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */ 877 878 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */ 879 880 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */ 881 882 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */ 883 884 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */ 885 886 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */ 887 888 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */ 889 890 #define IS_HIGH_CONST(VAL) \ 891 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */ 892 893 894 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */ 895 896 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */ 897 898 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \ 899 && IS_DISP1_CONST (VAL + 1)) 900 901 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \ 902 && IS_DISP8_CONST (VAL + 1)) 903 904 #define CONST_OK_FOR_LETTER_P(VAL, C) \ 905 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \ 906 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \ 907 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \ 908 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \ 909 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \ 910 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \ 911 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \ 912 : 0 ) 913 914 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \ 915 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \ 916 : ((C) == 'H') ? (c4x_H_constant (OP)) \ 917 : 0 ) 918 919 #define EXTRA_CONSTRAINT(OP, C) \ 920 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \ 921 : ((C) == 'R') ? (c4x_R_constraint (OP)) \ 922 : ((C) == 'S') ? (c4x_S_constraint (OP)) \ 923 : ((C) == 'T') ? (c4x_T_constraint (OP)) \ 924 : ((C) == 'U') ? (c4x_U_constraint (OP)) \ 925 : 0 ) 926 927 #define SMALL_CONST(VAL, insn) \ 928 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \ 929 ? IS_INT16_CONST (VAL) \ 930 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \ 931 ? IS_NOT_UINT16_CONST (VAL) \ 932 : ( (get_attr_data (insn) == DATA_HIGH_16) \ 933 ? IS_HIGH_CONST (VAL) \ 934 : IS_UINT16_CONST (VAL) \ 935 ) \ 936 ) \ 937 ) 938 939 /* 940 I. Routine calling with arguments in registers 941 ---------------------------------------------- 942 943 The TI C3x compiler has a rather unusual register passing algorithm. 944 Data is passed in the following registers (in order): 945 946 AR2, R2, R3, RC, RS, RE 947 948 However, the first and second floating point values are always in R2 949 and R3 (and all other floats are on the stack). Structs are always 950 passed on the stack. If the last argument is an ellipsis, the 951 previous argument is passed on the stack so that its address can be 952 taken for the stdargs macros. 953 954 Because of this, we have to pre-scan the list of arguments to figure 955 out what goes where in the list. 956 957 II. Routine calling with arguments on stack 958 ------------------------------------------- 959 960 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local 961 variables loc0, loc1, and loc2. After the function prologue has 962 been executed, the stack frame will look like: 963 964 [stack grows towards increasing addresses] 965 I-------------I 966 5 I saved reg1 I <= SP points here 967 I-------------I 968 4 I saved reg0 I 969 I-------------I 970 3 I loc2 I 971 I-------------I 972 2 I loc1 I 973 I-------------I 974 1 I loc0 I 975 I-------------I 976 0 I old FP I <= FP (AR3) points here 977 I-------------I 978 -1 I return PC I 979 I-------------I 980 -2 I arg0 I 981 I-------------I 982 -3 I arg1 I 983 I-------------I 984 -4 I arg2 I 985 I-------------I 986 987 All local variables (locn) are accessible by means of +FP(n+1) 988 addressing, where n is the local variable number. 989 990 All stack arguments (argn) are accessible by means of -FP(n-2). 991 992 The stack pointer (SP) points to the last register saved in the 993 prologue (regn). 994 995 Note that a push instruction performs a preincrement of the stack 996 pointer. (STACK_PUSH_CODE == PRE_INC) 997 998 III. Registers used in function calling convention 999 -------------------------------------------------- 1000 1001 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits) 1002 R6...R7 (only by PUSHF, i.e. upper 32 bits) 1003 AR3...AR7 1004 1005 (Because of this model, we only assign FP values in R6, R7 and 1006 only assign integer values in R4, R5.) 1007 1008 These registers are saved at each function entry and restored at 1009 the exit. Also it is expected any of these not affected by any 1010 call to user-defined (not service) functions. 1011 1012 Not preserved across calls: R0...R3 1013 R4...R5 (upper 8 bits) 1014 R6...R7 (lower 8 bits) 1015 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC 1016 1017 These registers are used arbitrary in a function without being preserved. 1018 It is also expected that any of these can be clobbered by any call. 1019 1020 Not used by GCC (except for in user "asm" statements): 1021 IE (DIE), IF (IIE), IOF (IIF) 1022 1023 These registers are never used by GCC for any data, but can be used 1024 with "asm" statements. */ 1025 1026 #define C4X_ARG0 -2 1027 #define C4X_LOC0 1 1028 1029 /* Basic Stack Layout. */ 1030 1031 /* The stack grows upward, stack frame grows upward, and args grow 1032 downward. */ 1033 1034 #define STARTING_FRAME_OFFSET C4X_LOC0 1035 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1) 1036 #define ARGS_GROW_DOWNWARD 1037 #define STACK_POINTER_OFFSET 1 1038 1039 /* Define this if pushing a word on the stack 1040 makes the stack pointer a smaller address. */ 1041 1042 /* #define STACK_GROWS_DOWNWARD. */ 1043 /* Like the dsp16xx, i370, i960, and we32k ports. */ 1044 1045 /* Define this if the nominal address of the stack frame 1046 is at the high-address end of the local variables; 1047 that is, each additional local variable allocated 1048 goes at a more negative offset in the frame. */ 1049 1050 /* #define FRAME_GROWS_DOWNWARD. */ 1051 1052 1053 /* Registers That Address the Stack Frame. */ 1054 1055 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */ 1056 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */ 1057 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */ 1058 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */ 1059 1060 /* Eliminating Frame Pointer and Arg Pointer. */ 1061 1062 #define FRAME_POINTER_REQUIRED 0 1063 1064 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ 1065 { \ 1066 int regno; \ 1067 int offset = 0; \ 1068 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ 1069 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 1070 offset += TARGET_PRESERVE_FLOAT \ 1071 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \ 1072 (DEPTH) = -(offset + get_frame_size ()); \ 1073 } 1074 1075 /* This is a hack... We need to specify a register. */ 1076 #define ELIMINABLE_REGS \ 1077 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }} 1078 1079 #define CAN_ELIMINATE(FROM, TO) \ 1080 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 1081 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM))) 1082 1083 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1084 { \ 1085 int regno; \ 1086 int offset = 0; \ 1087 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ 1088 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 1089 offset += TARGET_PRESERVE_FLOAT \ 1090 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \ 1091 (OFFSET) = -(offset + get_frame_size ()); \ 1092 } 1093 1094 1095 /* Passing Function Arguments on the Stack. */ 1096 1097 #define PUSH_ARGS 1 1098 #define PUSH_ROUNDING(BYTES) (BYTES) 1099 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 1100 1101 /* The following structure is used by calls.c, function.c, c4x.c. */ 1102 1103 typedef struct c4x_args 1104 { 1105 int floats; 1106 int ints; 1107 int maxfloats; 1108 int maxints; 1109 int init; 1110 int var; 1111 int prototype; 1112 int args; 1113 } 1114 CUMULATIVE_ARGS; 1115 1116 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ 1117 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 1118 1119 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1120 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED)) 1121 1122 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1123 (c4x_function_arg(&CUM, MODE, TYPE, NAMED)) 1124 1125 /* Define the profitability of saving registers around calls. 1126 We disable caller save to avoid a bug in flow.c (this also affects 1127 other targets such as m68k). Since we must use stf/sti, 1128 the profitability is marginal anyway. */ 1129 1130 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 1131 1132 /* Never pass data by reference. */ 1133 1134 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0 1135 1136 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1137 1138 /* 1 if N is a possible register number for function argument passing. */ 1139 1140 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1141 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \ 1142 || ((REGNO) == R2_REGNO) /* R2. */ \ 1143 || ((REGNO) == R3_REGNO) /* R3. */ \ 1144 || ((REGNO) == RC_REGNO) /* RC. */ \ 1145 || ((REGNO) == RS_REGNO) /* RS. */ \ 1146 || ((REGNO) == RE_REGNO)) /* RE. */ \ 1147 ? 1 \ 1148 : 0) 1149 1150 /* How Scalar Function Values Are Returned. */ 1151 1152 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1153 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */ 1154 1155 #define LIBCALL_VALUE(MODE) \ 1156 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */ 1157 1158 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO) 1159 1160 /* How Large Values Are Returned. */ 1161 1162 #define DEFAULT_PCC_STRUCT_RETURN 0 1163 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */ 1164 1165 /* Varargs handling. */ 1166 1167 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1168 c4x_va_arg (valist, type) 1169 1170 /* Generating Code for Profiling. */ 1171 1172 /* Note that the generated assembly uses the ^ operator to load the 16 1173 MSBs of the address. This is not supported by the TI assembler. 1174 The FUNCTION profiler needs a function mcount which gets passed 1175 a pointer to the LABELNO. */ 1176 1177 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1178 if (! TARGET_C3X) \ 1179 { \ 1180 fprintf (FILE, "\tpush\tar2\n"); \ 1181 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \ 1182 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \ 1183 fprintf (FILE, "\tcall\tmcount\n"); \ 1184 fprintf (FILE, "\tpop\tar2\n"); \ 1185 } \ 1186 else \ 1187 { \ 1188 fprintf (FILE, "\tpush\tar2\n"); \ 1189 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \ 1190 fprintf (FILE, "\tlsh\t16,ar2\n"); \ 1191 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \ 1192 fprintf (FILE, "\tcall\tmcount\n"); \ 1193 fprintf (FILE, "\tpop\tar2\n"); \ 1194 } 1195 1196 /* Implicit Calls to Library Routines. */ 1197 1198 #define MULQI3_LIBCALL "__mulqi3" 1199 #define DIVQI3_LIBCALL "__divqi3" 1200 #define UDIVQI3_LIBCALL "__udivqi3" 1201 #define MODQI3_LIBCALL "__modqi3" 1202 #define UMODQI3_LIBCALL "__umodqi3" 1203 1204 #define DIVQF3_LIBCALL "__divqf3" 1205 1206 #define MULHF3_LIBCALL "__mulhf3" 1207 #define DIVHF3_LIBCALL "__divhf3" 1208 1209 #define MULHI3_LIBCALL "__mulhi3" 1210 #define SMULHI3_LIBCALL "__smulhi3_high" 1211 #define UMULHI3_LIBCALL "__umulhi3_high" 1212 #define DIVHI3_LIBCALL "__divhi3" 1213 #define UDIVHI3_LIBCALL "__udivhi3" 1214 #define MODHI3_LIBCALL "__modhi3" 1215 #define UMODHI3_LIBCALL "__umodhi3" 1216 1217 #define FLOATHIQF2_LIBCALL "__floathiqf2" 1218 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2" 1219 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2" 1220 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2" 1221 1222 #define FLOATHIHF2_LIBCALL "__floathihf2" 1223 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2" 1224 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2" 1225 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2" 1226 1227 #define FFS_LIBCALL "__ffs" 1228 1229 #define INIT_TARGET_OPTABS \ 1230 do { \ 1231 smul_optab->handlers[(int) QImode].libfunc \ 1232 = init_one_libfunc (MULQI3_LIBCALL); \ 1233 sdiv_optab->handlers[(int) QImode].libfunc \ 1234 = init_one_libfunc (DIVQI3_LIBCALL); \ 1235 udiv_optab->handlers[(int) QImode].libfunc \ 1236 = init_one_libfunc (UDIVQI3_LIBCALL); \ 1237 smod_optab->handlers[(int) QImode].libfunc \ 1238 = init_one_libfunc (MODQI3_LIBCALL); \ 1239 umod_optab->handlers[(int) QImode].libfunc \ 1240 = init_one_libfunc (UMODQI3_LIBCALL); \ 1241 sdiv_optab->handlers[(int) QFmode].libfunc \ 1242 = init_one_libfunc (DIVQF3_LIBCALL); \ 1243 smul_optab->handlers[(int) HFmode].libfunc \ 1244 = init_one_libfunc (MULHF3_LIBCALL); \ 1245 sdiv_optab->handlers[(int) HFmode].libfunc \ 1246 = init_one_libfunc (DIVHF3_LIBCALL); \ 1247 smul_optab->handlers[(int) HImode].libfunc \ 1248 = init_one_libfunc (MULHI3_LIBCALL); \ 1249 sdiv_optab->handlers[(int) HImode].libfunc \ 1250 = init_one_libfunc (DIVHI3_LIBCALL); \ 1251 udiv_optab->handlers[(int) HImode].libfunc \ 1252 = init_one_libfunc (UDIVHI3_LIBCALL); \ 1253 smod_optab->handlers[(int) HImode].libfunc \ 1254 = init_one_libfunc (MODHI3_LIBCALL); \ 1255 umod_optab->handlers[(int) HImode].libfunc \ 1256 = init_one_libfunc (UMODHI3_LIBCALL); \ 1257 ffs_optab->handlers[(int) QImode].libfunc \ 1258 = init_one_libfunc (FFS_LIBCALL); \ 1259 smulhi3_libfunc \ 1260 = init_one_libfunc(SMULHI3_LIBCALL); \ 1261 umulhi3_libfunc \ 1262 = init_one_libfunc(UMULHI3_LIBCALL); \ 1263 fix_truncqfhi2_libfunc \ 1264 = init_one_libfunc(FIX_TRUNCQFHI2_LIBCALL); \ 1265 fixuns_truncqfhi2_libfunc \ 1266 = init_one_libfunc(FIXUNS_TRUNCQFHI2_LIBCALL); \ 1267 fix_trunchfhi2_libfunc \ 1268 = init_one_libfunc(FIX_TRUNCHFHI2_LIBCALL); \ 1269 fixuns_trunchfhi2_libfunc \ 1270 = init_one_libfunc(FIXUNS_TRUNCHFHI2_LIBCALL); \ 1271 floathiqf2_libfunc \ 1272 = init_one_libfunc(FLOATHIQF2_LIBCALL); \ 1273 floatunshiqf2_libfunc \ 1274 = init_one_libfunc(FLOATUNSHIQF2_LIBCALL); \ 1275 floathihf2_libfunc \ 1276 = init_one_libfunc(FLOATHIHF2_LIBCALL); \ 1277 floatunshihf2_libfunc \ 1278 = init_one_libfunc(FLOATUNSHIHF2_LIBCALL); \ 1279 } while (0) 1280 1281 #define TARGET_MEM_FUNCTIONS 1282 1283 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG 1284 or MULT. 1285 CCmode should be used when no special processing is needed. */ 1286 #define SELECT_CC_MODE(OP,X,Y) \ 1287 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ 1288 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \ 1289 || GET_MODE (X) == ABS \ 1290 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \ 1291 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \ 1292 || GET_MODE (Y) == ABS) \ 1293 ? CC_NOOVmode : CCmode) 1294 1295 /* Addressing Modes. */ 1296 1297 #define HAVE_POST_INCREMENT 1 1298 #define HAVE_PRE_INCREMENT 1 1299 #define HAVE_POST_DECREMENT 1 1300 #define HAVE_PRE_DECREMENT 1 1301 #define HAVE_PRE_MODIFY_REG 1 1302 #define HAVE_POST_MODIFY_REG 1 1303 #define HAVE_PRE_MODIFY_DISP 1 1304 #define HAVE_POST_MODIFY_DISP 1 1305 1306 /* The number of insns that can be packed into a single opcode. */ 1307 #define PACK_INSNS 2 1308 1309 /* Recognize any constant value that is a valid address. 1310 We could allow arbitrary constant addresses in the large memory 1311 model but for the small memory model we can only accept addresses 1312 within the data page. I suppose we could also allow 1313 CONST PLUS SYMBOL_REF. */ 1314 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF) 1315 1316 /* Maximum number of registers that can appear in a valid memory 1317 address. */ 1318 #define MAX_REGS_PER_ADDRESS 2 1319 1320 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1321 and check its validity for a certain class. 1322 We have two alternate definitions for each of them. 1323 The usual definition accepts all pseudo regs; the other rejects 1324 them unless they have been allocated suitable hard regs. 1325 The symbol REG_OK_STRICT causes the latter definition to be used. 1326 1327 Most source files want to accept pseudo regs in the hope that 1328 they will get allocated to the class that the insn wants them to be in. 1329 Source files for reload pass need to be strict. 1330 After reload, it makes no difference, since pseudo regs have 1331 been eliminated by then. */ 1332 1333 #ifndef REG_OK_STRICT 1334 1335 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */ 1336 1337 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X) 1338 1339 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */ 1340 1341 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X) 1342 1343 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1344 { \ 1345 if (c4x_check_legit_addr (MODE, X, 0)) \ 1346 goto ADDR; \ 1347 } 1348 1349 #else 1350 1351 /* Nonzero if X is a hard reg that can be used as an index. */ 1352 1353 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1354 1355 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1356 1357 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1358 1359 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1360 { \ 1361 if (c4x_check_legit_addr (MODE, X, 1)) \ 1362 goto ADDR; \ 1363 } 1364 1365 #endif 1366 1367 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1368 { \ 1369 rtx new; \ 1370 new = c4x_legitimize_address (X, MODE); \ 1371 if (new != NULL_RTX) \ 1372 { \ 1373 (X) = new; \ 1374 goto WIN; \ 1375 } \ 1376 } 1377 1378 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1379 { \ 1380 if (MODE != HImode \ 1381 && MODE != HFmode \ 1382 && GET_MODE (X) != HImode \ 1383 && GET_MODE (X) != HFmode \ 1384 && (GET_CODE (X) == CONST \ 1385 || GET_CODE (X) == SYMBOL_REF \ 1386 || GET_CODE (X) == LABEL_REF)) \ 1387 { \ 1388 if (! TARGET_SMALL) \ 1389 { \ 1390 int i; \ 1391 X = gen_rtx_LO_SUM (GET_MODE (X), \ 1392 gen_rtx_HIGH (GET_MODE (X), X), X); \ 1393 i = push_reload (XEXP (X, 0), NULL_RTX, \ 1394 &XEXP (X, 0), NULL, \ 1395 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \ 1396 OPNUM, TYPE); \ 1397 /* The only valid reg is DP. This is a fixed reg and will \ 1398 normally not be used so force it. */ \ 1399 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \ 1400 rld[i].nocombine = 1; \ 1401 } \ 1402 goto WIN; \ 1403 } \ 1404 else if (MODE != HImode \ 1405 && MODE != HFmode \ 1406 && GET_MODE (X) != HImode \ 1407 && GET_MODE (X) != HFmode \ 1408 && GET_CODE (X) == LO_SUM \ 1409 && GET_CODE (XEXP (X,0)) == HIGH \ 1410 && (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \ 1411 || GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \ 1412 || GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \ 1413 { \ 1414 if (! TARGET_SMALL) \ 1415 { \ 1416 int i = push_reload (XEXP (X, 0), NULL_RTX, \ 1417 &XEXP (X, 0), NULL, \ 1418 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \ 1419 OPNUM, TYPE); \ 1420 /* The only valid reg is DP. This is a fixed reg and will \ 1421 normally not be used so force it. */ \ 1422 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \ 1423 rld[i].nocombine = 1; \ 1424 } \ 1425 goto WIN; \ 1426 } \ 1427 } 1428 1429 /* No mode-dependent addresses on the C4x are autoincrements. */ 1430 1431 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1432 if (GET_CODE (ADDR) == PRE_DEC \ 1433 || GET_CODE (ADDR) == POST_DEC \ 1434 || GET_CODE (ADDR) == PRE_INC \ 1435 || GET_CODE (ADDR) == POST_INC \ 1436 || GET_CODE (ADDR) == POST_MODIFY \ 1437 || GET_CODE (ADDR) == PRE_MODIFY) \ 1438 goto LABEL 1439 1440 1441 /* Nonzero if the constant value X is a legitimate general operand. 1442 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1443 1444 The C4x can only load 16-bit immediate values, so we only allow a 1445 restricted subset of CONST_INT and CONST_DOUBLE. Disallow 1446 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory 1447 model) so that the symbols will be forced into the constant pool. 1448 On second thoughts, let's do this with the move expanders since 1449 the alias analysis has trouble if we force constant addresses 1450 into memory. 1451 */ 1452 1453 #define LEGITIMATE_CONSTANT_P(X) \ 1454 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \ 1455 || (GET_CODE (X) == CONST_INT) \ 1456 || (GET_CODE (X) == SYMBOL_REF) \ 1457 || (GET_CODE (X) == LABEL_REF) \ 1458 || (GET_CODE (X) == CONST) \ 1459 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \ 1460 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X)) 1461 1462 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X)) 1463 1464 /* Descripting Relative Cost of Operations. */ 1465 1466 /* Provide the costs of a rtl expression. This is in the body of a 1467 switch on CODE. 1468 1469 Note that we return, rather than break so that rtx_cost doesn't 1470 include CONST_COSTS otherwise expand_mult will think that it is 1471 cheaper to synthesize a multiply rather than to use a multiply 1472 instruction. I think this is because the algorithm synth_mult 1473 doesn't take into account the loading of the operands, whereas the 1474 calculation of mult_cost does. 1475 */ 1476 1477 1478 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \ 1479 case PLUS: \ 1480 case MINUS: \ 1481 case AND: \ 1482 case IOR: \ 1483 case XOR: \ 1484 case ASHIFT: \ 1485 case ASHIFTRT: \ 1486 case LSHIFTRT: \ 1487 return COSTS_N_INSNS (1); \ 1488 case MULT: \ 1489 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \ 1490 || TARGET_MPYI ? 1 : 14); \ 1491 case DIV: \ 1492 case UDIV: \ 1493 case MOD: \ 1494 case UMOD: \ 1495 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \ 1496 ? 15 : 50); 1497 1498 /* Compute the cost of computing a constant rtl expression RTX 1499 whose rtx-code is CODE. The body of this macro is a portion 1500 of a switch statement. If the code is computed here, 1501 return it with a return statement. Otherwise, break from the switch. 1502 1503 An insn is assumed to cost 4 units. 1504 COSTS_N_INSNS (N) is defined as (N) * 4 - 2. 1505 1506 Some small integers are effectively free for the C40. We should 1507 also consider if we are using the small memory model. With 1508 the big memory model we require an extra insn for a constant 1509 loaded from memory. 1510 1511 This is used by expand_binop to decide whether to force a constant 1512 into a register. If the cost is greater than 2 and the constant 1513 is used within a short loop, it gets forced into a register. 1514 Ideally, there should be some weighting as to how mnay times it is used 1515 within the loop. */ 1516 1517 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT) 1518 1519 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \ 1520 || (C) == IOR || (C) == XOR) 1521 1522 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE) 1523 1524 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 1525 case CONST_INT: \ 1526 if (c4x_J_constant (RTX)) \ 1527 return 0; \ 1528 if (! TARGET_C3X \ 1529 && OUTER_CODE == AND \ 1530 && GET_CODE (RTX) == CONST_INT \ 1531 && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \ 1532 return 0; \ 1533 if (! TARGET_C3X \ 1534 && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \ 1535 && GET_CODE (RTX) == CONST_INT \ 1536 && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \ 1537 return 0; \ 1538 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \ 1539 return 3; \ 1540 if (LOGICAL_CODE_P (OUTER_CODE) \ 1541 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \ 1542 return 2; \ 1543 case CONST: \ 1544 case LABEL_REF: \ 1545 case SYMBOL_REF: \ 1546 return 4; \ 1547 case CONST_DOUBLE: \ 1548 if (c4x_H_constant (RTX)) \ 1549 return 2; \ 1550 if (GET_MODE (RTX) == QFmode) \ 1551 return 4; \ 1552 else \ 1553 return 8; 1554 1555 /* Compute the cost of an address. This is meant to approximate the size 1556 and/or execution delay of an insn using that address. If the cost is 1557 approximated by the RTL complexity, including CONST_COSTS above, as 1558 is usually the case for CISC machines, this macro should not be defined. 1559 For aggressively RISCy machines, only one insn format is allowed, so 1560 this macro should be a constant. The value of this macro only matters 1561 for valid addresses. We handle the most common address without 1562 a call to c4x_address_cost. */ 1563 1564 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR)) 1565 1566 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 1567 if (REG_P (OP1) && ! REG_P (OP0)) \ 1568 { \ 1569 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \ 1570 CODE = swap_condition (CODE); \ 1571 } 1572 1573 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS)) 1574 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS)) 1575 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS)) 1576 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \ 1577 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG) 1578 1579 /* Compute extra cost of moving data between one register class 1580 and another. */ 1581 1582 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2 1583 1584 /* Memory move cost is same as fast register move. Maybe this should 1585 be bumped up?. */ 1586 1587 #define MEMORY_MOVE_COST(M,C,I) 4 1588 1589 /* Branches are kind of expensive (even with delayed branching) so 1590 make their cost higher. */ 1591 1592 #define BRANCH_COST 8 1593 1594 #define WORD_REGISTER_OPERATIONS 1595 1596 /* Dividing the Output into Sections. */ 1597 1598 #define TEXT_SECTION_ASM_OP "\t.text" 1599 1600 #define DATA_SECTION_ASM_OP "\t.data" 1601 1602 #define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\"" 1603 1604 /* Do not use .init section so __main will be called on startup. This will 1605 call __do_global_ctors and prepare for __do_global_dtors on exit. */ 1606 1607 #if 0 1608 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\"" 1609 #endif 1610 1611 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\"" 1612 1613 #undef EXTRA_SECTIONS 1614 #define EXTRA_SECTIONS in_init, in_fini 1615 1616 #undef EXTRA_SECTION_FUNCTIONS 1617 #define EXTRA_SECTION_FUNCTIONS \ 1618 INIT_SECTION_FUNCTION \ 1619 FINI_SECTION_FUNCTION 1620 1621 #define INIT_SECTION_FUNCTION \ 1622 extern void init_section PARAMS ((void)); \ 1623 void \ 1624 init_section () \ 1625 { \ 1626 if (in_section != in_init) \ 1627 { \ 1628 fprintf (asm_out_file, ";\t.init\n"); \ 1629 in_section = in_init; \ 1630 } \ 1631 } 1632 1633 #define FINI_SECTION_FUNCTION \ 1634 void \ 1635 fini_section () \ 1636 { \ 1637 if (in_section != in_fini) \ 1638 { \ 1639 fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \ 1640 in_section = in_fini; \ 1641 } \ 1642 } 1643 1644 #define ASM_STABS_OP "\t.stabs\t" 1645 1646 /* Switch into a generic section. */ 1647 #define TARGET_ASM_NAMED_SECTION c4x_asm_named_section 1648 1649 /* The TI assembler wants to have hex numbers this way. */ 1650 1651 #undef HOST_WIDE_INT_PRINT_HEX 1652 #ifndef HOST_WIDE_INT_PRINT_HEX 1653 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT 1654 # define HOST_WIDE_INT_PRINT_HEX "0%xh" 1655 # else 1656 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG 1657 # define HOST_WIDE_INT_PRINT_HEX "0%lxh" 1658 # else 1659 # define HOST_WIDE_INT_PRINT_HEX "0%llxh" 1660 # endif 1661 # endif 1662 #endif /* ! HOST_WIDE_INT_PRINT_HEX */ 1663 1664 /* Overall Framework of an Assembler File. */ 1665 /* We need to have a data section we can identify so that we can set 1666 the DP register back to a data pointer in the small memory model. 1667 This is only required for ISRs if we are paranoid that someone 1668 may have quietly changed this register on the sly. */ 1669 1670 #define ASM_FILE_START(FILE) \ 1671 { \ 1672 int dspversion = 0; \ 1673 if (TARGET_C30) dspversion = 30; \ 1674 if (TARGET_C31) dspversion = 31; \ 1675 if (TARGET_C32) dspversion = 32; \ 1676 if (TARGET_C33) dspversion = 33; \ 1677 if (TARGET_C40) dspversion = 40; \ 1678 if (TARGET_C44) dspversion = 44; \ 1679 fprintf (FILE, "\t.version\t%d\n", dspversion); \ 1680 fprintf (FILE, "\t.file\t"); \ 1681 if (TARGET_TI) \ 1682 { \ 1683 const char *p; \ 1684 const char *after_dir = main_input_filename; \ 1685 for (p = main_input_filename; *p; p++) \ 1686 if (*p == '/') \ 1687 after_dir = p + 1; \ 1688 output_quoted_string (FILE, after_dir); \ 1689 } \ 1690 else \ 1691 output_quoted_string (FILE, main_input_filename); \ 1692 fputs ("\n\t.data\ndata_sec:\n", FILE); \ 1693 } 1694 1695 #define ASM_COMMENT_START ";" 1696 1697 #define ASM_APP_ON "" 1698 #define ASM_APP_OFF "" 1699 1700 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN) 1701 1702 /* Output and Generation of Labels. */ 1703 1704 #define NO_DOT_IN_LABEL /* Only required for TI format. */ 1705 1706 /* Globalizing directive for a label. */ 1707 #define GLOBAL_ASM_OP "\t.global\t" 1708 1709 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ 1710 c4x_external_ref (NAME) 1711 1712 /* A C statement to output on FILE an assembler pseudo-op to 1713 declare a library function named external. 1714 (Only needed to keep asm30 happy for ___divqf3 etc.) */ 1715 1716 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ 1717 c4x_external_ref (XSTR (FUN, 0)) 1718 1719 #define ASM_FILE_END(FILE) \ 1720 c4x_file_end (FILE) 1721 1722 /* The prefix to add to user-visible assembler symbols. */ 1723 1724 #define USER_LABEL_PREFIX "_" 1725 1726 /* This is how to output an internal numbered label where 1727 PREFIX is the class of label and NUM is the number within the class. */ 1728 1729 #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \ 1730 fprintf (FILE, "%s%d:\n", PREFIX, NUM) 1731 1732 /* This is how to store into the string LABEL 1733 the symbol_ref name of an internal numbered label where 1734 PREFIX is the class of label and NUM is the number within the class. 1735 This is suitable for output with `assemble_name'. */ 1736 1737 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \ 1738 sprintf (BUFFER, "*%s%d", PREFIX, NUM) 1739 1740 /* Store in OUTPUT a string (made with alloca) containing 1741 an assembler-name for a local static variable named NAME. 1742 LABELNO is an integer which is different for each call. */ 1743 1744 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1745 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1746 sprintf ((OUTPUT), "%s$%d", (NAME), (LABELNO))) 1747 1748 /* A C statement to output to the stdio stream STREAM assembler code which 1749 defines (equates) the symbol NAME to have the value VALUE. */ 1750 1751 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ 1752 do { \ 1753 assemble_name (STREAM, NAME); \ 1754 fprintf (STREAM, "\t.set\t%s\n", VALUE); \ 1755 } while (0) 1756 1757 /* Output of Dispatch Tables. */ 1758 1759 /* This is how to output an element of a case-vector that is absolute. */ 1760 1761 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1762 fprintf (FILE, "\t.long\tL%d\n", VALUE); 1763 1764 /* This is how to output an element of a case-vector that is relative. */ 1765 1766 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1767 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL); 1768 1769 #undef SIZE_TYPE 1770 #define SIZE_TYPE "unsigned int" 1771 1772 #undef PTRDIFF_TYPE 1773 #define PTRDIFF_TYPE "int" 1774 1775 #undef WCHAR_TYPE 1776 #define WCHAR_TYPE "long int" 1777 1778 #undef WCHAR_TYPE_SIZE 1779 #define WCHAR_TYPE_SIZE 32 1780 1781 #define INT_TYPE_SIZE 32 1782 #define LONG_LONG_TYPE_SIZE 64 1783 #define FLOAT_TYPE_SIZE 32 1784 #define DOUBLE_TYPE_SIZE 32 1785 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */ 1786 1787 /* Output #ident as a .ident. */ 1788 1789 #define ASM_OUTPUT_IDENT(FILE, NAME) \ 1790 fprintf (FILE, "\t.ident \"%s\"\n", NAME); 1791 1792 /* Output of Uninitialized Variables. */ 1793 1794 /* This says how to output an assembler line to define a local 1795 uninitialized variable. */ 1796 1797 #undef ASM_OUTPUT_LOCAL 1798 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1799 ( fputs ("\t.bss\t", FILE), \ 1800 assemble_name (FILE, (NAME)), \ 1801 fprintf (FILE, ",%u\n", (ROUNDED))) 1802 1803 /* This says how to output an assembler line to define a global 1804 uninitialized variable. */ 1805 1806 #undef ASM_OUTPUT_COMMON 1807 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1808 ( fputs ("\t.globl\t", FILE), \ 1809 assemble_name (FILE, (NAME)), \ 1810 fputs ("\n\t.bss\t", FILE), \ 1811 assemble_name (FILE, (NAME)), \ 1812 fprintf (FILE, ",%u\n", (ROUNDED))) 1813 1814 #undef ASM_OUTPUT_BSS 1815 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1816 ( fputs ("\t.globl\t", FILE), \ 1817 assemble_name (FILE, (NAME)), \ 1818 fputs ("\n\t.bss\t", FILE), \ 1819 assemble_name (FILE, (NAME)), \ 1820 fprintf (FILE, ",%u\n", (SIZE))) 1821 1822 /* Macros Controlling Initialization Routines. */ 1823 1824 #define OBJECT_FORMAT_COFF 1825 #define REAL_NM_FILE_NAME "c4x-nm" 1826 1827 /* Output of Assembler Instructions. */ 1828 1829 /* Register names when used for integer modes. */ 1830 1831 #define REGISTER_NAMES \ 1832 { \ 1833 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1834 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \ 1835 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \ 1836 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \ 1837 } 1838 1839 /* Alternate register names when used for floating point modes. */ 1840 1841 #define FLOAT_REGISTER_NAMES \ 1842 { \ 1843 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 1844 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \ 1845 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \ 1846 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \ 1847 } 1848 1849 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE) 1850 1851 /* Determine which codes are valid without a following integer. These must 1852 not be alphabetic. */ 1853 1854 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#') 1855 1856 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X) 1857 1858 /* C4x specific pragmas. */ 1859 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ 1860 cpp_register_pragma (PFILE, 0, "CODE_SECTION", c4x_pr_CODE_SECTION); \ 1861 cpp_register_pragma (PFILE, 0, "DATA_SECTION", c4x_pr_DATA_SECTION); \ 1862 cpp_register_pragma (PFILE, 0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \ 1863 cpp_register_pragma (PFILE, 0, "FUNC_EXT_CALLED", c4x_pr_ignored); \ 1864 cpp_register_pragma (PFILE, 0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \ 1865 cpp_register_pragma (PFILE, 0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \ 1866 cpp_register_pragma (PFILE, 0, "FUNC_NEVER_RETURNS", \ 1867 c4x_pr_FUNC_NEVER_RETURNS); \ 1868 cpp_register_pragma (PFILE, 0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \ 1869 cpp_register_pragma (PFILE, 0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \ 1870 cpp_register_pragma (PFILE, 0, "INTERRUPT", c4x_pr_INTERRUPT); \ 1871 } while (0) 1872 1873 /* Assembler Commands for Alignment. */ 1874 1875 #define ASM_OUTPUT_SKIP(FILE, SIZE) \ 1876 { int c = SIZE; \ 1877 for (; c > 0; --c) \ 1878 fprintf (FILE,"\t.word\t0\n"); \ 1879 } 1880 1881 #define ASM_NO_SKIP_IN_TEXT 1 1882 1883 /* I'm not sure about this one. FIXME. */ 1884 1885 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 1886 if ((LOG) != 0) \ 1887 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG))) 1888 1889 1890 /* Macros for SDB and DWARF Output (use .sdef instead of .def 1891 to avoid conflict with TI's use of .def). */ 1892 1893 #define SDB_DELIM "\n" 1894 #define SDB_DEBUGGING_INFO 1 1895 1896 /* Don't use octal since this can confuse gas for the c4x. */ 1897 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM) 1898 1899 #define PUT_SDB_DEF(A) \ 1900 do { fprintf (asm_out_file, "\t.sdef\t"); \ 1901 ASM_OUTPUT_LABELREF (asm_out_file, A); \ 1902 fprintf (asm_out_file, SDB_DELIM); } while (0) 1903 1904 #define PUT_SDB_PLAIN_DEF(A) \ 1905 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM) 1906 1907 #define PUT_SDB_BLOCK_START(LINE) \ 1908 fprintf (asm_out_file, \ 1909 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \ 1910 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) 1911 1912 #define PUT_SDB_BLOCK_END(LINE) \ 1913 fprintf (asm_out_file, \ 1914 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \ 1915 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) 1916 1917 #define PUT_SDB_FUNCTION_START(LINE) \ 1918 fprintf (asm_out_file, \ 1919 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \ 1920 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) 1921 1922 /* Note we output relative line numbers for .ef which gas converts 1923 to absolute line numbers. The TI compiler outputs absolute line numbers 1924 in the .sym directive which gas does not support. */ 1925 #define PUT_SDB_FUNCTION_END(LINE) \ 1926 fprintf (asm_out_file, \ 1927 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \ 1928 SDB_DELIM, SDB_DELIM, SDB_DELIM, \ 1929 (LINE), SDB_DELIM) 1930 1931 #define PUT_SDB_EPILOGUE_END(NAME) \ 1932 do { fprintf (asm_out_file, "\t.sdef\t"); \ 1933 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \ 1934 fprintf (asm_out_file, \ 1935 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \ 1936 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0) 1937 1938 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1939 1940 #define DEFAULT_SIGNED_CHAR 1 1941 1942 /* A function address in a call instruction is a byte address (for 1943 indexing purposes) so give the MEM rtx a byte's mode. */ 1944 1945 #define FUNCTION_MODE QImode 1946 1947 #define SLOW_BYTE_ACCESS 0 1948 1949 /* Specify the machine mode that pointers have. After generation of 1950 RTL, the compiler makes no further distinction between pointers and 1951 any other objects of this machine mode. */ 1952 1953 #define Pmode QImode 1954 1955 /* On the C4x we can write the following code. We have to clear the cache 1956 every time we execute it because the data in the stack could change. 1957 1958 laj $+4 1959 addi3 4,r11,ar0 1960 lda *ar0,ar1 1961 lda *+ar0(1),ar0 1962 bud ar1 1963 nop 1964 nop 1965 or 1000h,st 1966 .word FNADDR 1967 .word CXT 1968 1969 On the c3x this is a bit more difficult. We have to write self 1970 modifying code here. So we have to clear the cache every time 1971 we execute it because the data in the stack could change. 1972 1973 ldiu TOP_OF_FUNCTION,ar1 1974 lsh 16,ar1 1975 or BOTTOM_OF_FUNCTION,ar1 1976 ldiu TOP_OF_STATIC,ar0 1977 bud ar1 1978 lsh 16,ar0 1979 or BOTTOM_OF_STATIC,ar0 1980 or 1000h,st 1981 1982 */ 1983 1984 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10) 1985 1986 #define TRAMPOLINE_TEMPLATE(FILE) \ 1987 { \ 1988 if (TARGET_C3X) \ 1989 { \ 1990 fprintf (FILE, "\tldiu\t0,ar1\n"); \ 1991 fprintf (FILE, "\tlsh\t16,ar1\n"); \ 1992 fprintf (FILE, "\tor\t0,ar1\n"); \ 1993 fprintf (FILE, "\tldiu\t0,ar0\n"); \ 1994 fprintf (FILE, "\tbud\tar1\n"); \ 1995 fprintf (FILE, "\tlsh\t16,ar0\n"); \ 1996 fprintf (FILE, "\tor\t0,ar0\n"); \ 1997 fprintf (FILE, "\tor\t1000h,st\n"); \ 1998 } \ 1999 else \ 2000 { \ 2001 fprintf (FILE, "\tlaj\t$+4\n"); \ 2002 fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \ 2003 fprintf (FILE, "\tlda\t*ar0,ar1\n"); \ 2004 fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \ 2005 fprintf (FILE, "\tbud\tar1\n"); \ 2006 fprintf (FILE, "\tnop\n"); \ 2007 fprintf (FILE, "\tnop\n"); \ 2008 fprintf (FILE, "\tor\t1000h,st\n"); \ 2009 fprintf (FILE, "\t.word\t0\n"); \ 2010 fprintf (FILE, "\t.word\t0\n"); \ 2011 } \ 2012 } 2013 2014 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 2015 { \ 2016 if (TARGET_C3X) \ 2017 { \ 2018 rtx tmp1, tmp2; \ 2019 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \ 2020 size_int (16), 0, 1); \ 2021 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \ 2022 GEN_INT (0x5069), size_int (16), 0, 1); \ 2023 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \ 2024 emit_move_insn (gen_rtx (MEM, QImode, \ 2025 plus_constant (tramp, 0)), tmp1); \ 2026 tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \ 2027 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \ 2028 GEN_INT (0x1069), size_int (16), 0, 1); \ 2029 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \ 2030 emit_move_insn (gen_rtx (MEM, QImode, \ 2031 plus_constant (tramp, 2)), tmp1); \ 2032 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \ 2033 size_int (16), 0, 1); \ 2034 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \ 2035 GEN_INT (0x5068), size_int (16), 0, 1); \ 2036 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \ 2037 emit_move_insn (gen_rtx (MEM, QImode, \ 2038 plus_constant (tramp, 3)), tmp1); \ 2039 tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \ 2040 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \ 2041 GEN_INT (0x1068), size_int (16), 0, 1); \ 2042 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \ 2043 emit_move_insn (gen_rtx (MEM, QImode, \ 2044 plus_constant (tramp, 6)), tmp1); \ 2045 } \ 2046 else \ 2047 { \ 2048 emit_move_insn (gen_rtx (MEM, QImode, \ 2049 plus_constant (TRAMP, 8)), FNADDR); \ 2050 emit_move_insn (gen_rtx (MEM, QImode, \ 2051 plus_constant (TRAMP, 9)), CXT); \ 2052 } \ 2053 } 2054 2055 /* Specify the machine mode that this machine uses for the index in 2056 the tablejump instruction. */ 2057 2058 #define CASE_VECTOR_MODE Pmode 2059 2060 /* Max number of (32-bit) bytes we can move from memory to memory 2061 in one reasonably fast instruction. */ 2062 2063 #define MOVE_MAX 1 2064 2065 /* MOVE_RATIO is the number of move instructions that is better than a 2066 block move. */ 2067 2068 #define MOVE_RATIO 3 2069 2070 #define BSS_SECTION_ASM_OP "\t.bss" 2071 2072 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2073 fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO]) 2074 2075 /* This is how to output an insn to pop a register from the stack. 2076 It need not be very fast code. */ 2077 2078 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2079 fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO]) 2080 2081 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2082 is done just by pretending it is already truncated. */ 2083 2084 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2085 2086 /* We need to use direct addressing for large constants and addresses 2087 that cannot fit within an instruction. We must check for these 2088 after after the final jump optimisation pass, since this may 2089 introduce a local_move insn for a SYMBOL_REF. This pass 2090 must come before delayed branch slot filling since it can generate 2091 additional instructions. */ 2092 2093 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS) 2094 2095 #define DBR_OUTPUT_SEQEND(FILE) \ 2096 if (final_sequence != NULL_RTX) \ 2097 { \ 2098 int count; \ 2099 rtx insn = XVECEXP (final_sequence, 0, 0); \ 2100 int laj = GET_CODE (insn) == CALL_INSN \ 2101 || (GET_CODE (insn) == INSN \ 2102 && GET_CODE (PATTERN (insn)) == TRAP_IF);\ 2103 \ 2104 count = dbr_sequence_length(); \ 2105 while (count < (laj ? 2 : 3)) \ 2106 { \ 2107 fputs("\tnop\n", FILE); \ 2108 count++; \ 2109 } \ 2110 if (laj) \ 2111 fputs("\tpush\tr11\n", FILE); \ 2112 } 2113 2114 #define NO_FUNCTION_CSE 2115 2116 /* We don't want a leading tab. */ 2117 2118 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING) 2119 2120 /* Define the codes that are matched by predicates in c4x.c. */ 2121 2122 #define PREDICATE_CODES \ 2123 {"fp_zero_operand", {CONST_DOUBLE}}, \ 2124 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \ 2125 {"stik_const_operand", {CONST_INT}}, \ 2126 {"not_const_operand", {CONST_INT}}, \ 2127 {"reg_operand", {REG, SUBREG}}, \ 2128 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\ 2129 {"r0r1_reg_operand", {REG, SUBREG}}, \ 2130 {"r2r3_reg_operand", {REG, SUBREG}}, \ 2131 {"ext_low_reg_operand", {REG, SUBREG}}, \ 2132 {"ext_reg_operand", {REG, SUBREG}}, \ 2133 {"std_reg_operand", {REG, SUBREG}}, \ 2134 {"std_or_reg_operand", {REG, SUBREG}}, \ 2135 {"addr_reg_operand", {REG, SUBREG}}, \ 2136 {"index_reg_operand", {REG, SUBREG}}, \ 2137 {"dp_reg_operand", {REG}}, \ 2138 {"sp_reg_operand", {REG}}, \ 2139 {"st_reg_operand", {REG}}, \ 2140 {"rc_reg_operand", {REG}}, \ 2141 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \ 2142 {"dst_operand", {SUBREG, REG, MEM}}, \ 2143 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \ 2144 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \ 2145 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \ 2146 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \ 2147 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \ 2148 {"nonimmediate_lsrc_operand", {SUBREG, REG, MEM}}, \ 2149 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \ 2150 {"par_ind_operand", {MEM}}, \ 2151 {"parallel_operand", {SUBREG, REG, MEM}}, \ 2152 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 2153 {"mem_operand", {MEM}}, 2154 2155 2156 /* Define the intrinsic functions for the c3x/c4x. */ 2157 2158 enum c4x_builtins 2159 { 2160 /* intrinsic name */ 2161 C4X_BUILTIN_FIX, /* fast_ftoi */ 2162 C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */ 2163 C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */ 2164 C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */ 2165 C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */ 2166 C4X_BUILTIN_RCPF /* fast_invf (only C4x) */ 2167 }; 2168