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Searched refs:BH (Results 1 – 25 of 48) sorted by relevance

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/openbsd/gnu/llvm/compiler-rt/lib/builtins/hexagon/
H A Ddfaddsub.S15 #define BH r3 macro
80 EXPB = extractu(BH,#EXPBITS,#HI_MANTBITS)
128 B_POS = cmp.gt(BH,#-1)
154 BH = togglebit(BH,#31) define
166 BH = #1 define
170 BH = asl(BH,#31) define
174 if (p0.new) AH = xor(AH,BH)
316 p1 = cmp.gt(BH,#-1)
333 BH = ##0x80000000 define
336 if (!p0) AH = or(AH,BH)
[all …]
H A Ddffma.S19 #define BH r3 macro
147 TMP = xor(AH,BH)
454 BH = USR define
458 if (p0) BH = or(BH,BL)
461 USR = BH
475 BH = extractu(TMP,#2,#SR_ROUND_OFF) define
480 BH ^= lsr(AH,#31)
481 BL = BH
485 p0 = !cmp.eq(BH,#2)
607 BH = convert_df2sf(B) define
[all …]
H A Ddfdiv.S16 #define BH r3 macro
81 EXPBA = combine(BH,AH)
82 SIGN = xor(AH,BH)
88 #undef BH
211 #define BH r3 macro
402 EXPBA = combine(BH,AH)
404 BH = insert(TMP,#DF_EXPBITS+1,#DF_MANTBITS-32) // clear out hidden bit, sign bit define
408 if (P_TMP2) BH = or(BH,TMP) // if normal, add back in hidden bit
435 AH = xor(AH,BH)
450 AH = xor(AH,BH)
H A Ddfmul.S14 #define BH r3 macro
114 EXP1 = extractu(BH,#EXPBITS,#HI_MANTBITS)
119 TMP = xor(AH,BH)
400 BH = extract(BH,#1,#31) define
403 AH ^= asl(BH,#31)
/openbsd/regress/lib/libcrypto/x509/bettertls/certificates/
H A D1734.key16 ZLCsCv5A2cqNe5ImrFUPu+BH/aT6PUiwpTuAgR78y0t00AVlC6tU24RYupwChfsT
H A D2842.key6 BH+k+UjSJpCXl0Hj82vpGrrgz+f3JhTnt+/jp7iJvh4SWfTGnMONgRoNHMc0L+vL
H A D2987.key18 FNFztY6cVB7Q415CmSGdv3e0kw1pVCSizPwlg3sDAoGBAOVnk/6KNwHVIM6HE/BH
H A D2801.chain36 pRyYc79FdC8UYbwTarbnz1Qg2I+BH+u5wi7q//aWCzI5N8jX54AcgdWalIlrp7iJ
H A D2674.chain17 ACFJx28d/BH+PNMtKcTQ9s9ISrONqKIU+lx7Ajfds8mgWkifNlgqW27WQQtuipph
H A D2758.chain21 aUCirrgQjmBoDgmY1K+D18Tu8UE1B2z4TIokhuJY+BH+a5c6z7HjwoKjfqFY3usY
H A D3110.chain46 BH+YJ9/ol9W8kutE4lXH99KiU3KdfJspbw==
/openbsd/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp187 {codeview::RegisterId::BH, X86::BH}, in initLLVMToSEHAndCVRegMapping()
767 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
768 return X86::BH; in getX86SubSuperRegisterOrZero()
779 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
816 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
852 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
888 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86RegisterInfo.td61 def BH : X86Reg<"bh", 7>;
116 def BX : X86Reg<"bx", 3, [BL,BH]>;
388 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
394 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
396 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
454 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
467 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
468 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
H A DX86FixupGadgets.cpp360 case X86::BH: in getWidestRegForReg()
444 case X86::BH: in getEquivalentRegForReg()
451 return X86::BH; in getEquivalentRegForReg()
H A DREADME-X86-64.txt44 It's not possible to reference AH, BH, CH, and DH registers in an instruction
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleM55.td204 "t2USA", "t2USUB", "t2UXTA[BH]")>;
213 def : InstRW<[M55WriteCX_DI], (instregex "t2LDR[BH]?i12$", "t2LDRS?[BH]?s$",
226 "tMOVr$", "tUXT[BH]$", "tSXT[BH]$")>;
230 "t2MOVr$", "t2SUBS?ri$", "t2[US]XT[BH]$")>;
H A DARMScheduleR52.td293 "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)",
491 "RFE", "t2RFE", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
496 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
497 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
H A DARMScheduleSwift.td358 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
492 "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
497 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
498 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2301 def : InstRW<[A64FXWrite_INDEX_RI_BH], (instregex "^INDEX_(RI|IR)_[BH]")>;
2314 def : InstRW<[A64FXWrite_INDEX_II_BH], (instregex "^INDEX_II_[BH]")>;
2321 def : InstRW<[A64FXWrite_INDEX_RR_BH], (instregex "^INDEX_RR_[BH]")>;
2374 def : InstRW<[A64FXWrite_LD2_BH], (instregex "^LD2[BH]")>;
2395 def : InstRW<[A64FXWrite_LD3_BH], (instregex "^LD3[BH]")>;
2416 def : InstRW<[A64FXWrite_LD4_BH], (instregex "^LD4[BH]")>;
2503 (instregex "^SST1[BH]_S(_[^I]|$)", "^SST1W(_[^ID]|$)")>;
2519 (instregex "^SST1[BH]_S_I", "^SST1W_I")>;
2534 def : InstRW<[A64FXWrite_ST2_BH], (instregex "^ST2[BH]")>;
2555 def : InstRW<[A64FXWrite_ST3_BH], (instregex "^ST3[BH]")>;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1459 bits<2> BH;
1466 let Inst{19-20} = BH;
1480 let BH = 0;
1487 let BH = 0;
1495 let BH = 0;
1552 bits<2> BH;
1562 let Inst{19-20} = BH;
1581 let BH = 0;
1598 let Inst{19-20} = 0; // Unused (BH)
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp760 auto [BH, EH] = std::make_pair(std::begin(HvxInts), std::end(HvxInts)); in getIntrinsicId()
766 auto FoundHvx = std::lower_bound(BH, EH, Hvx{Opc, 0, 0}, CmpOpcode); in getIntrinsicId()
/openbsd/share/misc/
H A Dcountrycodes33 BH:BAHRAIN
/openbsd/gnu/llvm/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp788 const unsigned ExegesisX86Target::kUnavailableRegisters[4] = {X86::AH, X86::BH,
794 X86::AH, X86::BH, X86::CH, X86::DH, X86::XMM8, X86::XMM9,
/openbsd/share/zoneinfo/datfiles/
H A Diso3166.tab54 BH Bahrain
/openbsd/gnu/llvm/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h83 ENTRY(BH) \

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