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Searched refs:BIC (Results 1 – 25 of 28) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td367 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(BIC|EON|ORN)[WX]rr")>;
368 def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "(BIC)S[WX]rr")>;
373 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>;
383 def : InstRW<[TSV110WrISReg], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]rs$")>;
388 def : InstRW<[TSV110WrISRegBr], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)S[WX]rs$")>;
578 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(AND|BIC|BIF|BIT|BSL|EOR|MVN|NOT|ORN|ORR)v")…
H A DAArch64SchedCyclone.td143 // ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr
157 // ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs
376 // BIC,ORR V,#imm are WriteV
416 // AND,BIC,CMTST,EOR,ORN,ORR
H A DAArch64SchedExynosM5.td637 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
638 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
641 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>;
642 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>;
793 def : InstRW<[M5WriteNALU2], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
H A DAArch64SchedFalkorDetails.td660 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
661 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIC|ORR)(v2i32|v4i16)$")>;
724 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
725 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIC|ORR)(v8i16|v4i32)$")>;
896 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^BIC(S)?(W|X)r(r|s)$")>;
H A DAArch64SchedExynosM3.td501 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
504 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
621 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
H A DAArch64SchedThunderX2T99.td429 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
451 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
470 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
1234 // ASIMD logical (AND, BIC, EOR)
1362 "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;
H A DAArch64SchedThunderX3T110.td689 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
711 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
730 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
1342 // ASIMD logical (AND, BIC, EOR)
1470 "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;
H A DAArch64SchedA55.td424 "(ORR|BIC)v(2i32|4i16|8i8)$", "MVNIv(2i|2s|4i16)")>;
426 "(ORR|BIC)v(16i8|4i32|8i16)$", "MVNIv(4i32|4s|8i16)")>;
H A DAArch64SchedExynosM4.td599 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
601 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
745 def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
H A DAArch64SchedA64FX.td606 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
626 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
643 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
1363 // ASIMD logical (AND, BIC, EOR)
1499 "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;
H A DAArch64SchedKryoDetails.td435 …(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")…
441 …(instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))…
453 (instregex "(BIC|ORR)S?Wri")>;
459 (instregex "(BIC|ORR)S?Xri")>;
H A DAArch64SchedAmpere1.td939 (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)(W|X)r")>;
941 (instregex "(ADD|AND|BIC|SUB)S(W|X)r")>;
H A DAArch64ISelLowering.h123 BIC, enumerator
H A DAArch64SchedNeoverseN2.td1522 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>;
1761 "^(AND|BIC|EOR|EOR(BT|TB)?|ORR)_ZZZ$",
1763 "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]$")>;
H A DAArch64InstrInfo.td2220 defm BIC : LogicalReg<0b00, 1, "bic",
4837 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
6384 // AdvSIMD BIC
6385 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
H A DAArch64SVEInstrInfo.td370 def AArch64bic_node : SDNode<"AArch64ISD::BIC", SDT_AArch64Arith_Unpred>;
H A DAArch64ISelLowering.cpp2454 MAKE_CASE(AArch64ISD::BIC) in getTargetNodeName()
18215 return convertMergedOpToPredOp(N, AArch64ISD::BIC, DAG, true); in performIntrinsicCombine()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleM7.td326 (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
H A DARMScheduleSwift.td130 // AND,BIC,EOR,ORN,ORR
H A DARMScheduleA57.td170 // ADD{S}, ADC{S}, ADR, AND{S}, BIC{S}, CMN, CMP, EOR{S}, ORN{S}, ORR{S},
H A DARMInstrThumb.td1094 // BIC register
H A DARMInstrInfo.td4168 defm BIC : AsI1_bin_irs<0b1110, "bic",
6326 // Same for AND <--> BIC
H A DARMInstrThumb2.td5232 // Same for AND <--> BIC
/openbsd/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td546 defm BIC : Arith<0b1100, "bic", bic, 0, []>;
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td67 def BIC : CondBranchRXY<"bi#", 0xe347>,

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