| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrArithmetic.td | 988 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
989 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
990 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
1123 def NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1125 def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
1126 def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
1127 def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
1155 def NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1156 def NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>;
1157 def NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
[all …]
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| H A D | X86FastISel.cpp | 2874 unsigned BaseOpc, CondCode; in fastLowerIntrinsicCall() local
2878 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2880 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2882 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2884 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2886 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2888 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2903 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && in fastLowerIntrinsicCall()
2907 bool IsDec = BaseOpc == ISD::SUB; in fastLowerIntrinsicCall()
2925 if (BaseOpc == X86ISD::UMUL && !ResultReg) { in fastLowerIntrinsicCall()
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 703 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti() local
715 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
738 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
756 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
758 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
763 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
769 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 442 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
460 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
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| H A D | AMDGPUBaseInfo.cpp | 350 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMTBUFOpcode() argument
351 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMTBUFOpcode()
380 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMUBUFOpcode() argument
381 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMUBUFOpcode()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 917 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in ScalarizeVecOp_VECREDUCE_SEQ() local
920 return DAG.getNode(BaseOpc, SDLoc(N), N->getValueType(0), in ScalarizeVecOp_VECREDUCE_SEQ()
6513 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE() local
6514 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE()
6551 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE_SEQ() local
6552 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE_SEQ()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 3194 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
3195 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
3203 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5924 unsigned BaseOpc; in lowerVectorMaskVecReduction() local
5938 BaseOpc = ISD::AND; in lowerVectorMaskVecReduction()
5946 BaseOpc = ISD::OR; in lowerVectorMaskVecReduction()
5955 BaseOpc = ISD::XOR; in lowerVectorMaskVecReduction()
5971 return DAG.getNode(BaseOpc, DL, XLenVT, SetCC, Op.getOperand(0)); in lowerVectorMaskVecReduction()
6018 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode()); in lowerVECREDUCE() local
6026 Vec = DAG.getNode(BaseOpc, DL, VecEVT, Lo, Hi); in lowerVECREDUCE()
6047 DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags()); in lowerVECREDUCE()
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