Searched refs:C20_MPLLA_TX_CLK_DIV_MASK (Results 1 – 2 of 2) sorted by relevance
206 #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) macro
2392 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()