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Searched refs:CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c80 …{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__…
H A Dci_baco.c91 …{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__…
H A Dtonga_baco.c82 …{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__…
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h101 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 macro
H A Dsmu_7_1_1_sh_mask.h101 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 macro
H A Dsmu_7_0_1_sh_mask.h101 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 macro
H A Dsmu_7_1_0_sh_mask.h101 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 macro
H A Dsmu_7_1_2_sh_mask.h101 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 macro
H A Dsmu_7_1_3_sh_mask.h125 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 macro