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Searched refs:CP_ME_CNTL__CE_HALT_MASK (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v7_0.c2370 CP_ME_CNTL__CE_HALT_MASK)); in gfx_v7_0_cp_gfx_enable()
4622 …G32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); in gfx_v7_0_soft_reset()
H A Dgfx_v6_0.c1922 CP_ME_CNTL__CE_HALT_MASK)); in gfx_v6_0_cp_gfx_enable()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2560 #define CP_ME_CNTL__CE_HALT_MASK 0x01000000L macro
H A Dgfx_7_2_sh_mask.h3045 #define CP_ME_CNTL__CE_HALT_MASK 0x1000000 macro
H A Dgfx_8_0_sh_mask.h3659 #define CP_ME_CNTL__CE_HALT_MASK 0x1000000 macro
H A Dgfx_8_1_sh_mask.h4181 #define CP_ME_CNTL__CE_HALT_MASK 0x1000000 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1173 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_9_1_sh_mask.h1072 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_9_2_1_sh_mask.h1039 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_9_4_3_sh_mask.h1089 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_9_4_2_sh_mask.h1672 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_11_0_0_sh_mask.h24035 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_10_1_0_sh_mask.h6661 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_11_0_3_sh_mask.h26381 #define CP_ME_CNTL__CE_HALT_MASK … macro
H A Dgc_10_3_0_sh_mask.h6927 #define CP_ME_CNTL__CE_HALT_MASK … macro