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Searched refs:DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK (Results 1 – 19 of 19) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h1441 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 macro
H A Ddce_10_0_sh_mask.h1469 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 macro
H A Ddce_11_0_sh_mask.h1377 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 macro
H A Ddce_11_2_sh_mask.h1501 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 macro
H A Ddce_12_0_sh_mask.h2476 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h77 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_0_3_sh_mask.h455 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_1_0_sh_mask.h1896 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_2_1_0_sh_mask.h392 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_0_1_sh_mask.h780 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_2_1_sh_mask.h178 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_1_2_sh_mask.h686 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_1_5_sh_mask.h193 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_1_4_sh_mask.h8099 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_1_6_sh_mask.h1212 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_0_2_sh_mask.h505 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_2_0_0_sh_mask.h510 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_0_0_sh_mask.h491 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro
H A Ddcn_3_2_0_sh_mask.h179 #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … macro