| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dccg.c | 458 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
465 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
475 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
482 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
492 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
499 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
509 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
516 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
526 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
533 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
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| H A D | dcn31_dccg.h | 65 SR(DCCG_GATE_DISABLE_CNTL2),\
139 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
140 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
141 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
142 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
143 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
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| H A D | dcn31_hwseq.c | 249 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dcn31_init_hw()
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| H A D | dcn31_resource.c | 685 SR(DCCG_GATE_DISABLE_CNTL2), \
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dccg.h | 73 SR(DCCG_GATE_DISABLE_CNTL2),\
191 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
192 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
193 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
194 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
195 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
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| H A D | dcn314_resource.c | 691 SR(DCCG_GATE_DISABLE_CNTL2), \
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dccg.h | 289 uint32_t DCCG_GATE_DISABLE_CNTL2; member
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dce/ |
| H A D | dce_hwseq.h | 199 SR(DCCG_GATE_DISABLE_CNTL2), \
424 SR(DCCG_GATE_DISABLE_CNTL2), \
636 uint32_t DCCG_GATE_DISABLE_CNTL2; member
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_hwseq.c | 365 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dcn201_init_hw()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_hwseq.c | 594 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dcn30_init_hw()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn316/ |
| H A D | dcn316_resource.c | 681 SR(DCCG_GATE_DISABLE_CNTL2), \
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_hwseq.c | 943 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dcn32_init_hw()
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| H A D | dcn32_resource.c | 532 SR(DCCG_GATE_DISABLE_CNTL2), \
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn315/ |
| H A D | dcn315_resource.c | 684 SR(DCCG_GATE_DISABLE_CNTL2), \
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn321/ |
| H A D | dcn321_resource.c | 531 SR(DCCG_GATE_DISABLE_CNTL2), \
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 1606 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dcn10_init_hw()
|