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Searched refs:DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT (Results 1 – 19 of 19) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5610 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012 macro
H A Ddce_8_0_sh_mask.h6912 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 macro
H A Ddce_10_0_sh_mask.h14909 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 macro
H A Ddce_11_0_sh_mask.h15057 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 macro
H A Ddce_11_2_sh_mask.h15719 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 macro
H A Ddce_12_0_sh_mask.h7977 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h471 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h2523 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_1_0_sh_mask.h4956 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h3673 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h3888 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h1176 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h3646 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h12010 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h4215 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h3855 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h3941 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h3959 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h1178 #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … macro