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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK (Results 1 – 16 of 16) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5809 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L macro
H A Ddce_8_0_sh_mask.h7967 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 macro
H A Ddce_10_0_sh_mask.h6995 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 macro
H A Ddce_11_0_sh_mask.h6897 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 macro
H A Ddce_11_2_sh_mask.h7969 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 macro
H A Ddce_12_0_sh_mask.h4917 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1539 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_1_0_sh_mask.h3879 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_2_1_0_sh_mask.h2385 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_1_sh_mask.h2526 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_2_sh_mask.h2010 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_4_sh_mask.h10640 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_3_1_6_sh_mask.h2577 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_2_sh_mask.h2456 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_2_0_0_sh_mask.h2653 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro
H A Ddcn_3_0_0_sh_mask.h2523 #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … macro