| /openbsd/gnu/llvm/llvm/utils/TableGen/ |
| H A D | InfoByHwMode.h | 34 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
49 if (M != DefaultMode) in union_modes()
54 Modes.push_back(DefaultMode); in union_modes()
81 bool hasDefault() const { return hasMode(DefaultMode); } in hasDefault()
85 assert(hasMode(DefaultMode)); in get()
86 Map.insert({Mode, Map.at(DefaultMode)}); in get()
92 if (Mode != DefaultMode && F == Map.end()) in get()
93 F = Map.find(DefaultMode); in get()
100 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
111 Map.insert(std::make_pair(DefaultMode, I)); in makeSimple()
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| H A D | RegisterBankEmitter.cpp | 84 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
85 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
245 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
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| H A D | CodeGenHwModes.h | 43 enum : unsigned { DefaultMode = 0 }; enumerator
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| H A D | InfoByHwMode.cpp | 26 if (Mode == DefaultMode) in getModeName()
68 auto D = Map.find(DefaultMode); in getOrCreateTypeForMode()
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| H A D | CodeGenHwModes.cpp | 81 return DefaultMode; in getHwModeId()
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| H A D | CodeGenDAGPatterns.cpp | 133 if (DefaultMode == M) { in insert()
155 if (M == DefaultMode || hasMode(M)) in constrain()
157 Map.insert({M, Map.at(DefaultMode)}); in constrain()
816 const TypeSetByHwMode::SetType &LegalTypes = Legal.get(DefaultMode); in expandOverloads()
879 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1817 if (S.get(DefaultMode).empty()) in setDefaultMode()
4448 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4463 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4465 AppendPattern(P, DefaultMode, DefaultCheck); in ExpandHwModeBasedTypes()
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| H A D | CodeGenDAGPatterns.h | 227 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isDefaultOnly()
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| H A D | CodeGenRegisters.cpp | 799 RSI.insertRegSizeForMode(DefaultMode, RI); in CodeGenRegisterClass()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 474 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
476 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
478 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
480 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
482 def VecF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
484 def VecF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
487 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
489 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
491 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
493 def VecPF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIModeRegister.cpp | 122 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon4004eaa60111::SIModeRegister
124 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
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| /openbsd/gnu/llvm/llvm/lib/Target/LoongArch/ |
| H A D | LoongArch.td | 32 defvar LA32 = DefaultMode;
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVFeatures.td | 483 defvar RV32 = DefaultMode;
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| /openbsd/gnu/llvm/llvm/include/llvm/Target/ |
| H A D | Target.td | 34 def DefaultMode : HwMode<"">;
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