1 /* $OpenBSD: if_alcreg.h,v 1.8 2022/01/09 05:42:46 jsg Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 29 */ 30 31 #ifndef _IF_ALCREG_H 32 #define _IF_ALCREG_H 33 34 #define ALC_PCIR_BAR 0x10 35 36 #define ATHEROS_AR8152_B_V10 0xC0 37 #define ATHEROS_AR8152_B_V11 0xC1 38 39 /* 40 * Atheros AR816x/AR817x revisions 41 */ 42 #define AR816X_REV_A0 0 43 #define AR816X_REV_A1 1 44 #define AR816X_REV_B0 2 45 #define AR816X_REV_C0 3 46 47 #define AR816X_REV_SHIFT 3 48 #define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT) 49 50 /* 0x0000 - 0x02FF : PCIe configuration space */ 51 52 #define ALC_PEX_UNC_ERR_SEV 0x10C 53 #define PEX_UNC_ERR_SEV_TRN 0x00000001 54 #define PEX_UNC_ERR_SEV_DLP 0x00000010 55 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 56 #define PEX_UNC_ERR_SEV_FCP 0x00002000 57 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 58 #define PEX_UNC_ERR_SEV_CA 0x00008000 59 #define PEX_UNC_ERR_SEV_UC 0x00010000 60 #define PEX_UNC_ERR_SEV_ROV 0x00020000 61 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 62 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 63 #define PEX_UNC_ERR_SEV_UR 0x00100000 64 65 #define ALC_EEPROM_LD 0x204 /* AR816x */ 66 #define EEPROM_LD_START 0x00000001 67 #define EEPROM_LD_IDLE 0x00000010 68 #define EEPROM_LD_DONE 0x00000000 69 #define EEPROM_LD_PROGRESS 0x00000020 70 #define EEPROM_LD_EXIST 0x00000100 71 #define EEPROM_LD_EEPROM_EXIST 0x00000200 72 #define EEPROM_LD_FLASH_EXIST 0x00000400 73 #define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 74 #define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 75 76 #define ALC_TWSI_CFG 0x218 77 #define TWSI_CFG_SW_LD_START 0x00000800 78 #define TWSI_CFG_HW_LD_START 0x00001000 79 #define TWSI_CFG_LD_EXIST 0x00400000 80 81 #define ALC_SLD 0x218 /* AR816x */ 82 #define SLD_START 0x00000800 83 #define SLD_PROGRESS 0x00001000 84 #define SLD_IDLE 0x00002000 85 #define SLD_SLVADDR_MASK 0x007F0000 86 #define SLD_EXIST 0x00800000 87 #define SLD_FREQ_MASK 0x03000000 88 #define SLD_FREQ_100K 0x00000000 89 #define SLD_FREQ_200K 0x01000000 90 #define SLD_FREQ_300K 0x02000000 91 #define SLD_FREQ_400K 0x03000000 92 93 #define PCIEM_LINK_CAP_ASPM 0x00000c00 94 #define PCIEM_LINK_CTL_RCB 0x0008 95 #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 96 #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 97 #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 98 #define PCIEM_LINK_CTL_ASPMC 0x0003 99 100 #define ALC_PCIE_PHYMISC 0x1000 101 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 102 103 #define ALC_PCIE_PHYMISC2 0x1004 104 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 105 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 106 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 107 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 108 109 #define ALC_PDLL_TRNS1 0x1104 110 #define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800 111 112 #define ALC_TWSI_DEBUG 0x1108 113 #define TWSI_DEBUG_DEV_EXIST 0x20000000 114 115 #define ALC_EEPROM_CFG 0x12C0 116 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 117 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 118 #define EEPROM_CFG_ACK 0x40000000 119 #define EEPROM_CFG_RW 0x80000000 120 #define EEPROM_CFG_DATA_HI_SHIFT 0 121 #define EEPROM_CFG_ADDR_SHIFT 16 122 123 #define ALC_EEPROM_DATA_LO 0x12C4 124 125 #define ALC_OPT_CFG 0x12F0 126 #define OPT_CFG_CLK_ENB 0x00000002 127 128 #define ALC_PM_CFG 0x12F8 129 #define PM_CFG_SERDES_ENB 0x00000001 130 #define PM_CFG_RBER_ENB 0x00000002 131 #define PM_CFG_CLK_REQ_ENB 0x00000004 132 #define PM_CFG_ASPM_L1_ENB 0x00000008 133 #define PM_CFG_SERDES_L1_ENB 0x00000010 134 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 135 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 136 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 137 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 138 #define PM_CFG_RX_L1_AFTER_L0S 0x00000800 139 #define PM_CFG_ASPM_L0S_ENB 0x00001000 140 #define PM_CFG_CLK_SWH_L1 0x00002000 141 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 142 #define PM_CFG_PCIE_RECV 0x00008000 143 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 144 #define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000 145 #define PM_CFG_TX_L1_AFTER_L0S 0x00080000 146 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 147 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 148 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 149 #define PM_CFG_SA_DLY_ENB 0x20000000 150 #define PM_CFG_MAC_ASPM_CHK 0x40000000 151 #define PM_CFG_HOTRST 0x80000000 152 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 153 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 154 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 155 #define PM_CFG_LCKDET_TIMER_SHIFT 24 156 157 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 158 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 159 #define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4 160 #define PM_CFG_LCKDET_TIMER_DEFAULT 12 161 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 162 #define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15 163 164 #define ALC_LTSSM_ID_CFG 0x12FC 165 #define LTSSM_ID_WRO_ENB 0x00001000 166 167 #define ALC_MASTER_CFG 0x1400 168 #define MASTER_RESET 0x00000001 169 #define MASTER_TEST_MODE_MASK 0x0000000C 170 #define MASTER_BERT_START 0x00000010 171 #define MASTER_OOB_DIS_OFF 0x00000040 172 #define MASTER_SA_TIMER_ENB 0x00000080 173 #define MASTER_MTIMER_ENB 0x00000100 174 #define MASTER_MANUAL_INTR_ENB 0x00000200 175 #define MASTER_IM_TX_TIMER_ENB 0x00000400 176 #define MASTER_IM_RX_TIMER_ENB 0x00000800 177 #define MASTER_CLK_SEL_DIS 0x00001000 178 #define MASTER_CLK_SWH_MODE 0x00002000 179 #define MASTER_INTR_RD_CLR 0x00004000 180 #define MASTER_CHIP_REV_MASK 0x00FF0000 181 #define MASTER_CHIP_ID_MASK 0x7F000000 182 #define MASTER_OTP_SEL 0x80000000 183 #define MASTER_TEST_MODE_SHIFT 2 184 #define MASTER_CHIP_REV_SHIFT 16 185 #define MASTER_CHIP_ID_SHIFT 24 186 187 /* Number of ticks per usec for AR813x/AR815x. */ 188 #define ALC_TICK_USECS 2 189 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 190 191 #define ALC_MANUAL_TIMER 0x1404 192 193 #define ALC_IM_TIMER 0x1408 194 #define IM_TIMER_TX_MASK 0x0000FFFF 195 #define IM_TIMER_RX_MASK 0xFFFF0000 196 #define IM_TIMER_TX_SHIFT 0 197 #define IM_TIMER_RX_SHIFT 16 198 #define ALC_IM_TIMER_MIN 0 199 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 200 /* 201 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 202 * interrupts in a second. 203 */ 204 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 205 /* 206 * alc(4) does not rely on Tx completion interrupts, so set it 207 * somewhat large value to reduce Tx completion interrupts. 208 */ 209 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 210 211 #define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */ 212 213 #define GPHY_CFG_EXT_RESET 0x0001 214 #define GPHY_CFG_RTL_MODE 0x0002 215 #define GPHY_CFG_LED_MODE 0x0004 216 #define GPHY_CFG_ANEG_NOW 0x0008 217 #define GPHY_CFG_RECV_ANEG 0x0010 218 #define GPHY_CFG_GATE_25M_ENB 0x0020 219 #define GPHY_CFG_LPW_EXIT 0x0040 220 #define GPHY_CFG_PHY_IDDQ 0x0080 221 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 222 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 223 #define GPHY_CFG_HIB_EN 0x0400 224 #define GPHY_CFG_HIB_PULSE 0x0800 225 #define GPHY_CFG_SEL_ANA_RESET 0x1000 226 #define GPHY_CFG_PHY_PLL_ON 0x2000 227 #define GPHY_CFG_PWDOWN_HW 0x4000 228 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 229 #define GPHY_CFG_100AB_ENB 0x00020000 230 231 #define ALC_IDLE_STATUS 0x1410 232 #define IDLE_STATUS_RXMAC 0x00000001 233 #define IDLE_STATUS_TXMAC 0x00000002 234 #define IDLE_STATUS_RXQ 0x00000004 235 #define IDLE_STATUS_TXQ 0x00000008 236 #define IDLE_STATUS_DMARD 0x00000010 237 #define IDLE_STATUS_DMAWR 0x00000020 238 #define IDLE_STATUS_SMB 0x00000040 239 #define IDLE_STATUS_CMB 0x00000080 240 241 #define ALC_MDIO 0x1414 242 #define MDIO_DATA_MASK 0x0000FFFF 243 #define MDIO_REG_ADDR_MASK 0x001F0000 244 #define MDIO_OP_READ 0x00200000 245 #define MDIO_OP_WRITE 0x00000000 246 #define MDIO_SUP_PREAMBLE 0x00400000 247 #define MDIO_OP_EXECUTE 0x00800000 248 #define MDIO_CLK_25_4 0x00000000 249 #define MDIO_CLK_25_6 0x02000000 250 #define MDIO_CLK_25_8 0x03000000 251 #define MDIO_CLK_25_10 0x04000000 252 #define MDIO_CLK_25_14 0x05000000 253 #define MDIO_CLK_25_20 0x06000000 254 #define MDIO_CLK_25_128 0x07000000 255 #define MDIO_OP_BUSY 0x08000000 256 #define MDIO_AP_ENB 0x10000000 257 #define MDIO_MODE_EXT 0x40000000 258 #define MDIO_DATA_SHIFT 0 259 #define MDIO_REG_ADDR_SHIFT 16 260 261 #define MDIO_REG_ADDR(x) \ 262 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 263 /* Default PHY address. */ 264 #define ALC_PHY_ADDR 0 265 266 #define ALC_PHY_STATUS 0x1418 267 #define PHY_STATUS_RECV_ENB 0x00000001 268 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 269 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 270 #define PHY_STATUS_LPW_STATE 0x80000000 271 #define PHY_STATIS_OE_PWSP_SHIFT 16 272 273 /* Packet memory BIST. */ 274 #define ALC_BIST0 0x141C 275 #define BIST0_ENB 0x00000001 276 #define BIST0_SRAM_FAIL 0x00000002 277 #define BIST0_FUSE_FLAG 0x00000004 278 279 /* PCIe retry buffer BIST. */ 280 #define ALC_BIST1 0x1420 281 #define BIST1_ENB 0x00000001 282 #define BIST1_SRAM_FAIL 0x00000002 283 #define BIST1_FUSE_FLAG 0x00000004 284 285 #define ALC_SERDES_LOCK 0x1424 286 #define SERDES_LOCK_DET 0x00000001 287 #define SERDES_LOCK_DET_ENB 0x00000002 288 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 289 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 290 291 #define ALC_LPI_CTL 0x1440 292 #define LPI_CTL_ENB 0x00000001 293 294 #define ALC_EXT_MDIO 0x1448 295 #define EXT_MDIO_REG_MASK 0x0000FFFF 296 #define EXT_MDIO_DEVADDR_MASK 0x001F0000 297 #define EXT_MDIO_REG_SHIFT 0 298 #define EXT_MDIO_DEVADDR_SHIFT 16 299 300 #define EXT_MDIO_REG(x) \ 301 (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK) 302 #define EXT_MDIO_DEVADDR(x) \ 303 (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK) 304 305 #define ALC_IDLE_DECISN_TIMER 0x1474 306 #define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400 307 308 #define ALC_MAC_CFG 0x1480 309 #define MAC_CFG_TX_ENB 0x00000001 310 #define MAC_CFG_RX_ENB 0x00000002 311 #define MAC_CFG_TX_FC 0x00000004 312 #define MAC_CFG_RX_FC 0x00000008 313 #define MAC_CFG_LOOP 0x00000010 314 #define MAC_CFG_FULL_DUPLEX 0x00000020 315 #define MAC_CFG_TX_CRC_ENB 0x00000040 316 #define MAC_CFG_TX_AUTO_PAD 0x00000080 317 #define MAC_CFG_TX_LENCHK 0x00000100 318 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 319 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 320 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 321 #define MAC_CFG_PROMISC 0x00008000 322 #define MAC_CFG_TX_PAUSE 0x00010000 323 #define MAC_CFG_SCNT 0x00020000 324 #define MAC_CFG_SYNC_RST_TX 0x00040000 325 #define MAC_CFG_SIM_RST_TX 0x00080000 326 #define MAC_CFG_SPEED_MASK 0x00300000 327 #define MAC_CFG_SPEED_10_100 0x00100000 328 #define MAC_CFG_SPEED_1000 0x00200000 329 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 330 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 331 #define MAC_CFG_RXCSUM_ENB 0x01000000 332 #define MAC_CFG_ALLMULTI 0x02000000 333 #define MAC_CFG_BCAST 0x04000000 334 #define MAC_CFG_DBG 0x08000000 335 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 336 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 337 #define MAC_CFG_SPEED_MODE_SW 0x40000000 338 #define MAC_CFG_FAST_PAUSE 0x80000000 339 #define MAC_CFG_PREAMBLE_SHIFT 10 340 #define MAC_CFG_PREAMBLE_DEFAULT 7 341 342 #define ALC_IPG_IFG_CFG 0x1484 343 #define IPG_IFG_IPGT_MASK 0x0000007F 344 #define IPG_IFG_MIFG_MASK 0x0000FF00 345 #define IPG_IFG_IPG1_MASK 0x007F0000 346 #define IPG_IFG_IPG2_MASK 0x7F000000 347 #define IPG_IFG_IPGT_SHIFT 0 348 #define IPG_IFG_IPGT_DEFAULT 0x60 349 #define IPG_IFG_MIFG_SHIFT 8 350 #define IPG_IFG_MIFG_DEFAULT 0x50 351 #define IPG_IFG_IPG1_SHIFT 16 352 #define IPG_IFG_IPG1_DEFAULT 0x40 353 #define IPG_IFG_IPG2_SHIFT 24 354 #define IPG_IFG_IPG2_DEFAULT 0x60 355 356 /* Station address. */ 357 #define ALC_PAR0 0x1488 358 #define ALC_PAR1 0x148C 359 360 /* 64bit multicast hash register. */ 361 #define ALC_MAR0 0x1490 362 #define ALC_MAR1 0x1494 363 364 /* half-duplex parameter configuration. */ 365 #define ALC_HDPX_CFG 0x1498 366 #define HDPX_CFG_LCOL_MASK 0x000003FF 367 #define HDPX_CFG_RETRY_MASK 0x0000F000 368 #define HDPX_CFG_EXC_DEF_EN 0x00010000 369 #define HDPX_CFG_NO_BACK_C 0x00020000 370 #define HDPX_CFG_NO_BACK_P 0x00040000 371 #define HDPX_CFG_ABEBE 0x00080000 372 #define HDPX_CFG_ABEBT_MASK 0x00F00000 373 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 374 #define HDPX_CFG_LCOL_SHIFT 0 375 #define HDPX_CFG_LCOL_DEFAULT 0x37 376 #define HDPX_CFG_RETRY_SHIFT 12 377 #define HDPX_CFG_RETRY_DEFAULT 0x0F 378 #define HDPX_CFG_ABEBT_SHIFT 20 379 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 380 #define HDPX_CFG_JAMIPG_SHIFT 24 381 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 382 383 #define ALC_FRAME_SIZE 0x149C 384 385 #define ALC_WOL_CFG 0x14A0 386 #define WOL_CFG_PATTERN 0x00000001 387 #define WOL_CFG_PATTERN_ENB 0x00000002 388 #define WOL_CFG_MAGIC 0x00000004 389 #define WOL_CFG_MAGIC_ENB 0x00000008 390 #define WOL_CFG_LINK_CHG 0x00000010 391 #define WOL_CFG_LINK_CHG_ENB 0x00000020 392 #define WOL_CFG_PATTERN_DET 0x00000100 393 #define WOL_CFG_MAGIC_DET 0x00000200 394 #define WOL_CFG_LINK_CHG_DET 0x00000400 395 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 396 #define WOL_CFG_PATTERN0 0x00010000 397 #define WOL_CFG_PATTERN1 0x00020000 398 #define WOL_CFG_PATTERN2 0x00040000 399 #define WOL_CFG_PATTERN3 0x00080000 400 #define WOL_CFG_PATTERN4 0x00100000 401 #define WOL_CFG_PATTERN5 0x00200000 402 #define WOL_CFG_PATTERN6 0x00400000 403 404 /* WOL pattern length. */ 405 #define ALC_PATTERN_CFG0 0x14A4 406 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 407 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 408 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 409 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 410 411 #define ALC_PATTERN_CFG1 0x14A8 412 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 413 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 414 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 415 416 /* RSS */ 417 #define ALC_RSS_KEY0 0x14B0 418 419 #define ALC_RSS_KEY1 0x14B4 420 421 #define ALC_RSS_KEY2 0x14B8 422 423 #define ALC_RSS_KEY3 0x14BC 424 425 #define ALC_RSS_KEY4 0x14C0 426 427 #define ALC_RSS_KEY5 0x14C4 428 429 #define ALC_RSS_KEY6 0x14C8 430 431 #define ALC_RSS_KEY7 0x14CC 432 433 #define ALC_RSS_KEY8 0x14D0 434 435 #define ALC_RSS_KEY9 0x14D4 436 437 #define ALC_RSS_IDT_TABLE0 0x14E0 438 439 #define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */ 440 441 #define ALC_RSS_IDT_TABLE1 0x14E4 442 443 #define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */ 444 445 #define ALC_RSS_IDT_TABLE2 0x14E8 446 447 #define ALC_RSS_IDT_TABLE3 0x14EC 448 449 #define ALC_RSS_IDT_TABLE4 0x14F0 450 451 #define ALC_RSS_IDT_TABLE5 0x14F4 452 453 #define ALC_RSS_IDT_TABLE6 0x14F8 454 455 #define ALC_RSS_IDT_TABLE7 0x14FC 456 457 #define ALC_SRAM_RD0_ADDR 0x1500 458 459 #define ALC_SRAM_RD1_ADDR 0x1504 460 461 #define ALC_SRAM_RD2_ADDR 0x1508 462 463 #define ALC_SRAM_RD3_ADDR 0x150C 464 465 #define RD_HEAD_ADDR_MASK 0x000003FF 466 #define RD_TAIL_ADDR_MASK 0x03FF0000 467 #define RD_HEAD_ADDR_SHIFT 0 468 #define RD_TAIL_ADDR_SHIFT 16 469 470 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 471 #define RD_NIC_LEN_MASK 0x000003FF 472 473 #define ALC_RD_NIC_LEN1 0x1514 474 475 #define ALC_SRAM_TD_ADDR 0x1518 476 #define TD_HEAD_ADDR_MASK 0x000003FF 477 #define TD_TAIL_ADDR_MASK 0x03FF0000 478 #define TD_HEAD_ADDR_SHIFT 0 479 #define TD_TAIL_ADDR_SHIFT 16 480 481 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 482 #define SRAM_TD_LEN_MASK 0x000003FF 483 484 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 485 486 #define ALC_SRAM_RX_FIFO_LEN 0x1524 487 #define SRAM_RX_FIFO_LEN_MASK 0x00000FFF 488 #define SRAM_RX_FIFO_LEN_SHIFT 0 489 490 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 491 492 #define ALC_SRAM_TX_FIFO_LEN 0x152C 493 494 #define ALC_SRAM_TCPH_ADDR 0x1530 495 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 496 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 497 #define SRAM_TCPH_ADDR_SHIFT 0 498 #define SRAM_PKTH_ADDR_SHIFT 16 499 500 #define ALC_DMA_BLOCK 0x1534 501 #define DMA_BLOCK_LOAD 0x00000001 502 503 #define ALC_RX_BASE_ADDR_HI 0x1540 504 505 #define ALC_TX_BASE_ADDR_HI 0x1544 506 507 #define ALC_SMB_BASE_ADDR_HI 0x1548 508 509 #define ALC_SMB_BASE_ADDR_LO 0x154C 510 511 #define ALC_RD0_HEAD_ADDR_LO 0x1550 512 513 #define ALC_RD1_HEAD_ADDR_LO 0x1554 514 515 #define ALC_RD2_HEAD_ADDR_LO 0x1558 516 517 #define ALC_RD3_HEAD_ADDR_LO 0x155C 518 519 #define ALC_RD_RING_CNT 0x1560 520 #define RD_RING_CNT_MASK 0x00000FFF 521 #define RD_RING_CNT_SHIFT 0 522 523 #define ALC_RX_BUF_SIZE 0x1564 524 #define RX_BUF_SIZE_MASK 0x0000FFFF 525 /* 526 * If larger buffer size than 1536 is specified the controller 527 * will be locked up. This is hardware limitation. 528 */ 529 #define RX_BUF_SIZE_MAX 1536 530 531 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 532 533 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 534 535 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 536 537 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 538 539 #define ALC_RRD_RING_CNT 0x1578 540 #define RRD_RING_CNT_MASK 0x00000FFF 541 #define RRD_RING_CNT_SHIFT 0 542 543 #define ALC_TDH_HEAD_ADDR_LO 0x157C 544 545 #define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */ 546 547 #define ALC_TDL_HEAD_ADDR_LO 0x1580 548 549 #define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */ 550 551 #define ALC_TD_RING_CNT 0x1584 552 #define TD_RING_CNT_MASK 0x0000FFFF 553 #define TD_RING_CNT_SHIFT 0 554 555 #define ALC_CMB_BASE_ADDR_LO 0x1588 556 557 #define ALC_TXQ_CFG 0x1590 558 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 559 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 560 #define TXQ_CFG_ENB 0x00000020 561 #define TXQ_CFG_ENHANCED_MODE 0x00000040 562 #define TXQ_CFG_8023_ENB 0x00000080 563 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 564 #define TXQ_CFG_TD_BURST_SHIFT 0 565 #define TXQ_CFG_TD_BURST_DEFAULT 5 566 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 567 568 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 569 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 570 #define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800 571 #define TSO_OFFLOAD_THRESH_SHIFT 0 572 #define TSO_OFFLOAD_THRESH_UNIT 8 573 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 574 575 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 576 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 577 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 578 #define TXF_WATER_MARK_BURST_ENB 0x80000000 579 #define TXF_WATER_MARK_LO_SHIFT 0 580 #define TXF_WATER_MARK_HI_SHIFT 16 581 582 #define ALC_THROUGHPUT_MON 0x159C 583 #define THROUGHPUT_MON_RATE_MASK 0x00000003 584 #define THROUGHPUT_MON_ENB 0x00000080 585 #define THROUGHPUT_MON_RATE_SHIFT 0 586 587 #define ALC_RXQ_CFG 0x15A0 588 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 589 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 590 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 591 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 592 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 593 #define RXQ_CFG_QUEUE1_ENB 0x00000010 594 #define RXQ_CFG_QUEUE2_ENB 0x00000020 595 #define RXQ_CFG_QUEUE3_ENB 0x00000040 596 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 597 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 598 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 599 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 600 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 601 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 602 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 603 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 604 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 605 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 606 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 607 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 608 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 609 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 610 #define RXQ_CFG_QUEUE0_ENB 0x80000000 611 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 612 #define RXQ_CFG_RD_BURST_DEFAULT 8 613 #define RXQ_CFG_RD_BURST_SHIFT 20 614 #define RXQ_CFG_ENB \ 615 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 616 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 617 618 /* AR816x specific bits */ 619 #define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004 620 #define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008 621 #define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010 622 #define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020 623 #define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C 624 #define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080 625 #define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00 626 #define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8 627 #define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100 628 629 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 630 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 631 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 632 #define RX_RD_FREE_THRESH_HI_SHIFT 0 633 #define RX_RD_FREE_THRESH_LO_SHIFT 6 634 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 635 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 636 637 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 638 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 639 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 640 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 641 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 642 643 /* 644 * Size = tx-packet(1522) IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + 645 * rx-packet(1522) + delay-of-link(64) = 3212. 646 */ 647 #define RX_FIFO_PAUSE_816X_RSVD 3212 648 649 #define ALC_RD_DMA_CFG 0x15AC 650 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 651 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 652 #define RD_DMA_CFG_THRESH_SHIFT 0 653 #define RD_DMA_CFG_TIMER_SHIFT 16 654 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 655 #define RD_DMA_CFG_TIMER_DEFAULT 0 656 #define RD_DMA_CFG_TICK_USECS 8 657 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 658 659 #define ALC_RSS_HASH_VALUE 0x15B0 660 661 #define ALC_RSS_HASH_FLAG 0x15B4 662 663 #define ALC_RSS_CPU 0x15B8 664 665 #define ALC_DMA_CFG 0x15C0 666 #define DMA_CFG_IN_ORDER 0x00000001 667 #define DMA_CFG_ENH_ORDER 0x00000002 668 #define DMA_CFG_OUT_ORDER 0x00000004 669 #define DMA_CFG_RCB_64 0x00000000 670 #define DMA_CFG_RCB_128 0x00000008 671 #define DMA_CFG_RD_BURST_128 0x00000000 672 #define DMA_CFG_RD_BURST_256 0x00000010 673 #define DMA_CFG_RD_BURST_512 0x00000020 674 #define DMA_CFG_RD_BURST_1024 0x00000030 675 #define DMA_CFG_RD_BURST_2048 0x00000040 676 #define DMA_CFG_RD_BURST_4096 0x00000050 677 #define DMA_CFG_WR_BURST_128 0x00000000 678 #define DMA_CFG_WR_BURST_256 0x00000080 679 #define DMA_CFG_WR_BURST_512 0x00000100 680 #define DMA_CFG_WR_BURST_1024 0x00000180 681 #define DMA_CFG_WR_BURST_2048 0x00000200 682 #define DMA_CFG_WR_BURST_4096 0x00000280 683 #define DMA_CFG_RD_REQ_PRI 0x00000400 684 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 685 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 686 #define DMA_CFG_CMB_ENB 0x00100000 687 #define DMA_CFG_SMB_ENB 0x00200000 688 #define DMA_CFG_CMB_NOW 0x00400000 689 #define DMA_CFG_SMB_DIS 0x01000000 690 #define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000 691 #define DMA_CFG_RD_CHNL_SEL_1 0x00000000 692 #define DMA_CFG_RD_CHNL_SEL_2 0x04000000 693 #define DMA_CFG_RD_CHNL_SEL_3 0x08000000 694 #define DMA_CFG_RD_CHNL_SEL_4 0x0C000000 695 #define DMA_CFG_WSRAM_RDCTL 0x10000000 696 #define DMA_CFG_RD_PEND_CLR 0x20000000 697 #define DMA_CFG_WR_PEND_CLR 0x40000000 698 #define DMA_CFG_SMB_NOW 0x80000000 699 #define DMA_CFG_RD_BURST_MASK 0x07 700 #define DMA_CFG_RD_BURST_SHIFT 4 701 #define DMA_CFG_WR_BURST_MASK 0x07 702 #define DMA_CFG_WR_BURST_SHIFT 7 703 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 704 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 705 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 706 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 707 708 #define ALC_SMB_STAT_TIMER 0x15C4 709 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 710 #define SMB_STAT_TIMER_SHIFT 0 711 712 #define ALC_CMB_TD_THRESH 0x15C8 713 #define CMB_TD_THRESH_MASK 0x0000FFFF 714 #define CMB_TD_THRESH_SHIFT 0 715 716 #define ALC_CMB_TX_TIMER 0x15CC 717 #define CMB_TX_TIMER_MASK 0x0000FFFF 718 #define CMB_TX_TIMER_SHIFT 0 719 720 #define ALC_MSI_MAP_TBL1 0x15D0 721 722 #define ALC_MSI_ID_MAP 0x15D4 723 724 #define ALC_MSI_MAP_TBL2 0x15D8 725 726 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 727 728 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 729 730 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 731 732 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 733 734 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 735 #define MBOX_RD_PROD_SHIFT 0 736 737 #define ALC_MBOX_TD_PROD_IDX 0x15F0 738 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 739 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 740 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 741 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 742 743 #define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */ 744 #define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */ 745 #define ALC_MBOX_TD_CONS_IDX 0x15F4 746 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 747 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 748 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 749 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 750 751 #define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */ 752 #define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */ 753 754 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 755 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 756 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 757 #define MBOX_RD0_CONS_IDX_SHIFT 0 758 #define MBOX_RD1_CONS_IDX_SHIFT 16 759 760 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 761 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 762 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 763 #define MBOX_RD2_CONS_IDX_SHIFT 0 764 #define MBOX_RD3_CONS_IDX_SHIFT 16 765 766 #define ALC_INTR_STATUS 0x1600 767 #define INTR_SMB 0x00000001 768 #define INTR_TIMER 0x00000002 769 #define INTR_MANUAL_TIMER 0x00000004 770 #define INTR_RX_FIFO_OFLOW 0x00000008 771 #define INTR_RD0_UNDERRUN 0x00000010 772 #define INTR_RD1_UNDERRUN 0x00000020 773 #define INTR_RD2_UNDERRUN 0x00000040 774 #define INTR_RD3_UNDERRUN 0x00000080 775 #define INTR_TX_FIFO_UNDERRUN 0x00000100 776 #define INTR_DMA_RD_TO_RST 0x00000200 777 #define INTR_DMA_WR_TO_RST 0x00000400 778 #define INTR_TX_CREDIT 0x00000800 779 #define INTR_GPHY 0x00001000 780 #define INTR_GPHY_LOW_PW 0x00002000 781 #define INTR_TXQ_TO_RST 0x00004000 782 #define INTR_TX_PKT0 0x00008000 783 #define INTR_RX_PKT0 0x00010000 784 #define INTR_RX_PKT1 0x00020000 785 #define INTR_RX_PKT2 0x00040000 786 #define INTR_RX_PKT3 0x00080000 787 #define INTR_MAC_RX 0x00100000 788 #define INTR_MAC_TX 0x00200000 789 #define INTR_UNDERRUN 0x00400000 790 #define INTR_FRAME_ERROR 0x00800000 791 #define INTR_FRAME_OK 0x01000000 792 #define INTR_CSUM_ERROR 0x02000000 793 #define INTR_PHY_LINK_DOWN 0x04000000 794 #define INTR_DIS_INT 0x80000000 795 796 /* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */ 797 #define INTR_TX_PKT1 0x00000020 798 #define INTR_TX_PKT2 0x00000040 799 #define INTR_TX_PKT3 0x00000080 800 #define INTR_RX_PKT4 0x08000000 801 #define INTR_RX_PKT5 0x10000000 802 #define INTR_RX_PKT6 0x20000000 803 #define INTR_RX_PKT7 0x40000000 804 805 /* Interrupt Mask Register */ 806 #define ALC_INTR_MASK 0x1604 807 808 #define INTR_TX_PKT INTR_TX_PKT0 809 #define INTR_RX_PKT INTR_RX_PKT0 810 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 811 812 #define ALC_INTRS \ 813 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 814 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 815 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 816 INTR_TX_FIFO_UNDERRUN) 817 #define ALC_INTR_RETRIG_TIMER 0x1608 818 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 819 #define INTR_RETRIG_TIMER_SHIFT 0 820 821 #define ALC_HDS_CFG 0x160C 822 #define HDS_CFG_ENB 0x00000001 823 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 824 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 825 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 826 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 827 828 #define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */ 829 #define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */ 830 #define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */ 831 #define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */ 832 833 /* AR813x/AR815x registers for MAC statistics */ 834 #define ALC_RX_MIB_BASE 0x1700 835 836 #define ALC_TX_MIB_BASE 0x1760 837 838 #define ALC_DRV 0x1804 /* AR816x */ 839 #define DRV_ASPM_SPD10LMT_1M 0x00000000 840 #define DRV_ASPM_SPD10LMT_10M 0x00000001 841 #define DRV_ASPM_SPD10LMT_100M 0x00000002 842 #define DRV_ASPM_SPD10LMT_NO 0x00000003 843 #define DRV_ASPM_SPD10LMT_MASK 0x00000003 844 #define DRV_ASPM_SPD100LMT_1M 0x00000000 845 #define DRV_ASPM_SPD100LMT_10M 0x00000004 846 #define DRV_ASPM_SPD100LMT_100M 0x00000008 847 #define DRV_ASPM_SPD100LMT_NO 0x0000000C 848 #define DRV_ASPM_SPD100LMT_MASK 0x0000000C 849 #define DRV_ASPM_SPD1000LMT_100M 0x00000000 850 #define DRV_ASPM_SPD1000LMT_NO 0x00000010 851 #define DRV_ASPM_SPD1000LMT_1M 0x00000020 852 #define DRV_ASPM_SPD1000LMT_10M 0x00000030 853 #define DRV_ASPM_SPD1000LMT_MASK 0x00000000 854 #define DRV_WOLCAP_BIOS_EN 0x00000100 855 #define DRV_WOLMAGIC_EN 0x00000200 856 #define DRV_WOLLINKUP_EN 0x00000400 857 #define DRV_WOLPATTERN_EN 0x00000800 858 #define DRV_AZ_EN 0x00001000 859 #define DRV_WOLS5_BIOS_EN 0x00010000 860 #define DRV_WOLS5_EN 0x00020000 861 #define DRV_DISABLE 0x00040000 862 #define DRV_PHY_MASK 0x1FE00000 863 #define DRV_PHY_EEE 0x00200000 864 #define DRV_PHY_APAUSE 0x00400000 865 #define DRV_PHY_PAUSE 0x00800000 866 #define DRV_PHY_DUPLEX 0x01000000 867 #define DRV_PHY_10 0x02000000 868 #define DRV_PHY_100 0x04000000 869 #define DRV_PHY_1000 0x08000000 870 #define DRV_PHY_AUTO 0x10000000 871 #define DRV_PHY_SHIFT 21 872 873 #define ALC_CLK_GATING_CFG 0x1814 874 #define CLK_GATING_DMAW_ENB 0x0001 875 #define CLK_GATING_DMAR_ENB 0x0002 876 #define CLK_GATING_TXQ_ENB 0x0004 877 #define CLK_GATING_RXQ_ENB 0x0008 878 #define CLK_GATING_TXMAC_ENB 0x0010 879 #define CLK_GATING_RXMAC_ENB 0x0020 880 881 #define ALC_DEBUG_DATA0 0x1900 882 883 #define ALC_DEBUG_DATA1 0x1904 884 885 #define ALC_MSI_RETRANS_TIMER 0x1920 886 #define MSI_RETRANS_TIMER_MASK 0x0000FFFF 887 #define MSI_RETRANS_MASK_SEL_STD 0x00000000 888 #define MSI_RETRANS_MASK_SEL_LINE 0x00010000 889 #define MSI_RETRANS_TIMER_SHIFT 0 890 891 #define ALC_WRR 0x1938 892 #define WRR_PRI0_MASK 0x0000001F 893 #define WRR_PRI1_MASK 0x00001F00 894 #define WRR_PRI2_MASK 0x001F0000 895 #define WRR_PRI3_MASK 0x1F000000 896 #define WRR_PRI_RESTRICT_MASK 0x60000000 897 #define WRR_PRI_RESTRICT_ALL 0x00000000 898 #define WRR_PRI_RESTRICT_HI 0x20000000 899 #define WRR_PRI_RESTRICT_HI2 0x40000000 900 #define WRR_PRI_RESTRICT_NONE 0x60000000 901 #define WRR_PRI0_SHIFT 0 902 #define WRR_PRI1_SHIFT 8 903 #define WRR_PRI2_SHIFT 16 904 #define WRR_PRI3_SHIFT 24 905 #define WRR_PRI_DEFAULT 4 906 #define WRR_PRI_RESTRICT_SHIFT 29 907 908 #define ALC_HQTD_CFG 0x193C 909 #define HQTD_CFG_Q1_BURST_MASK 0x0000000F 910 #define HQTD_CFG_Q2_BURST_MASK 0x000000F0 911 #define HQTD_CFG_Q3_BURST_MASK 0x00000F00 912 #define HQTD_CFG_BURST_ENB 0x80000000 913 #define HQTD_CFG_Q1_BURST_SHIFT 0 914 #define HQTD_CFG_Q2_BURST_SHIFT 4 915 #define HQTD_CFG_Q3_BURST_SHIFT 8 916 917 #define ALC_MISC 0x19C0 918 #define MISC_INTNLOSC_OPEN 0x00000008 919 #define MISC_ISO_ENB 0x00001000 920 #define MISC_PSW_OCP_MASK 0x00E00000 921 #define MISC_PSW_OCP_SHIFT 21 922 #define MISC_PSW_OCP_DEFAULT 7 923 924 #define ALC_MISC2 0x19C8 925 #define MISC2_CALB_START 0x00000001 926 927 #define ALC_MISC3 0x19CC 928 #define MISC3_25M_NOTO_INTNL 0x00000001 929 #define MISC3_25M_BY_SW 0x00000002 930 931 #define ALC_MII_DBG_ADDR 0x1D 932 #define ALC_MII_DBG_DATA 0x1E 933 934 #define MII_ANA_CFG0 0x00 935 #define ANA_RESTART_CAL 0x0001 936 #define ANA_MANUL_SWICH_ON_MASK 0x001E 937 #define ANA_MAN_ENABLE 0x0020 938 #define ANA_SEL_HSP 0x0040 939 #define ANA_EN_HB 0x0080 940 #define ANA_EN_HBIAS 0x0100 941 #define ANA_OEN_125M 0x0200 942 #define ANA_EN_LCKDT 0x0400 943 #define ANA_LCKDT_PHY 0x0800 944 #define ANA_AFE_MODE 0x1000 945 #define ANA_VCO_SLOW 0x2000 946 #define ANA_VCO_FAST 0x4000 947 #define ANA_SEL_CLK125M_DSP 0x8000 948 #define ANA_MANUL_SWICH_ON_SHIFT 1 949 950 #define MII_DBG_ANACTL 0x00 951 #define DBG_ANACTL_DEFAULT 0x02EF 952 953 #define MII_ANA_CFG4 0x04 954 #define ANA_IECHO_ADJ_MASK 0x0F 955 #define ANA_IECHO_ADJ_3_MASK 0x000F 956 #define ANA_IECHO_ADJ_2_MASK 0x00F0 957 #define ANA_IECHO_ADJ_1_MASK 0x0F00 958 #define ANA_IECHO_ADJ_0_MASK 0xF000 959 #define ANA_IECHO_ADJ_3_SHIFT 0 960 #define ANA_IECHO_ADJ_2_SHIFT 4 961 #define ANA_IECHO_ADJ_1_SHIFT 8 962 #define ANA_IECHO_ADJ_0_SHIFT 12 963 964 #define MII_DBG_SYSMODCTL 0x04 965 #define DBG_SYSMODCTL_DEFAULT 0xBB8B 966 967 #define MII_ANA_CFG5 0x05 968 #define ANA_SERDES_CDR_BW_MASK 0x0003 969 #define ANA_MS_PAD_DBG 0x0004 970 #define ANA_SPEEDUP_DBG 0x0008 971 #define ANA_SERDES_TH_LOS_MASK 0x0030 972 #define ANA_SERDES_EN_DEEM 0x0040 973 #define ANA_SERDES_TXELECIDLE 0x0080 974 #define ANA_SERDES_BEACON 0x0100 975 #define ANA_SERDES_HALFTXDR 0x0200 976 #define ANA_SERDES_SEL_HSP 0x0400 977 #define ANA_SERDES_EN_PLL 0x0800 978 #define ANA_SERDES_EN 0x1000 979 #define ANA_SERDES_EN_LCKDT 0x2000 980 #define ANA_SERDES_CDR_BW_SHIFT 0 981 #define ANA_SERDES_TH_LOS_SHIFT 4 982 983 #define MII_DBG_SRDSYSMOD 0x05 984 #define DBG_SRDSYSMOD_DEFAULT 0x2C46 985 986 #define MII_ANA_CFG11 0x0B 987 #define ANA_PS_HIB_EN 0x8000 988 989 #define MII_DBG_HIBNEG 0x0B 990 #define DBG_HIBNEG_HIB_PULSE 0x1000 991 #define DBG_HIBNEG_PSHIB_EN 0x8000 992 #define DBG_HIBNEG_DEFAULT 0xBC40 993 994 #define MII_ANA_CFG18 0x12 995 #define ANA_TEST_MODE_10BT_01MASK 0x0003 996 #define ANA_LOOP_SEL_10BT 0x0004 997 #define ANA_RGMII_MODE_SW 0x0008 998 #define ANA_EN_LONGECABLE 0x0010 999 #define ANA_TEST_MODE_10BT_2 0x0020 1000 #define ANA_EN_10BT_IDLE 0x0400 1001 #define ANA_EN_MASK_TB 0x0800 1002 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 1003 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 1004 #define ANA_TEST_MODE_10BT_01SHIFT 0 1005 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 1006 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 1007 1008 #define MII_DBG_TST10BTCFG 0x12 1009 #define DBG_TST10BTCFG_DEFAULT 0x4C04 1010 1011 #define MII_DBG_AZ_ANADECT 0x15 1012 #define DBG_AZ_ANADECT_DEFAULT 0x3220 1013 #define DBG_AZ_ANADECT_LONG 0x3210 1014 1015 #define MII_DBG_MSE16DB 0x18 1016 #define DBG_MSE16DB_UP 0x05EA 1017 #define DBG_MSE16DB_DOWN 0x02EA 1018 1019 #define MII_DBG_MSE20DB 0x1C 1020 #define DBG_MSE20DB_TH_MASK 0x01FC 1021 #define DBG_MSE20DB_TH_DEFAULT 0x2E 1022 #define DBG_MSE20DB_TH_HI 0x54 1023 #define DBG_MSE20DB_TH_SHIFT 2 1024 1025 #define MII_DBG_AGC 0x23 1026 #define DBG_AGC_2_VGA_MASK 0x3F00 1027 #define DBG_AGC_2_VGA_SHIFT 8 1028 #define DBG_AGC_LONG1G_LIMT 40 1029 #define DBG_AGC_LONG100M_LIMT 44 1030 1031 #define MII_ANA_CFG41 0x29 1032 #define ANA_TOP_PS_EN 0x8000 1033 1034 #define MII_DBG_LEGCYPS 0x29 1035 #define DBG_LEGCYPS_ENB 0x8000 1036 #define DBG_LEGCYPS_DEFAULT 0x129D 1037 1038 #define MII_ANA_CFG54 0x36 1039 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 1040 #define ANA_DESERVED 0x0040 1041 #define ANA_EN_LIT_CH 0x0080 1042 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 1043 #define ANA_BP_BAD_LINK_ACCUM 0x4000 1044 #define ANA_BP_SMALL_BW 0x8000 1045 #define ANA_LONG_CABLE_TH_100_SHIFT 0 1046 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 1047 1048 #define MII_DBG_TST100BTCFG 0x36 1049 #define DBG_TST100BTCFG_DEFAULT 0xE12C 1050 1051 #define MII_DBG_GREENCFG 0x3B 1052 #define DBG_GREENCFG_DEFAULT 0x7078 1053 1054 #define MII_DBG_GREENCFG2 0x3D 1055 #define DBG_GREENCFG2_GATE_DFSE_EN 0x0080 1056 #define DBG_GREENCFG2_BP_GREEN 0x8000 1057 1058 /* Device addr 3 */ 1059 #define MII_EXT_PCS 3 1060 1061 #define MII_EXT_CLDCTL3 0x8003 1062 #define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000 1063 1064 #define MII_EXT_CLDCTL5 0x8005 1065 #define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000 1066 1067 #define MII_EXT_CLDCTL6 0x8006 1068 #define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF 1069 #define EXT_CLDCTL6_CAB_LEN_SHIFT 0 1070 #define EXT_CLDCTL6_CAB_LEN_SHORT1G 116 1071 #define EXT_CLDCTL6_CAB_LEN_SHORT100M 152 1072 1073 #define MII_EXT_VDRVBIAS 0x8062 1074 #define EXT_VDRVBIAS_DEFAULT 3 1075 1076 /* Device addr 7 */ 1077 #define MII_EXT_ANEG 7 1078 1079 #define MII_EXT_ANEG_LOCAL_EEEADV 0x3C 1080 #define ANEG_LOCA_EEEADV_100BT 0x0002 1081 #define ANEG_LOCA_EEEADV_1000BT 0x0004 1082 1083 #define MII_EXT_ANEG_AFE 0x801A 1084 #define ANEG_AFEE_10BT_100M_TH 0x0040 1085 1086 #define MII_EXT_ANEG_S3DIG10 0x8023 1087 #define ANEG_S3DIG10_SL 0x0001 1088 #define ANEG_S3DIG10_DEFAULT 0 1089 1090 #define MII_EXT_ANEG_NLP78 0x8027 1091 #define ANEG_NLP78_120M_DEFAULT 0x8A05 1092 1093 /* Statistics counters collected by the MAC. */ 1094 struct smb { 1095 /* Rx stats. */ 1096 uint32_t rx_frames; 1097 uint32_t rx_bcast_frames; 1098 uint32_t rx_mcast_frames; 1099 uint32_t rx_pause_frames; 1100 uint32_t rx_control_frames; 1101 uint32_t rx_crcerrs; 1102 uint32_t rx_lenerrs; 1103 uint32_t rx_bytes; 1104 uint32_t rx_runts; 1105 uint32_t rx_fragments; 1106 uint32_t rx_pkts_64; 1107 uint32_t rx_pkts_65_127; 1108 uint32_t rx_pkts_128_255; 1109 uint32_t rx_pkts_256_511; 1110 uint32_t rx_pkts_512_1023; 1111 uint32_t rx_pkts_1024_1518; 1112 uint32_t rx_pkts_1519_max; 1113 uint32_t rx_pkts_truncated; 1114 uint32_t rx_fifo_oflows; 1115 uint32_t rx_rrs_errs; 1116 uint32_t rx_alignerrs; 1117 uint32_t rx_bcast_bytes; 1118 uint32_t rx_mcast_bytes; 1119 uint32_t rx_pkts_filtered; 1120 /* Tx stats. */ 1121 uint32_t tx_frames; 1122 uint32_t tx_bcast_frames; 1123 uint32_t tx_mcast_frames; 1124 uint32_t tx_pause_frames; 1125 uint32_t tx_excess_defer; 1126 uint32_t tx_control_frames; 1127 uint32_t tx_deferred; 1128 uint32_t tx_bytes; 1129 uint32_t tx_pkts_64; 1130 uint32_t tx_pkts_65_127; 1131 uint32_t tx_pkts_128_255; 1132 uint32_t tx_pkts_256_511; 1133 uint32_t tx_pkts_512_1023; 1134 uint32_t tx_pkts_1024_1518; 1135 uint32_t tx_pkts_1519_max; 1136 uint32_t tx_single_colls; 1137 uint32_t tx_multi_colls; 1138 uint32_t tx_late_colls; 1139 uint32_t tx_excess_colls; 1140 uint32_t tx_underrun; 1141 uint32_t tx_desc_underrun; 1142 uint32_t tx_lenerrs; 1143 uint32_t tx_pkts_truncated; 1144 uint32_t tx_bcast_bytes; 1145 uint32_t tx_mcast_bytes; 1146 uint32_t updated; 1147 }; 1148 1149 /* CMB (Coalescing Message Block) */ 1150 struct cmb { 1151 uint32_t cons; 1152 }; 1153 1154 /* Rx free descriptor */ 1155 struct rx_desc { 1156 uint64_t addr; 1157 }; 1158 1159 /* Rx return descriptor */ 1160 struct rx_rdesc { 1161 uint32_t rdinfo; 1162 #define RRD_CSUM_MASK 0x0000FFFF 1163 #define RRD_RD_CNT_MASK 0x000F0000 1164 #define RRD_RD_IDX_MASK 0xFFF00000 1165 #define RRD_CSUM_SHIFT 0 1166 #define RRD_RD_CNT_SHIFT 16 1167 #define RRD_RD_IDX_SHIFT 20 1168 #define RRD_CSUM(x) \ 1169 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 1170 #define RRD_RD_CNT(x) \ 1171 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 1172 #define RRD_RD_IDX(x) \ 1173 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 1174 uint32_t rss; 1175 uint32_t vtag; 1176 #define RRD_VLAN_MASK 0x0000FFFF 1177 #define RRD_HEAD_LEN_MASK 0x00FF0000 1178 #define RRD_HDS_MASK 0x03000000 1179 #define RRD_HDS_NONE 0x00000000 1180 #define RRD_HDS_HEAD 0x01000000 1181 #define RRD_HDS_DATA 0x02000000 1182 #define RRD_CPU_MASK 0x0C000000 1183 #define RRD_HASH_FLAG_MASK 0xF0000000 1184 #define RRD_VLAN_SHIFT 0 1185 #define RRD_HEAD_LEN_SHIFT 16 1186 #define RRD_HDS_SHIFT 24 1187 #define RRD_CPU_SHIFT 26 1188 #define RRD_HASH_FLAG_SHIFT 28 1189 #define RRD_VLAN(x) \ 1190 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 1191 #define RRD_HEAD_LEN(x) \ 1192 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 1193 #define RRD_CPU(x) \ 1194 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 1195 uint32_t status; 1196 #define RRD_LEN_MASK 0x00003FFF 1197 #define RRD_LEN_SHIFT 0 1198 #define RRD_TCP_UDPCSUM_NOK 0x00004000 1199 #define RRD_IPCSUM_NOK 0x00008000 1200 #define RRD_VLAN_TAG 0x00010000 1201 #define RRD_PROTO_MASK 0x000E0000 1202 #define RRD_PROTO_IPV4 0x00020000 1203 #define RRD_PROTO_IPV6 0x000C0000 1204 #define RRD_ERR_SUM 0x00100000 1205 #define RRD_ERR_CRC 0x00200000 1206 #define RRD_ERR_ALIGN 0x00400000 1207 #define RRD_ERR_TRUNC 0x00800000 1208 #define RRD_ERR_RUNT 0x01000000 1209 #define RRD_ERR_ICMP 0x02000000 1210 #define RRD_BCAST 0x04000000 1211 #define RRD_MCAST 0x08000000 1212 #define RRD_SNAP_LLC 0x10000000 1213 #define RRD_ETHER 0x00000000 1214 #define RRD_FIFO_FULL 0x20000000 1215 #define RRD_ERR_LENGTH 0x40000000 1216 #define RRD_VALID 0x80000000 1217 #define RRD_BYTES(x) \ 1218 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 1219 #define RRD_IPV4(x) \ 1220 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 1221 }; 1222 1223 /* Tx descriptor */ 1224 struct tx_desc { 1225 uint32_t len; 1226 #define TD_BUFLEN_MASK 0x00003FFF 1227 #define TD_VLAN_MASK 0xFFFF0000 1228 #define TD_BUFLEN_SHIFT 0 1229 #define TX_BYTES(x) \ 1230 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 1231 #define TD_VLAN_SHIFT 16 1232 uint32_t flags; 1233 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 1234 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 1235 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 1236 #define TD_CUSTOM_CSUM 0x00000100 1237 #define TD_IPCSUM 0x00000200 1238 #define TD_TCPCSUM 0x00000400 1239 #define TD_UDPCSUM 0x00000800 1240 #define TD_TSO 0x00001000 1241 #define TD_TSO_DESCV1 0x00000000 1242 #define TD_TSO_DESCV2 0x00002000 1243 #define TD_CON_VLAN_TAG 0x00004000 1244 #define TD_INS_VLAN_TAG 0x00008000 1245 #define TD_IPV4_DESCV2 0x00010000 1246 #define TD_LLC_SNAP 0x00020000 1247 #define TD_ETHERNET 0x00000000 1248 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 1249 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 1250 #define TD_MSS_MASK 0x7FFC0000 1251 #define TD_EOP 0x80000000 1252 #define TD_L4HDR_OFFSET_SHIFT 0 1253 #define TD_TCPHDR_OFFSET_SHIFT 0 1254 #define TD_PLOAD_OFFSET_SHIFT 0 1255 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 1256 #define TD_MSS_SHIFT 18 1257 uint64_t addr; 1258 }; 1259 1260 #define ALC_TX_RING_CNT 256 1261 #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) 1262 #define ALC_RX_RING_CNT 256 1263 #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) 1264 #define ALC_RX_BUF_ALIGN 4 1265 #define ALC_RR_RING_CNT ALC_RX_RING_CNT 1266 #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) 1267 #define ALC_CMB_ALIGN 8 1268 #define ALC_SMB_ALIGN 8 1269 1270 #define ALC_TSO_MAXSEGSIZE 4096 1271 #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 1272 #define ALC_MAXTXSEGS 32 1273 1274 #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 1275 #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) 1276 1277 #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 1278 1279 /* Water mark to kick reclaiming Tx buffers. */ 1280 #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) 1281 /* 1282 * AR816x controllers support up to 16 messages but this driver 1283 * uses single message. 1284 */ 1285 #define ALC_MSI_MESSAGES 1 1286 #define ALC_MSIX_MESSAGES 1 1287 1288 #define ALC_TX_RING_SZ \ 1289 (sizeof(struct tx_desc) * ALC_TX_RING_CNT) 1290 #define ALC_RX_RING_SZ \ 1291 (sizeof(struct rx_desc) * ALC_RX_RING_CNT) 1292 #define ALC_RR_RING_SZ \ 1293 (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) 1294 #define ALC_CMB_SZ (sizeof(struct cmb)) 1295 #define ALC_SMB_SZ (sizeof(struct smb)) 1296 1297 #define ALC_PROC_MIN 16 1298 #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) 1299 #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) 1300 1301 /* 1302 * The number of bits reserved for MSS in AR813x/AR815x controllers 1303 * are 13 bits. This limits the maximum interface MTU size in TSO 1304 * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper 1305 * stack should not generate TCP segments with MSS greater than the 1306 * limit. Also Atheros says that maximum MTU for TSO is 6KB. 1307 */ 1308 #define ALC_TSO_MTU (6 * 1024) 1309 1310 struct alc_rxdesc { 1311 struct mbuf *rx_m; 1312 bus_dmamap_t rx_dmamap; 1313 struct rx_desc *rx_desc; 1314 }; 1315 1316 struct alc_txdesc { 1317 struct mbuf *tx_m; 1318 bus_dmamap_t tx_dmamap; 1319 }; 1320 1321 struct alc_ring_data { 1322 struct tx_desc *alc_tx_ring; 1323 bus_dma_segment_t alc_tx_ring_seg; 1324 bus_addr_t alc_tx_ring_paddr; 1325 struct rx_desc *alc_rx_ring; 1326 bus_dma_segment_t alc_rx_ring_seg; 1327 bus_addr_t alc_rx_ring_paddr; 1328 struct rx_rdesc *alc_rr_ring; 1329 bus_dma_segment_t alc_rr_ring_seg; 1330 bus_addr_t alc_rr_ring_paddr; 1331 struct cmb *alc_cmb; 1332 bus_dma_segment_t alc_cmb_seg; 1333 bus_addr_t alc_cmb_paddr; 1334 struct smb *alc_smb; 1335 bus_dma_segment_t alc_smb_seg; 1336 bus_addr_t alc_smb_paddr; 1337 }; 1338 1339 struct alc_chain_data { 1340 struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; 1341 struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; 1342 bus_dmamap_t alc_tx_ring_map; 1343 bus_dma_segment_t alc_tx_ring_seg; 1344 bus_dmamap_t alc_rx_ring_map; 1345 bus_dma_segment_t alc_rx_ring_seg; 1346 bus_dmamap_t alc_rr_ring_map; 1347 bus_dma_segment_t alc_rr_ring_seg; 1348 bus_dmamap_t alc_rx_sparemap; 1349 bus_dmamap_t alc_cmb_map; 1350 bus_dma_segment_t alc_cmb_seg; 1351 bus_dmamap_t alc_smb_map; 1352 bus_dma_segment_t alc_smb_seg; 1353 1354 int alc_tx_prod; 1355 int alc_tx_cons; 1356 int alc_tx_cnt; 1357 int alc_rx_cons; 1358 int alc_rr_cons; 1359 int alc_rxlen; 1360 1361 struct mbuf *alc_rxhead; 1362 struct mbuf *alc_rxtail; 1363 struct mbuf *alc_rxprev_tail; 1364 }; 1365 1366 struct alc_hw_stats { 1367 /* Rx stats. */ 1368 uint32_t rx_frames; 1369 uint32_t rx_bcast_frames; 1370 uint32_t rx_mcast_frames; 1371 uint32_t rx_pause_frames; 1372 uint32_t rx_control_frames; 1373 uint32_t rx_crcerrs; 1374 uint32_t rx_lenerrs; 1375 uint64_t rx_bytes; 1376 uint32_t rx_runts; 1377 uint32_t rx_fragments; 1378 uint32_t rx_pkts_64; 1379 uint32_t rx_pkts_65_127; 1380 uint32_t rx_pkts_128_255; 1381 uint32_t rx_pkts_256_511; 1382 uint32_t rx_pkts_512_1023; 1383 uint32_t rx_pkts_1024_1518; 1384 uint32_t rx_pkts_1519_max; 1385 uint32_t rx_pkts_truncated; 1386 uint32_t rx_fifo_oflows; 1387 uint32_t rx_rrs_errs; 1388 uint32_t rx_alignerrs; 1389 uint64_t rx_bcast_bytes; 1390 uint64_t rx_mcast_bytes; 1391 uint32_t rx_pkts_filtered; 1392 /* Tx stats. */ 1393 uint32_t tx_frames; 1394 uint32_t tx_bcast_frames; 1395 uint32_t tx_mcast_frames; 1396 uint32_t tx_pause_frames; 1397 uint32_t tx_excess_defer; 1398 uint32_t tx_control_frames; 1399 uint32_t tx_deferred; 1400 uint64_t tx_bytes; 1401 uint32_t tx_pkts_64; 1402 uint32_t tx_pkts_65_127; 1403 uint32_t tx_pkts_128_255; 1404 uint32_t tx_pkts_256_511; 1405 uint32_t tx_pkts_512_1023; 1406 uint32_t tx_pkts_1024_1518; 1407 uint32_t tx_pkts_1519_max; 1408 uint32_t tx_single_colls; 1409 uint32_t tx_multi_colls; 1410 uint32_t tx_late_colls; 1411 uint32_t tx_excess_colls; 1412 uint32_t tx_underrun; 1413 uint32_t tx_desc_underrun; 1414 uint32_t tx_lenerrs; 1415 uint32_t tx_pkts_truncated; 1416 uint64_t tx_bcast_bytes; 1417 uint64_t tx_mcast_bytes; 1418 }; 1419 1420 /* 1421 * Software state per device. 1422 */ 1423 struct alc_softc { 1424 struct device sc_dev; 1425 struct arpcom sc_arpcom; 1426 1427 bus_space_tag_t sc_mem_bt; 1428 bus_space_handle_t sc_mem_bh; 1429 bus_size_t sc_mem_size; 1430 bus_dma_tag_t sc_dmat; 1431 pci_chipset_tag_t sc_pct; 1432 pcitag_t sc_pcitag; 1433 pci_vendor_id_t sc_product; 1434 1435 void *sc_irq_handle; 1436 1437 struct mii_data sc_miibus; 1438 int alc_rev; 1439 int alc_chip_rev; 1440 int alc_phyaddr; 1441 uint8_t alc_eaddr[ETHER_ADDR_LEN]; 1442 uint32_t alc_max_framelen; 1443 uint32_t alc_dma_rd_burst; 1444 uint32_t alc_dma_wr_burst; 1445 uint32_t alc_rcb; 1446 int alc_expcap; 1447 int alc_flags; 1448 #define ALC_FLAG_PCIE 0x0001 1449 #define ALC_FLAG_PCIX 0x0002 1450 #define ALC_FLAG_PM 0x0010 1451 #define ALC_FLAG_FASTETHER 0x0020 1452 #define ALC_FLAG_JUMBO 0x0040 1453 #define ALC_FLAG_CMB_BUG 0x0100 1454 #define ALC_FLAG_SMB_BUG 0x0200 1455 #define ALC_FLAG_L0S 0x0400 1456 #define ALC_FLAG_L1S 0x0800 1457 #define ALC_FLAG_APS 0x1000 1458 #define ALC_FLAG_AR816X_FAMILY 0x2000 1459 #define ALC_FLAG_LINK_WAR 0x4000 1460 #define ALC_FLAG_LINK 0x8000 1461 #define ALC_FLAG_E2X00 0x10000 1462 1463 struct timeout alc_tick_ch; 1464 struct alc_hw_stats alc_stats; 1465 struct alc_chain_data alc_cdata; 1466 struct alc_ring_data alc_rdata; 1467 int alc_int_rx_mod; 1468 int alc_int_tx_mod; 1469 int alc_buf_size; 1470 }; 1471 1472 /* Register access macros. */ 1473 #define CSR_WRITE_4(_sc, reg, val) \ 1474 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 1475 #define CSR_WRITE_2(_sc, reg, val) \ 1476 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 1477 #define CSR_WRITE_1(_sc, reg, val) \ 1478 bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 1479 #define CSR_READ_2(_sc, reg) \ 1480 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 1481 #define CSR_READ_4(_sc, reg) \ 1482 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 1483 1484 #define ALC_RXCHAIN_RESET(_sc) \ 1485 do { \ 1486 (_sc)->alc_cdata.alc_rxhead = NULL; \ 1487 (_sc)->alc_cdata.alc_rxtail = NULL; \ 1488 (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ 1489 (_sc)->alc_cdata.alc_rxlen = 0; \ 1490 } while (0) 1491 1492 #define ALC_TX_TIMEOUT 5 1493 #define ALC_RESET_TIMEOUT 100 1494 #define ALC_TIMEOUT 1000 1495 #define ALC_PHY_TIMEOUT 1000 1496 1497 #define MASTER_WAKEN_25M 0x00000020 1498 #define ALC_FLAG_MSI 0x0004 1499 #define ALC_FLAG_MSIX 0x0008 1500 1501 #endif /* _IF_ALCREG_H */ 1502