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Searched refs:FADD (Results 1 – 25 of 73) sorted by relevance

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/openbsd/gnu/usr.bin/binutils-2.17/opcodes/
H A D	m88k-dis.c	176 …{0x84002800,"fadd.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FADD ,0,1,1,1,0… 177 …{0x84002880,"fadd.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 178 …{0x84002a00,"fadd.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 179 …{0x84002a80,"fadd.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 180 …{0x84002820,"fadd.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 181 …{0x840028a0,"fadd.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 182 …{0x84002a20,"fadd.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 183 …{0x84002aa0,"fadd.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0…
/openbsd/gnu/usr.bin/binutils/opcodes/
H A D	m88k-dis.c	181 …{0x84002800,"fadd.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FADD ,0,1,1,1,0… 182 …{0x84002880,"fadd.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 183 …{0x84002a00,"fadd.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 184 …{0x84002a80,"fadd.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 185 …{0x84002820,"fadd.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 186 …{0x840028a0,"fadd.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 187 …{0x84002a20,"fadd.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0… 188 …{0x84002aa0,"fadd.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0…
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A D	ConstrainedOps.def	`52 DAG_INSTRUCTION(FAdd, 2, 1, experimental_constrained_fadd, FADD) 100 // constrained FMA or FMUL + FADD intrinsics.`
/openbsd/gnu/gcc/gcc/config/sh/
H A D	sh4a.md	`175 ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG 205 ;; Double-precision floating-point (FADD,FMUL,FSUB)`
H A D	sh4.md	`394 ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG 433 ;; Double-precision floating-point (FADD,FMUL,FSUB)`
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A D	X86TargetTransformInfo.cpp	1041 { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd in getArithmeticInstrCost() 1095 { ISD::FADD, MVT::f64, { 1, 4, 1, 1 } }, // vaddsd in getArithmeticInstrCost() 1391 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // (x87) in getArithmeticInstrCost() 1419 case ISD::FADD: in getArithmeticInstrCost() 4941 { ISD::FADD, MVT::v2f64, 3 }, in getArithmeticReductionCost() 4946 { ISD::FADD, MVT::v2f64, 2 }, in getArithmeticReductionCost() 4947 { ISD::FADD, MVT::v2f32, 2 }, in getArithmeticReductionCost() 4948 { ISD::FADD, MVT::v4f32, 4 }, in getArithmeticReductionCost() 4962 { ISD::FADD, MVT::v4f64, 3 }, in getArithmeticReductionCost() 4963 { ISD::FADD, MVT::v4f32, 3 }, in getArithmeticReductionCost() [all …]
H A D	X86IntrinsicsInfo.h	`430 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND), 431 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND), 1004 X86_INTRINSIC_DATA(avx512fp16_add_ph_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),`
/openbsd/gnu/usr.bin/binutils/include/opcode/
H A D	m88k.h	`341 #define FADD NOP +1 macro`
/openbsd/gnu/usr.bin/binutils-2.17/include/opcode/
H A D	m88k.h	`342 #define FADD NOP +1 macro`
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A D	PPCSchedPredicates.td	`15 CheckOpcode<[FADD,`
/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A D	VVPNodes.def	`112 ADD_BINARY_VVP_OP_COMPACT(FADD) REGISTER_PACKED(VVP_FADD)`
/openbsd/gnu/llvm/llvm/docs/
H A D	AddingConstrainedIntrinsics.rst	`29 node FADD must be STRICT_FADD.`
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A D	ISDOpcodes.h	`390 FADD, enumerator`
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A D	SelectionDAGBuilder.cpp	5002 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2() 5018 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2() 5021 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2() 5039 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2() 5042 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2() 5045 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2() 5048 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2() 5051 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in getLimitedPrecisionExp2() 5117 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, in expandLog() 6474 SDValue Add = DAG.getNode(ISD::FADD, sdl, in visitIntrinsicCall() [all …]
H A D	LegalizeVectorOps.cpp	`327 case ISD::FADD: in LegalizeOp() 1487 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO)); in ExpandUINT_TO_FLOAT() 1508 TLI.isOperationLegalOrCustom(ISD::FADD, VT)) in ExpandFSUB()`
H A D	SelectionDAGBuilder.h	`545 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()`
H A D	LegalizeFloatTypes.cpp	`77 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult() 1222 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; in ExpandFloatResult() 1759 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, NewLo); in ExpandFloatRes_XINT_TO_FP() 2278 case ISD::FADD: in PromoteFloatResult() 2644 case ISD::FADD: in SoftPromoteHalfResult()`
H A D	DAGCombiner.cpp	1769 case ISD::FADD: return visitFADD(N); in visit() 15142 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; in visitFMULForFMADistributiveCombine() 15242 return DAG.getNode(ISD::FADD, DL, VT, N1, N0); in visitFADD() 15312 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD() 15368 if (N0.getOpcode() == ISD::FADD) { in visitFADD() 15379 if (N1.getOpcode() == ISD::FADD) { in visitFADD() 15391 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD() 15497 N1.getOpcode() == ISD::FADD) { in visitFSUB() 15509 return DAG.getNode(ISD::FADD, DL, VT, N0, NegN1); in visitFSUB() 15577 return DAG.getNode(ISD::FADD, DL, VT, N0, N0); in visitFMUL() [all …]
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A D	AMDGPUTargetTransformInfo.cpp	`578 if (OPC == ISD::FADD \|\| OPC == ISD::FSUB) { in getArithmeticInstrCost() 593 case ISD::FADD: in getArithmeticInstrCost()`
H A D	AMDGPUISelLowering.cpp	447 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in AMDGPUTargetLowering() 537 ISD::STORE, ISD::FADD, in AMDGPUTargetLowering() 561 case ISD::FADD: in fnegFoldsIntoOp() 2168 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL() 2244 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT() 2304 return DAG.getNode(ISD::FADD, SL, VT, T, Sel); in LowerFROUND() 2329 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR() 2557 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64() 3850 case ISD::FADD: { in performFNegCombine() 3868 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine() [all …]
/openbsd/gnu/usr.bin/binutils/gas/doc/
H A D	c-pdp11.texi	`100 @code{FADD}, @code{FDIV}, @code{FMUL}, and @code{FSUB}.`
/openbsd/gnu/usr.bin/binutils-2.17/gas/doc/
H A D	c-pdp11.texi	`100 @code{FADD}, @code{FDIV}, @code{FMUL}, and @code{FSUB}.`
/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/
H A D	NVPTXISelLowering.cpp	`563 setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::FADD, ISD::MUL, ISD::SHL, in NVPTXTargetLowering() 577 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) { in NVPTXTargetLowering() 2235 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign); in LowerFROUND32() 2266 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA, in LowerFROUND64() 4694 if (User->getOpcode() != ISD::FADD) in PerformADDCombineWithOperands() 5074 case ISD::FADD: in PerformDAGCombine()`
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A D	AArch64SchedFalkorDetails.td	`595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD\|FADD\|FSUB)v2f32$")>; 622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD\|FADD(P)?\|FSUB)(v2f64\|v4f32)$")>; 1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD\|FSUB)(S\|D)rr$")>;`
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A D	RISCVTargetTransformInfo.cpp	`1038 ISD != ISD::FADD) in getArithmeticReductionCost() 1359 case ISD::FADD: in getArithmeticInstrCost()`

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