1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxfpareg.h,v 1.3 2022/12/28 01:39:21 yasuoka Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 6.2 FPA Registers 38 */ 39 40 #ifndef _CN30XXFPAREG_H_ 41 #define _CN30XXFPAREG_H_ 42 43 /* ---- register offsets */ 44 45 #define FPA_INT_SUM 0x0001180028000040ULL 46 #define FPA_INT_ENB 0x0001180028000048ULL 47 #define FPA_CTL_STATUS 0x0001180028000050ULL 48 #define FPA_QUE0_AVAILABLE 0x0001180028000098ULL 49 #define FPA_QUE1_AVAILABLE 0x00011800280000a0ULL 50 #define FPA_QUE2_AVAILABLE 0x00011800280000a8ULL 51 #define FPA_QUE3_AVAILABLE 0x00011800280000b0ULL 52 #define FPA_QUE4_AVAILABLE 0x00011800280000b8ULL 53 #define FPA_QUE5_AVAILABLE 0x00011800280000c0ULL 54 #define FPA_QUE6_AVAILABLE 0x00011800280000c8ULL 55 #define FPA_QUE7_AVAILABLE 0x00011800280000d0ULL 56 #define FPA_WART_CTL 0x00011800280000d8ULL 57 #define FPA_WART_STATUS 0x00011800280000e0ULL 58 #define FPA_BIST_STATUS 0x00011800280000e8ULL 59 #define FPA_QUE0_PAGE_INDEX 0x00011800280000f0ULL 60 #define FPA_QUE1_PAGE_INDEX 0x00011800280000f8ULL 61 #define FPA_QUE2_PAGE_INDEX 0x0001180028000100ULL 62 #define FPA_QUE3_PAGE_INDEX 0x0001180028000108ULL 63 #define FPA_QUE4_PAGE_INDEX 0x0001180028000110ULL 64 #define FPA_QUE5_PAGE_INDEX 0x0001180028000118ULL 65 #define FPA_QUE6_PAGE_INDEX 0x0001180028000120ULL 66 #define FPA_QUE7_PAGE_INDEX 0x0001180028000128ULL 67 #define FPA_QUE_EXP 0x0001180028000130ULL 68 #define FPA_QUE_ACT 0x0001180028000138ULL 69 70 /* ---- register bit definitions */ 71 72 #define FPA_INT_SUM_XXX_63_28 0xfffffffff0000000ULL 73 #define FPA_INT_SUM_Q7_PERR 0x0000000008000000ULL 74 #define FPA_INT_SUM_Q7_COFF 0x0000000004000000ULL 75 #define FPA_INT_SUM_Q7_UND 0x0000000002000000ULL 76 #define FPA_INT_SUM_Q6_PERR 0x0000000001000000ULL 77 #define FPA_INT_SUM_Q6_COFF 0x0000000000800000ULL 78 #define FPA_INT_SUM_Q6_UND 0x0000000000400000ULL 79 #define FPA_INT_SUM_Q5_PERR 0x0000000000200000ULL 80 #define FPA_INT_SUM_Q5_COFF 0x0000000000100000ULL 81 #define FPA_INT_SUM_Q5_UND 0x0000000000080000ULL 82 #define FPA_INT_SUM_Q4_PERR 0x0000000000040000ULL 83 #define FPA_INT_SUM_Q4_COFF 0x0000000000020000ULL 84 #define FPA_INT_SUM_Q4_UND 0x0000000000010000ULL 85 #define FPA_INT_SUM_Q3_PERR 0x0000000000008000ULL 86 #define FPA_INT_SUM_Q3_COFF 0x0000000000004000ULL 87 #define FPA_INT_SUM_Q3_UND 0x0000000000002000ULL 88 #define FPA_INT_SUM_Q2_PERR 0x0000000000001000ULL 89 #define FPA_INT_SUM_Q2_COFF 0x0000000000000800ULL 90 #define FPA_INT_SUM_Q2_UND 0x0000000000000400ULL 91 #define FPA_INT_SUM_Q1_PERR 0x0000000000000200ULL 92 #define FPA_INT_SUM_Q1_COFF 0x0000000000000100ULL 93 #define FPA_INT_SUM_Q1_UND 0x0000000000000080ULL 94 #define FPA_INT_SUM_Q0_PERR 0x0000000000000040ULL 95 #define FPA_INT_SUM_Q0_COFF 0x0000000000000020ULL 96 #define FPA_INT_SUM_Q0_UND 0x0000000000000010ULL 97 #define FPA_INT_SUM_FED1_DBE 0x0000000000000008ULL 98 #define FPA_INT_SUM_FED1_SBE 0x0000000000000004ULL 99 #define FPA_INT_SUM_FED0_DBE 0x0000000000000002ULL 100 #define FPA_INT_SUM_FED0_SBE 0x0000000000000001ULL 101 102 #define FPA_INT_ENB_XXX_63_28 0xfffffffff0000000ULL 103 #define FPA_INT_ENB_Q7_PERR 0x0000000008000000ULL 104 #define FPA_INT_ENB_Q7_COFF 0x0000000004000000ULL 105 #define FPA_INT_ENB_Q7_UND 0x0000000002000000ULL 106 #define FPA_INT_ENB_Q6_PERR 0x0000000001000000ULL 107 #define FPA_INT_ENB_Q6_COFF 0x0000000000800000ULL 108 #define FPA_INT_ENB_Q6_UND 0x0000000000400000ULL 109 #define FPA_INT_ENB_Q5_PERR 0x0000000000200000ULL 110 #define FPA_INT_ENB_Q5_COFF 0x0000000000100000ULL 111 #define FPA_INT_ENB_Q5_UND 0x0000000000080000ULL 112 #define FPA_INT_ENB_Q4_PERR 0x0000000000040000ULL 113 #define FPA_INT_ENB_Q4_COFF 0x0000000000020000ULL 114 #define FPA_INT_ENB_Q4_UND 0x0000000000010000ULL 115 #define FPA_INT_ENB_Q3_PERR 0x0000000000008000ULL 116 #define FPA_INT_ENB_Q3_COFF 0x0000000000004000ULL 117 #define FPA_INT_ENB_Q3_UND 0x0000000000002000ULL 118 #define FPA_INT_ENB_Q2_PERR 0x0000000000001000ULL 119 #define FPA_INT_ENB_Q2_COFF 0x0000000000000800ULL 120 #define FPA_INT_ENB_Q2_UND 0x0000000000000400ULL 121 #define FPA_INT_ENB_Q1_PERR 0x0000000000000200ULL 122 #define FPA_INT_ENB_Q1_COFF 0x0000000000000100ULL 123 #define FPA_INT_ENB_Q1_UND 0x0000000000000080ULL 124 #define FPA_INT_ENB_Q0_PERR 0x0000000000000040ULL 125 #define FPA_INT_ENB_Q0_COFF 0x0000000000000020ULL 126 #define FPA_INT_ENB_Q0_UND 0x0000000000000010ULL 127 #define FPA_INT_ENB_FED1_DBE 0x0000000000000008ULL 128 #define FPA_INT_ENB_FED1_SBE 0x0000000000000004ULL 129 #define FPA_INT_ENB_FED0_DBE 0x0000000000000002ULL 130 #define FPA_INT_ENB_FED0_SBE 0x0000000000000001ULL 131 132 #define FPA_CTL_STATUS_XXX_63_18 0xfffffffffffc0000ULL 133 #define FPA_CTL_STATUS_RESET 0x0000000000020000ULL 134 #define FPA_CTL_STATUS_USE_LDT 0x0000000000010000ULL 135 #define FPA_CTL_STATUS_USE_STT 0x0000000000008000ULL 136 #define FPA_CTL_STATUS_ENB 0x0000000000004000ULL 137 #define FPA_CTL_STATUS_MEM1_ERR 0x0000000000003f80ULL 138 #define FPA_CTL_STATUS_MEM0_ERR 0x000000000000007fULL 139 140 #define FPA_QUEX_AVAILABLE_XXX_63_29 0xffffffffe0000000ULL 141 #define FPA_QUEX_AVAILABLE_QUE_SIZ 0x000000001fffffffULL 142 143 #define FPA_WART_CTL_XXX_63_16 0xffffffffffff0000ULL 144 #define FPA_WART_CTL_CTL 0x000000000000ffffULL 145 146 #define FPA_WART_STATUS_XXX_63_32 0xffffffff00000000ULL 147 #define FPA_WART_STATUS_STATUS 0x00000000ffffffffULL 148 149 #define FPA_BIST_STATUS_XXX_63_5 0xffffffffffffffe0ULL 150 #define FPA_BIST_STATUS_FRD 0x0000000000000010ULL 151 #define FPA_BIST_STATUS_FPF0 0x0000000000000008ULL 152 #define FPA_BIST_STATUS_FPF1 0x0000000000000004ULL 153 #define FPA_BIST_STATUS_FFR 0x0000000000000002ULL 154 #define FPA_BIST_STATUS_FDR 0x0000000000000001ULL 155 156 #define FPA_QUEX_PAGE_INDEX_XXX_63_25 0xfffffffffe000000ULL 157 #define FPA_QUEX_PAGE_INDEX_PG_NUM 0x0000000001ffffffULL 158 159 #define FPA_QUE_EXP_XXX_63_32 0xffffffff00000000ULL 160 #define FPA_QUE_EXP_XXX_31_29 0x00000000e0000000ULL 161 #define FPA_QUE_EXP_EXP_QUE 0x000000001c000000ULL 162 #define FPA_QUE_EXP_EXP_INDX 0x0000000003ffffffULL 163 164 #define FPA_QUE_ACT_XXX_63_32 0xffffffff00000000ULL 165 #define FPA_QUE_ACT_XXX_31_29 0x00000000e0000000ULL 166 #define FPA_QUE_ACT_ACT_QUE 0x000000001c000000ULL 167 #define FPA_QUE_ACT_ACT_INDX 0x0000000003ffffffULL 168 169 /* ---- operations */ 170 171 /* 172 * 6.1 Free Pool Unit Operations 173 */ 174 175 #define FPA_MAJORDID 0x5 /* 0b00101 */ 176 177 #define FPA_OPS_MAJORDID 0x0000f80000000000ULL 178 #define FPA_OPS_MAJORDID_SHIFT 43 179 #define FPA_OPS_SUBDID 0x0000070000000000ULL 180 #define FPA_OPS_SUBDID_SHIFT 40 181 #define FPA_OPS_XXX_39_0 0x000000ffffffffffULL 182 183 /* 6.1.1 Load Operations */ 184 185 #define FPA_OPS_LOAD_1 0x0001000000000000ULL 186 #define FPA_OPS_LOAD_MAJORDID 0x0000f80000000000ULL 187 #define FPA_OPS_LOAD_SUBDID 0x0000070000000000ULL 188 #define FPA_OPS_LOAD_XXX_39_0 0x000000ffffffffffULL 189 190 /* 6.1.2 IOBDMA Operations */ 191 192 #define FPA_OPS_IOBDMA_SRCADDR 0xff00000000000000ULL 193 #define FPA_OPS_IOBDMA_LEN 0x00ff000000000000ULL 194 #define FPA_OPS_IOBDMA_LEN_SHIFT 48 195 #define FPA_OPS_IOBDMA_MAJORDID 0x0000f80000000000ULL 196 #define FPA_OPS_IOBDMA_SUBDIR 0x0000070000000000ULL 197 #define FPA_OPS_IOBDMA_XXX_39_0 0x000000ffffffffffULL 198 199 /* 6.1.3 Store Operations */ 200 201 #define FPA_OPS_STORE_1 0x0001000000000000ULL 202 #define FPA_OPS_STORE_MAJORDID 0x0000f80000000000ULL 203 #define FPA_OPS_STORE_SUBDID 0x0000070000000000ULL 204 #define FPA_OPS_STORE_XXX_39_0 0x000000ffffffffffULL 205 206 #define FPA_OPS_STORE_DATA_XXX_63_9 0xfffffffffffffe00ULL 207 #define FPA_OPS_STORE_DATA_DWBCOUNT 0x00000000000001ffULL 208 209 /* ---- bus_space(9) */ 210 211 #define FPA_BASE 0x0001180028000000ULL 212 #define FPA_SIZE 0x0200 213 214 #define FPA_INT_SUM_OFFSET 0x0040 215 #define FPA_INT_ENB_OFFSET 0x0048 216 #define FPA_CTL_STATUS_OFFSET 0x0050 217 #define FPA_QUE0_AVAILABLE_OFFSET 0x0098 218 #define FPA_QUE1_AVAILABLE_OFFSET 0x00a0 219 #define FPA_QUE2_AVAILABLE_OFFSET 0x00a8 220 #define FPA_QUE3_AVAILABLE_OFFSET 0x00b0 221 #define FPA_QUE4_AVAILABLE_OFFSET 0x00b8 222 #define FPA_QUE5_AVAILABLE_OFFSET 0x00c0 223 #define FPA_QUE6_AVAILABLE_OFFSET 0x00c8 224 #define FPA_QUE7_AVAILABLE_OFFSET 0x00d0 225 #define FPA_WART_CTL_OFFSET 0x00d8 226 #define FPA_WART_STATUS_OFFSET 0x00e0 227 #define FPA_BIST_STATUS_OFFSET 0x00e8 228 #define FPA_QUE0_PAGE_INDEX_OFFSET 0x00f0 229 #define FPA_QUE1_PAGE_INDEX_OFFSET 0x00f8 230 #define FPA_QUE2_PAGE_INDEX_OFFSET 0x0100 231 #define FPA_QUE3_PAGE_INDEX_OFFSET 0x0108 232 #define FPA_QUE4_PAGE_INDEX_OFFSET 0x0110 233 #define FPA_QUE5_PAGE_INDEX_OFFSET 0x0118 234 #define FPA_QUE6_PAGE_INDEX_OFFSET 0x0120 235 #define FPA_QUE7_PAGE_INDEX_OFFSET 0x0128 236 #define FPA_QUE_EXP_OFFSET 0x0130 237 #define FPA_QUE_ACT_OFFSET 0x0138 238 239 /* XXXX not use bit field */ 240 /** 241 * cvmx_fpa_ctl_status 242 * 243 * FPA_CTL_STATUS = FPA's Control/Status Register 244 * 245 * The FPA's interrupt enable register. 246 */ 247 248 #if 0 249 250 #ifndef MIPS_SPACE 251 #define MIPS_SPACE 252 typedef enum { 253 MIPS_SPACE_XKSEG = 3LL, 254 MIPS_SPACE_XKPHYS = 2LL, 255 MIPS_SPACE_XSSEG = 1LL, 256 MIPS_SPACE_XUSEG = 0LL 257 } mips_space_t; 258 #endif 259 260 typedef enum { 261 MIPS_XKSEG_SPACE_KSEG0 = 0LL, 262 MIPS_XKSEG_SPACE_KSEG1 = 1LL, 263 MIPS_XKSEG_SPACE_SSEG = 2LL, 264 MIPS_XKSEG_SPACE_KSEG3 = 3LL 265 } mips_xkseg_space_t; 266 267 // decodes <14:13> of a kseg3 window address 268 typedef enum { 269 OCTEON_ADD_WIN_SCR = 0L, 270 OCTEON_ADD_WIN_DMA = 1L, // see cvmx_add_win_dma_dec_t for further decode 271 OCTEON_ADD_WIN_UNUSED = 2L, 272 OCTEON_ADD_WIN_UNUSED2 = 3L 273 } octeon_add_win_dec_t; 274 275 // decode within DMA space 276 typedef enum { 277 OCTEON_ADD_WIN_DMA_ADD = 0L, // add store data to the write buffer entry, allocating it if necessary 278 OCTEON_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM 279 // store data must be normal DRAM memory space address in this case 280 OCTEON_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command 281 // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents 282 OCTEON_ADD_WIN_DMA_SENDIO = 3L, // send out the write buffer entry as an IO write 283 // store data must be normal IO space address in this case 284 OCTEON_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus 285 // no write buffer data needed/used 286 } octeon_add_win_dma_dec_t; 287 288 289 typedef union { 290 291 uint64_t u64; 292 293 struct { 294 mips_space_t R : 2; 295 uint64_t offset :62; 296 } sva; // mapped or unmapped virtual address 297 298 struct { 299 uint64_t zeroes :33; 300 uint64_t offset :31; 301 } suseg; // mapped USEG virtual addresses (typically) 302 303 struct { 304 uint64_t ones :33; 305 mips_xkseg_space_t sp : 2; 306 uint64_t offset :29; 307 } sxkseg; // mapped or unmapped virtual address 308 309 struct { 310 mips_space_t R : 2; // CVMX_MIPS_SPACE_XKPHYS in this case 311 uint64_t cca : 3; // ignored by octeon 312 uint64_t mbz :10; 313 uint64_t pa :49; // physical address 314 } sxkphys; // physical address accessed through xkphys unmapped virtual address 315 316 struct { 317 uint64_t mbz :15; 318 uint64_t is_io : 1; // if set, the address is uncached and resides on MCB bus 319 uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID 320 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I 321 uint64_t offset :36; 322 } sphys; // physical address 323 324 struct { 325 uint64_t zeroes :24; // techically, <47:40> are dont-cares 326 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I 327 uint64_t offset :36; 328 } smem; // physical mem address 329 330 struct { 331 uint64_t mem_region :2; 332 uint64_t mbz :13; 333 uint64_t is_io : 1; // 1 in this case 334 uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID 335 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I 336 uint64_t offset :36; 337 } sio; // physical IO address 338 339 struct { 340 uint64_t ones : 49; 341 octeon_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_SCR (0) in this case 342 uint64_t addr : 13; 343 } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3 344 // there should only be stores to IOBDMA space, no loads 345 struct { 346 uint64_t ones : 49; 347 octeon_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_DMA (1) in this case 348 uint64_t unused2: 3; 349 octeon_add_win_dma_dec_t type : 3; 350 uint64_t addr : 7; 351 } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3 352 353 struct { 354 uint64_t didspace : 24; 355 uint64_t unused : 40; 356 } sfilldidspace; 357 358 } cn30xxfpa_addr_t; 359 360 #endif 361 362 #endif /* _CN30XXFPAREG_H_ */ 363