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Searched refs:FPRegs (Results 1 – 8 of 8) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td86 def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>;
88 def FONES : VISInstD<0b001111111, "fones", FPRegs>;
90 def FSRC1S : VISInst1<0b001110101, "fsrc1s", FPRegs>;
92 def FSRC2S : VISInst2<0b001111001, "fsrc2s", FPRegs>;
94 def FNOT1S : VISInst1<0b001101011, "fnot1s", FPRegs>;
96 def FNOT2S : VISInst2<0b001100111, "fnot2s", FPRegs>;
98 def FORS : VISInst<0b001111101, "fors", FPRegs>;
100 def FNORS : VISInst<0b001100011, "fnors", FPRegs>;
102 def FANDS : VISInst<0b001110001, "fands", FPRegs>;
104 def FNANDS : VISInst<0b001101111, "fnands", FPRegs>;
[all …]
H A DSparcInstrInfo.td521 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
542 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
565 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
1197 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1214 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1263 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1266 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1301 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1317 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1335 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
[all …]
H A DSparcInstr64Bit.td338 def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
339 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
407 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2, FPRegs:$f, RegCCOp:$rcond),
428 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
430 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
442 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
444 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;
H A DSparcInstrAliases.td32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
55 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
78 (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
560 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
565 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
H A DSparcRegisterInfo.td351 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
355 // The Low?FPRegs classes are used only for inline-asm constraints.
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp2094 SmallVector<CalleeSavedInfo, 18> FPRegs; in processFunctionBeforeFrameFinalized() local
2121 FPRegs.push_back(I); in processFunctionBeforeFrameFinalized()
2160 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { in processFunctionBeforeFrameFinalized()
2161 int FI = FPRegs[i].getFrameIdx(); in processFunctionBeforeFrameFinalized()
/openbsd/gnu/llvm/libunwind/src/
H A DUnwindCursor.hpp2377 double *FPRegs = reinterpret_cast<double *>( in stepWithTBTable() local
2381 32 - TBTable->tb.fpr_saved + i + unwPPCF0Index, FPRegs[i]); in stepWithTBTable()
2384 ptrToRegs = reinterpret_cast<char *>(FPRegs); in stepWithTBTable()
/openbsd/gnu/llvm/llvm/docs/
H A DWritingAnLLVMBackend.rst529 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
530 first argument defines the namespace with the string "``SP``". ``FPRegs``
538 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;