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Searched refs:FirstReg (Results 1 – 12 of 12) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp382 Register FirstReg; in CreateRegs() local
390 if (!FirstReg) FirstReg = R; in CreateRegs()
393 return FirstReg; in CreateRegs()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp494 unsigned FirstReg = 0; in ScanInstruction() local
500 if (FirstReg != 0) { in ScanInstruction()
502 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
505 FirstReg = Reg; in ScanInstruction()
509 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/openbsd/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3407 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3424 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3573 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
4401 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4409 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
5327 unsigned SecondReg = nextReg(FirstReg); in expandLoadStoreDMacro()
5332 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandLoadStoreDMacro()
5346 if (FirstReg != BaseReg || !IsLoad) { in expandLoadStoreDMacro()
5374 unsigned SecondReg = nextReg(FirstReg); in expandStoreDM1Macro()
5379 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandStoreDM1Macro()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1662 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1663 Reg = FirstReg; in printVectorList()
1664 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1665 Reg = FirstReg; in printVectorList()
1666 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1667 Reg = FirstReg; in printVectorList()
1668 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) in printVectorList() local
1669 Reg = FirstReg; in printVectorList()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord() argument
2317 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2319 if (FirstReg == SecondReg) in CanFormLdStDWord()
2420 Register FirstReg, SecondReg; in RescheduleOps() local
2428 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2435 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2441 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2455 .addReg(FirstReg) in RescheduleOps()
2473 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2474 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4361 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4393 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4419 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4433 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4482 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4556 unsigned FirstReg = 0; in HandleByVal() local
4572 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
4578 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) { in HandleByVal()
4579 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); in HandleByVal()
4580 ++FirstReg; in HandleByVal()
[all …]
H A DMipsISelLowering.h575 const Argument *FuncArg, unsigned FirstReg,
584 unsigned FirstReg, unsigned LastReg,
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1787 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
4385 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
4386 auto ParseRes = ParseMatrixTile(FirstReg, ElementWidth); in tryParseMatrixTileList()
4394 unsigned PrevReg = FirstReg; in tryParseMatrixTileList()
4400 SeenRegs.insert(FirstReg); in tryParseMatrixTileList()
4481 MCRegister FirstReg; in tryParseVectorList() local
4492 int64_t PrevReg = FirstReg; in tryParseVectorList()
7713 MCRegister FirstReg; in tryParseGPRSeqPair() local
7726 bool isXReg = XRegClass.contains(FirstReg), in tryParseGPRSeqPair()
7727 isWReg = WRegClass.contains(FirstReg); in tryParseGPRSeqPair()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1634 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
1640 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1641 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1643 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1645 Register OldFirstReg = FirstReg; in insertSelect()
1646 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
1647 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
1652 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
H A DPPCISelLowering.cpp6790 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
6792 assert(FirstReg && SecondReg && in CC_AIX()
6795 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo)); in CC_AIX()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2551 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
2559 FirstReg = Count - 1; in computeCalleeSaveRegisterPairs()
2565 for (unsigned i = FirstReg; i < Count; i += RegInc) { in computeCalleeSaveRegisterPairs()
2585 bool IsFirst = i == FirstReg; in computeCalleeSaveRegisterPairs()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4774 unsigned FirstReg = Reg; in parseVectorList() local
4783 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
4937 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4941 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); in parseVectorList()
4945 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()