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Searched refs:GENFC_WT__VSYNC_SEL_W_MASK (Results 1 – 18 of 18) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7155 #define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L macro
H A Ddce_8_0_sh_mask.h10633 #define GENFC_WT__VSYNC_SEL_W_MASK 0x8 macro
H A Ddce_10_0_sh_mask.h11017 #define GENFC_WT__VSYNC_SEL_W_MASK 0x8 macro
H A Ddce_11_0_sh_mask.h10829 #define GENFC_WT__VSYNC_SEL_W_MASK 0x8 macro
H A Ddce_11_2_sh_mask.h12083 #define GENFC_WT__VSYNC_SEL_W_MASK 0x8 macro
H A Ddce_12_0_sh_mask.h2183 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h220 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_1_0_sh_mask.h822 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_0_1_sh_mask.h317 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4418 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_1_2_sh_mask.h317 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5123 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7772 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_1_6_sh_mask.h330 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_0_2_sh_mask.h233 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_2_0_0_sh_mask.h233 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_0_0_sh_mask.h214 #define GENFC_WT__VSYNC_SEL_W_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4417 #define GENFC_WT__VSYNC_SEL_W_MASK … macro