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Searched refs:HW (Results 1 – 25 of 33) sorted by relevance

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/openbsd/gnu/llvm/compiler-rt/lib/builtins/
H A Dfp_div_impl.inc27 #define HW (typeWidth / 2)
29 #define loMask (REP_C(-1) >> HW)
129 // <= abs(e_n) + 2 * 2^-HW
157 // so x0 fits to UQ0.HW without wrapping.
190 // Now, we should multiply UQ0.HW and UQ1.(HW-1) numbers, naturally
232 rep_t x_UQ0 = (rep_t)x_UQ0_hw << HW;
264 // x_UQ0 = x_UQ0_hw * 2^HW - 1
265 // x_UQ0 * b_UQ1 = (x_UQ0_hw * 2^HW) * (b_UQ1_hw * 2^HW + blo) - b_UQ1
276 rep_t hi_corr = corr_UQ1 >> HW;
277 // x_UQ0 * corr_UQ1 = (x_UQ0_hw * 2^HW) * (hi_corr * 2^HW + lo_corr) - corr_UQ1
[all …]
/openbsd/gnu/llvm/llvm/lib/DebugInfo/PDB/Native/
H A DTpiStreamBuilder.cpp197 BinaryStreamWriter HW(*HVS); in commit() local
199 if (auto EC = HW.writeStreamRef(*HashValueStream)) in commit()
204 if (auto EC = HW.writeObject(IndexOffset)) in commit()
/openbsd/regress/lib/libcrypto/x509/bettertls/certificates/
H A D133.crt17 HW/avX0wjyWpsdlwBkckbUK8zAb3TBxxrX0nxpkx/H++Soaq73XsbZGyENJOHRW1
H A D3136.crt11 JU54tjUtZJAaRf0YbC3MABKd/NWG0tkYRRbqTqe109ruZ8OhSQD4maYOLU1nE/HW
H A D1337.key13 LGy4IKECgYEAxb6899zXkMNepsWE5bmOtIYEysBrojqvHX9ZeHXlLC2phaE/HW+K
H A D167.key4 HW+1YscNS0ikr8amvdy3OD1+Bbb/HsQU2niLLfuUGQ2WMTK7GOtU5nIJsuMK8QdQ
H A D312.key22 68ajDw62TmlCUwY11q1rNIwi+6IY9V4hMp0Kwod3r4rDrqoCNW9g4yTIJ6Gsr+HW
H A D2654.chain19 cYGmdfMHCQT2QlTzSxTehNElfOYKXWvv2BeCPdh/BLjsuSqCzaUrCYU5pcHK7/HW
/openbsd/gnu/llvm/compiler-rt/lib/orc/tests/unit/
H A Dsimple_packed_serialization_test.cpp129 const char *HW = "Hello, world!"; in TEST() local
130 blobSerializationRoundTrip<SPSString, std::string_view>(std::string_view(HW)); in TEST()
/openbsd/sys/dev/pci/drm/amd/display/
H A DTODO66 overy complicated HW programming function for sendind and receiving i2c/aux
68 HW blocks.
107 bypassing the i2c device and goes directly to HW. This should be changed.
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td500 def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>;
501 def : InstRW<[P5600WriteMSALongInt], (instregex "^MADD_Q_[HW]$")>;
502 def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>;
503 def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>;
504 def : InstRW<[P5600WriteMSALongInt], (instregex "^MULR_Q_[HW]$")>;
505 def : InstRW<[P5600WriteMSALongInt], (instregex "^MUL_Q_[HW]$")>;
H A DMipsScheduleGeneric.td1579 def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>;
1580 def : InstRW<[GenericWriteMSALongInt], (instregex "^MADD_Q_[HW]$")>;
1581 def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>;
1582 def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>;
1583 def : InstRW<[GenericWriteMSALongInt], (instregex "^MULR_Q_[HW]$")>;
1584 def : InstRW<[GenericWriteMSALongInt], (instregex "^MUL_Q_[HW]$")>;
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td444 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
447 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
451 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
452 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedKryoDetails.td1510 (instregex "LDRS(BW|BX|HW|HX|W)ui")>;
1516 (instregex "LDRS(BW|BX|HW|HX|W)ro(W|X)")>;
1522 (instregex "LDRS(BW|BX|HW|HX|W)(post|pre)")>;
1540 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
H A DAArch64SchedAmpere1.td966 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
970 (instregex "LDURS(BW|BX|HW|HX|W)i")>;
H A DAArch64SchedNeoverseN2.td2146 (instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED_REAL$",
2231 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",
2239 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[HW]_D_SCALED$",
/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVEInstrFormats.td46 /// VLIndex is the index of VL register in MI's operands. The HW instruction
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td32 // TODO - tune this on real HW once it arrives. For now, we will use the same
H A DP9InstrResources.td406 (instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?(O)?$")
/openbsd/gnu/llvm/llvm/include/llvm/Target/
H A DTarget.td22 // A string representing subtarget features that turn on this HW mode.
36 // A class used to associate objects with HW modes. It is only intended to
46 // dependent on a HW mode. This class inherits from ValueType itself,
64 // The register size/alignment information, parameterized by a HW mode.
224 // The register size/alignment information, parameterized by a HW mode.
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARM.td36 // Floating Point, HW Division and Neon Support
441 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DVOP3PInstructions.td462 // actual HW restriction. In particular earlyclobber also affects src0 and
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86SchedHaswell.td20 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsics.td545 // caused by HW exceptions under option -EHa.

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